gmane.linux.ports.mips.general

[PATCH] MIPS: Properly align the .data..init_task section.

David Daney — 2012-05-25T23:25:34

From: David Daney <david.daney< at >cavium.com>

Improper alignment can lead to unbootable systems and/or random
crashes.

Signed-off-by: David Daney <david.daney< at >cavium.com>
Cc: <stable< at >vger.kernel.org>
---
 arch/mips/include/asm/thread_info.h |    4 ++--
 arch/mips/kernel/vmlinux.lds.S      |    3 ++-
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h
index e2eca7d..ca97e0e 100644
--- a/arch/mips/include/asm/thread_info.h
+++ b/arch/mips/include/asm/thread_info.h
< at >< at > -60,6 +60,8 < at >< at > struct thread_info {
 register struct thread_info *__current_thread_info __asm__("$28");
 #define current_thread_info()  __current_thread_info
 
+#endif /* !__ASSEMBLY__ */
+
 /* thread information allocation */
 #if defined(CONFIG_PAGE_SIZE_4KB) && defined(CONFIG_32BIT)
 #define THREAD_SIZE_ORDER (1)
< at >< at > -85,8 +87,6 < at >< at > register struct thread_info *__current_thread_info __asm__("$28");
 
 #define STACK_WARN(THREAD_SIZE / 8)
 
-#endif /* !__ASSEMBLY_

[PATCH v2] Update all configuration files for new features.

Steven J. Hill — 2012-05-24T21:03:23

From: "Steven J. Hill" <sjhill< at >mips.com>

Signed-off-by: Steven J. Hill <sjhill< at >mips.com>
---
 arch/mips/configs/malta_defconfig     | 1793 ++++++++++++++++++++++++++++++++-
 arch/mips/configs/maltaaprp_defconfig | 1739 ++++++++++++++++++++++++++++++++
 arch/mips/configs/maltasmtc_defconfig | 1746 ++++++++++++++++++++++++++++++++
 arch/mips/configs/maltasmvp_defconfig | 1750 ++++++++++++++++++++++++++++++++
 arch/mips/configs/maltaup_defconfig   | 1734 +++++++++++++++++++++++++++++++
 5 files changed, 8730 insertions(+), 32 deletions(-)
 create mode 100644 arch/mips/configs/maltaaprp_defconfig
 create mode 100644 arch/mips/configs/maltasmtc_defconfig
 create mode 100644 arch/mips/configs/maltasmvp_defconfig
 create mode 100644 arch/mips/configs/maltaup_defconfig

diff --git a/arch/mips/configs/malta_defconfig b/arch/mips/configs/malta_defconfig
index 5527abb..d412195 100644
--- a/arch/mips/configs/malta_defconfig
+++ b/arch/mips/configs/malta_defconfig
< at >< at > -1,58 +1,465 < at >< at >
+#
+# Automatically generated file; D

[PATCH 0/4] Optimise core MIPS library functions for microMIPS.

Steven J. Hill — 2012-05-24T20:55:38

From: "Steven J. Hill" <sjhill< at >mips.com>

Steven J. Hill (4):
  MIPS: Optimise core library function 'memset' for microMIPS.
  MIPS: Optimise core library function 'strncpy' for microMIPS.
  MIPS: Optimise core library function 'strlen' for microMIPS.
  MIPS: Optimise core library function 'strnlen' for microMIPS.

 arch/mips/include/asm/asm.h  |    2 +
 arch/mips/lib/memset.S       |   84 +++++++++++++++++++++++++++---------------
 arch/mips/lib/strlen_user.S  |    9 +++--
 arch/mips/lib/strncpy_user.S |   28 +++++++-------
 arch/mips/lib/strnlen_user.S |    2 +-
 5 files changed, 77 insertions(+), 48 deletions(-)

[PATCH 0/9] Add support for pure microMIPS kernel.

Steven J. Hill — 2012-05-24T20:45:57

From: "Steven J. Hill" <sjhill< at >mips.com>

This set of patches is to support building a pure microMIPS kernel
image using only instruction from the microMIPS ISA. The result is
a kernel binary reduction of more than 20% and an increase in the
speed of execution due to the smaller and faster instructions.

Steven J. Hill (9):
  MIPS: Add microMIPS breakpoints and DSP support.
  MIPS: Add support for microMIPS instructions.
  MIPS: Add support for microMIPS exception handling.
  MIPS: Support microMIPS/MIPS16e handling of delay slots.
  MIPS: Support microMIPS/MIPS16e unaligned accesses.
  MIPS: Support microMIPS/MIPS16e floating point.
  MIPS: Work-around microMIPS GNU assembler bug.
  MIPS: Fixup ordering of micro assembler instructions.
  MIPS: Add microMIPS configuration option.

 arch/mips/Kconfig                      |   10 +
 arch/mips/Makefile                     |    1 +
 arch/mips/configs/sead3_defconfig      |    5 +-
 arch/mips/configs/sead3micro_defconfig | 1771 ++++++++++++++++++++++++++++++++
 ar

[PATCH] MIPS: Refactor 'clear_page' and 'copy_page' functions.

Steven J. Hill — 2012-05-24T20:38:24

From: "Steven J. Hill" <sjhill< at >mips.com>

Remove usage of the '__attribute__((alias("...")))' hack that aliased
to integer arrays containing micro-assembled instructions. This hack
breaks when building a microMIPS kernel. It also makes the code much
easier to understand.

Signed-off-by: Steven J. Hill <sjhill< at >mips.com>
---
 arch/mips/mm/Makefile     |    4 +--
 arch/mips/mm/page-funcs.S |   49 +++++++++++++++++++++++++++++++++
 arch/mips/mm/page.c       |   67 ++++++++++++---------------------------------
 3 files changed, 69 insertions(+), 51 deletions(-)
 create mode 100644 arch/mips/mm/page-funcs.S

diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile
index 4aa2028..fd6203f 100644
--- a/arch/mips/mm/Makefile
+++ b/arch/mips/mm/Makefile
< at >< at > -3,8 +3,8 < at >< at >
 #
 
 obj-y+= cache.o dma-default.o extable.o fault.o \
-   gup.o init.o mmap.o page.o tlbex.o \
-   tlbex-fault.o uasm.o
+   gup.o init.o mmap.o page.o page-funcs.o \
+   tlbex.o tlbex-fault.o uasm.o
 
 obj-$(CONFIG_32BIT)+= iore

[PATCH] MIPS: Add support for the M14KEc core.

Steven J. Hill — 2012-05-24T15:24:12

From: "Steven J. Hill" <sjhill< at >mips.com>

Signed-off-by: Steven J. Hill <sjhill< at >mips.com>
---
 arch/mips/include/asm/cpu-features.h |    3 +++
 arch/mips/include/asm/cpu.h          |    4 +++-
 arch/mips/kernel/cpu-probe.c         |    7 +++++++
 arch/mips/mm/c-r4k.c                 |    1 +
 arch/mips/mm/tlbex.c                 |    2 ++
 arch/mips/oprofile/common.c          |    1 +
 arch/mips/oprofile/op_model_mipsxx.c |    4 ++++
 7 files changed, 21 insertions(+), 1 deletion(-)

diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 2daf1c5..98bee29 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
< at >< at > -98,6 +98,9 < at >< at >
 #ifndef kernel_uses_smartmips_rixi
 #define kernel_uses_smartmips_rixi 0
 #endif
+#ifndef cpu_has_mmips
+#define cpu_has_mmips(cpu_data[0].options & MIPS_CPU_MICROMIPS)
+#endif
 #ifndef cpu_has_vtag_icache
 #define cpu_has_vtag_icache(cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
 #endif
diff --git a/arch/mi

[PATCH v2,4/9] MIPS: Add microMIPS breakpoints and DSP support.

Steven J. Hill — 2012-05-23T04:57:16

From: "Steven J. Hill" <sjhill< at >mips.com>

Signed-off-by: Steven J. Hill <sjhill< at >mips.com>
---
 arch/mips/include/asm/break.h |   11 +++++++++--
 arch/mips/include/asm/dsp.h   |    4 ++++
 arch/mips/kernel/proc.c       |    9 +++++++--
 3 files changed, 20 insertions(+), 4 deletions(-)

diff --git a/arch/mips/include/asm/break.h b/arch/mips/include/asm/break.h
index 9161e68..4e4dc87 100644
--- a/arch/mips/include/asm/break.h
+++ b/arch/mips/include/asm/break.h
< at >< at > -3,8 +3,9 < at >< at >
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1995, 2003 by Ralf Baechle
  * Copyright (C) 1999 Silicon Graphics, Inc.
+ * Copyright (C) 1995, 2003 by Ralf Baechle
+ * Copyright (C) 2011, 2012 MIPS Technologies, Inc.
  */
 #ifndef __ASM_BREAK_H
 #define __ASM_BREAK_H
< at >< at > -27,11 +28,17 < at >< at >
 #define BRK_STACKOVERFLOW 9/* For Ada stackchecking */
 #define BRK_NORLD10/* No rld found - not used by Linux/MIPS */
 #define _BRK_THREADBP11/* For threads, user bp (used by

handle_sys question

Songmao Tian — 2012-05-22T09:40:20

Hello all:
   In handle_sys there's a
50<http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=blob;f=arch/mips/kernel/scall32-o32.S;h=a632bc144efa1b9ca977a582864530e33ee039cb;hb=72c04af9a2d57b7945cf3de8e71461bd80695d50#l50>
       sw      a3, PT_R26(sp)          # save a3 for syscall
restarting

I woner why it need to save  a3 in R26(k0) slot in the stack?

Thanks,
songmao

[PATCH v3,2/9] MIPS: Optimise core library functions for microMIPS.

Steven J. Hill — 2012-05-21T15:58:55

From: "Steven J. Hill" <sjhill< at >mips.com>

Optimise some of the core library functions to use microMIPS
instructions for binary size reduction. When the microMIPS ISA
is not being used, the library functions compiled to binary
are identical.

Signed-off-by: Steven J. Hill <sjhill< at >mips.com>
---
 arch/mips/include/asm/asm.h          |    2 +
 arch/mips/include/asm/cpu-features.h |    3 ++
 arch/mips/include/asm/cpu.h          |    4 +-
 arch/mips/include/asm/page.h         |    6 +++
 arch/mips/kernel/cpu-probe.c         |   10 ++++
 arch/mips/lib/memcpy.S               |   17 +++++--
 arch/mips/lib/memset.S               |   84 ++++++++++++++++++++++------------
 arch/mips/lib/strlen_user.S          |    9 ++--
 arch/mips/lib/strncpy_user.S         |   28 ++++++------
 arch/mips/lib/strnlen_user.S         |    2 +-
 arch/mips/mm/c-r4k.c                 |    1 +
 arch/mips/mm/page.c                  |   26 ++++++-----
 arch/mips/mm/tlbex.c                 |    2 +
 arch/mips/oprofile/common.c          |    1 +

[PATCH v3,08/10] MIPS: MIPS32R2 optimisations for pipeline stalls and code size.

Steven J. Hill — 2012-05-21T15:58:40

From: "Steven J. Hill" <sjhill< at >mips.com>

If the CPU type is selected as MIPS32R2, then we can surround
some code with #ifdef's to reduce the binary size. Detect when
to use 'ehb' instruction to avoid pipeline stalls. Utilise the
'ins' and 'ext' MIPS32R2 instructions to reduce the size of
exception handlers.

Signed-off-by: Steven J. Hill <sjhill< at >mips.com>
---
 arch/mips/mm/tlbex.c |   40 ++++++++++++++++++++++++++++++++++++----
 1 file changed, 36 insertions(+), 4 deletions(-)

diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 897b727..de7fe58 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
< at >< at > -340,6 +340,7 < at >< at > static void __cpuinit build_restore_work_registers(u32 **p)
  */
 extern unsigned long pgd_current[];
 
+# ifndef CONFIG_CPU_MIPS32_R2
 /*
  * The R3000 TLB handler is simple.
  */
< at >< at > -379,6 +380,7 < at >< at > static void __cpuinit build_r3000_tlb_refill_handler(void)
 
 dump_handler((u32 *)ebase, 32);
 }
+# endif /* !CONFIG_CPU_MIPS32_R2 */
 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */

[PATCH] MIPS: Add support for the MIPS32 4Kc family I/D caches.

Steven J. Hill — 2012-05-21T15:33:32

From: "Steven J. Hill" <sjhill< at >mips.com>

Signed-off-by: Douglas Leung <douglas< at >mips.com>
Signed-off-by: Steven J. Hill <sjhill< at >mips.com>
---
 arch/mips/mm/c-r4k.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 18546fa..bca1447 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
< at >< at > -1000,7 +1000,7 < at >< at > static void __cpuinit probe_pcache(void)
 c->icache.linesz = 2 << lsize;
 else
 c->icache.linesz = lsize;
-c->icache.sets = 64 << ((config1 >> 22) & 7);
+c->icache.sets = 32 << (((config1 >> 22) + 1) & 7);
 c->icache.ways = 1 + ((config1 >> 16) & 7);
 
 icache_size = c->icache.sets *
< at >< at > -1020,7 +1020,7 < at >< at > static void __cpuinit probe_pcache(void)
 c->dcache.linesz = 2 << lsize;
 else
 c->dcache.linesz= lsize;
-c->dcache.sets = 64 << ((config1 >> 13) & 7);
+c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7);
 c->dcache.ways = 1 + ((config1 >> 7) & 7);
 
 dcache_size = c->dcache.sets *

[PATCH] MIPS: Remove dead code related to 1004K oprofile support.

Steven J. Hill — 2012-05-21T15:33:16

From: "Steven J. Hill" <sjhill< at >mips.com>

Signed-off-by: Steven J. Hill <sjhill< at >mips.com>
---
 arch/mips/oprofile/op_model_mipsxx.c |    6 ------
 1 file changed, 6 deletions(-)

diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c
index ef4e87f..a86e93e 100644
--- a/arch/mips/oprofile/op_model_mipsxx.c
+++ b/arch/mips/oprofile/op_model_mipsxx.c
< at >< at > -338,12 +338,6 < at >< at > static int __init mipsxx_init(void)
 break;
 
 case CPU_1004K:
-#if 0
-/* FIXME: report as 34K for now */
-op_model_mipsxx_ops.cpu_type = "mips/1004K";
-break;
-#endif
-
 case CPU_34K:
 op_model_mipsxx_ops.cpu_type = "mips/34K";
 break;

[PATCH v3,1/5] MIPS: Add support for the 1074K core.

Steven J. Hill — 2012-05-21T15:31:50

From: "Steven J. Hill" <sjhill< at >mips.com>

This patch adds support for detecting and using 1074K cores.

Signed-off-by: Steven J. Hill <sjhill< at >mips.com>
---
 arch/mips/include/asm/cpu.h  |    1 +
 arch/mips/kernel/cpu-probe.c |    4 ++++
 arch/mips/mm/c-r4k.c         |   20 +++++++++++++++++++-
 3 files changed, 24 insertions(+), 1 deletion(-)

diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index f9fa2a4..9f8feeb 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
< at >< at > -94,6 +94,7 < at >< at >
 #define PRID_IMP_24KE0x9600
 #define PRID_IMP_74K0x9700
 #define PRID_IMP_1004K0x9900
+#define PRID_IMP_1074K0x9a00
 
 /*
  * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 5099201..4b5c7d6 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
< at >< at > -835,6 +835,10 < at >< at > static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
 c->cputype = CPU_1004K;

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[PATCH V3 17/17] MIPS: lantiq: remove orphaned code

John Crispin — 2012-05-18T15:44:27

Now that all drivers are converted to OF we are able to remove some remaining
pieces of orphaned code.

Signed-off-by: John Crispin <blogic< at >openwrt.org>
---
 arch/mips/include/asm/mach-lantiq/lantiq.h         |    5 -
 .../mips/include/asm/mach-lantiq/lantiq_platform.h |   33 -------
 .../mips/include/asm/mach-lantiq/xway/lantiq_irq.h |   44 +---------
 .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h |   90 +-------------------
 arch/mips/lantiq/prom.c                            |    6 --
 arch/mips/lantiq/xway/sysctrl.c                    |    4 +
 6 files changed, 7 insertions(+), 175 deletions(-)

diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h
index 64fbc3f..5e8a6e9 100644
--- a/arch/mips/include/asm/mach-lantiq/lantiq.h
+++ b/arch/mips/include/asm/mach-lantiq/lantiq.h
< at >< at > -27,9 +27,6 < at >< at >
 ltq_w32_mask(x, y, ltq_ebu_membase + (z))
 extern __iomem void *ltq_ebu_membase;
 
-extern unsigned int ltq_get_cpu_ver(void);
-extern unsigned int ltq_get_soc_typ

801707538158

2012-05-17T21:22:20

[PATCH 0/8] patchset focus on MIPS SMP woes

Yong Zhang — 2012-05-17T10:10:02

From: Yong Zhang <yong.zhang< at >windriver.com>

Since commit 5fbd036b [sched: Cleanup cpu_active madness] and
commit 2baab4e9 [sched: Fix select_fallback_rq() vs cpu_active/cpu_online],
it's more safe to put notify_cpu_starting() and set_cpu_online() with
irq disabled, otherwise we will have a typical race condition which
above two commits try to resolve:

      CPU1                            CPU2
__cpu_up();
   mp_ops->boot_secondary();
                              start_secondary();
                                ->init_secondary();
                                  local_irq_enable();
                              <IRQ>
                              do something;
                                    wake up softirqd;
                                    try_to_wake_up();
                                      select_fallback_rq();
                                      /* select wrong cpu */
   set_cpu_online();


This patchset fix the above issue as well as set_cpu_online is
called on the caller cpu.

BTW, I

[PATCH v2 0/2] MIPS: enable APRP (APSP) and add features - v2

Deng-Cheng Zhu — 2012-05-17T08:51:18

The APRP model makes it possible that one or more CPUs run the Linux
kernel whereas a dedicated CPU runs special real-time or signal processing
program.

This patchset adds the following to the current APRP support:
1. Several bug fixes;
2. Running floating point heavy jobs on the RP side;
3. Waking up RP side read by interrupt;
4. CPS multicore APRP support.

A mp3 player program was ported to run in the APRP (APSP exactly) model.
Considerable performance benefits were observed on the player program.

Changes:
v2 - v1:
o Rebase the patches to the latest kernel, and fix a bunch of warnings and
  errors reported by the current scripts/checkpatch.pl.
o Add MIPS_MALTA dependency to Kconfig since modifications of Malta files
  are needed. But it should be easy to port changes to other platforms.

Deng-Cheng Zhu (2):
  MIPS: fix/enrich 34K APRP (APSP) functionalities
  MIPS: enable CPS multicore APRP (APSP)

 arch/mips/Kconfig                                  |   10 +-
 .../include/asm/mach-malta/cpu-feature-over

[PATCH V3 1/3] GPIO: MIPS: lantiq: move gpio-stp and gpio-ebu to the subsystem folder

John Crispin — 2012-05-16T20:49:52

Move the 2 drivers from arch/mips/lantiq/xway/ to the subsystem and make them
buildable.

The following 2 patches will convert the drivers to OF.

Signed-off-by: John Crispin <blogic< at >openwrt.org>
Cc: Grant Likely <grant.likely< at >secretlab.ca>
Cc: linux-kernel< at >vger.kernel.org
---
This patch is part of a series moving the mips/lantiq target to OF and clkdev
support. The patch, once Acked, should go upstream via Ralf's MIPS tree.

 arch/mips/lantiq/xway/Makefile   |    2 +-
 arch/mips/lantiq/xway/gpio_ebu.c |  126 -------------------------------
 arch/mips/lantiq/xway/gpio_stp.c |  152 --------------------------------------
 drivers/gpio/Kconfig             |   18 +++++
 drivers/gpio/Makefile            |    2 +
 drivers/gpio/gpio-mm-lantiq.c    |  126 +++++++++++++++++++++++++++++++
 drivers/gpio/gpio-stp-xway.c     |  152 ++++++++++++++++++++++++++++++++++++++
 7 files changed, 299 insertions(+), 279 deletions(-)
 delete mode 100644 arch/mips/lantiq/xway/gpio_ebu.c
 delete mode 100644 arch/mips/lantiq/xway/gpio

[PATCH V4 06/17] MIPS: lantiq: convert dma to platform driver

John Crispin — 2012-05-15T17:00:12

Add code to make the dma driver load as a platform device from the devicetree.

Signed-off-by: John Crispin <blogic< at >openwrt.org>

---
Changes in V4
* drop the typo prone comment

Changes in V3
* add a missing \n

 arch/mips/lantiq/xway/dma.c |   61 +++++++++++++++++++++++++++---------------
 1 files changed, 39 insertions(+), 22 deletions(-)

diff --git a/arch/mips/lantiq/xway/dma.c b/arch/mips/lantiq/xway/dma.c
index b210e93..55d2c4f 100644
--- a/arch/mips/lantiq/xway/dma.c
+++ b/arch/mips/lantiq/xway/dma.c
< at >< at > -19,7 +19,8 < at >< at >
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/dma-mapping.h>
-#include <linux/export.h>
+#include <linux/module.h>
+#include <linux/clk.h>
 
 #include <lantiq_soc.h>
 #include <xway_dma.h>
< at >< at > -55,13 +56,6 < at >< at >
 #define ltq_dma_w32_mask(x, y, z)ltq_w32_mask(x, y, \
 ltq_dma_membase + (z))
 
-static struct resource ltq_dma_resource = {
-.name= "dma",
-.start= LTQ_DMA_BASE_ADDR,
-.end= LTQ_DMA_BASE_ADDR + LTQ_DMA_SIZE - 1,
-.flags  = IORESOURCE_MEM