gmane.linux.bios

Optimizations to GMP build/host tuning break toolchainportability

Raymond Danks — 2012-05-25T17:13:09

I'm writing this as a bug for the GMP community and CCing coreboot, 
although, with the proper direction I can imagine this all ending in a 
change to the configure flags in the coreboot xgcc build.

The coreboot project contains a build script for generating a cross 
toolchain (xgcc).  The versions were recently bumped to:
GMP_VERSION=5.0.5
MPFR_VERSION=3.1.0
MPC_VERSION=0.9
LIBELF_VERSION=0.8.13
GCC_VERSION=4.6.3
GCC_AUTOCONF_VERSION=2.64
BINUTILS_VERSION=2.22

For the purposes of this bug, the important change was the move from GMP 
5.0.2 to GMP 5.0.5.  The issue is that an xgcc toolchain built on one 
host cannot consistently be moved to a similar operating system on a 
different host with a different underlying architecture.  This was seen 
with both 32bit and 64bit OS installs under the following configurations:

64bit Build Host
Ubuntu 11.04 \n \l
Linux ubuntubuilder03 2.6.38-14-server #58-Ubuntu SMP Tue Mar 27 
20:21:58 UTC 2012 x86_64 x86_64 x86_64 GNU/Linux
vendor_id    : AuthenticAMD
model name

make und Git: fatal: No names found,cannot describe anything.

Paul Menzel — 2012-05-24T20:09:18

Dear coreboot folks,


I cloned the source tree,

        $ git describe
        4.0-2410-g92ff934

did `make crossgcc` and run `make menuconfig`.

I chose ASRock E350M1 and SeaBIOS master.

At the end I got the following.

        $ make
        […]
            Checking out SeaBIOS revision origin/master
        Switched to branch 'master'
        Deleted branch coreboot (was 347f294).
        Branch coreboot set up to track remote branch master from origin.
        Switched to a new branch 'coreboot'
            CONFIG     SeaBIOS origin/master
          Working around non-functional -combine
          Build default config
        # 
        # configuration written to /home/joe/coreboot/build/seabios/.config
        #
            MAKE       SeaBIOS origin/master
          Working around non-functional -combine
          Build Kconfig config file
        /home/joe/coreboot/build/seabios/.config:89:warning: override: reassigning to symbol COREBOOT
        /home/joe/coreboot/build/seabios/.config:90:warning

[AMD] Persimmon

2012-05-23T08:32:43

Hello all,

 

I check out coreboot and build and run persimmon project via menuconfig,

Mainborad: AMD

Mainboard Model: Persimon

FlashSize: 4MB

 

But it always show 0x00 on my PCI debug card. 

I do not know its 80 port default path is LPC or PCI, so

I have tried to route 80 port to PCI in entry32.inc (src/cpu/x86/32bit),

But it seem not work.

 

Can someone help me to solve this issue,

 

Thanks.

 

Here is my configuration:

NorthBridge: AMD family 14

SouthBridge: SB800

SIO: FNTEK F81865

Add mainboard supermicro x7db8

manasa gv — 2012-05-23T12:25:42

From: Manasa GV <manasa671989< at >gmail.com>

This patch is to file x7db8.Build(Jenkins) results failed for patch
set1 in patch493.Test results showing error. So i added cmos.layout
file.Later i done abuild,then also it is showing errors. Errors are-
need to add smbus.c, smbus.h ,early_setup.c file for Southbridge
i63xx.
So please suggest me to add these files.

Signed-off-by: manasa gv<manasa671989< at >gmail.com>
---
src/mainboard/supermicro/x7db8/cmos.layout |   72 ++++++++++++++++++++++++++++
1 files changed, 72 insertions(+), 0 deletions(-)
create mode 100644 src/mainboard/supermicro/x7db8/cmos.layout

diff --git a/src/mainboard/supermicro/x7db8/cmos.layout
b/src/mainboard/supermicro/x7db8/cmos.layout
new file mode 100644
index 0000000..9d22590
--- /dev/null
+++ b/src/mainboard/supermicro/x7db8/cmos.layout
< at >< at > -0,0 +1,72 < at >< at >
+entries
+
+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_second

Trac reminder: list of new ticket(s)

coreboot tracker — 2012-05-21T14:00:01

Boots from PCI add-on card on Intel ICHs

Kyösti Mälkki — 2012-05-20T08:23:07

Hi

I did not find this method of bypassing the mainboard flash chip and
booting from PCI add-on card documented or discussed before. The nice
think in this is that neither mainboard or its flash needs to be
modified. Good news in the case of a soldered flash and this method may
work with mini-PCI slots on laptops too.

For pre-ICH6 the key is in subtractive PCI decode. This has been
supported in 82801 chipset from the early days and is briefly documented
in ICH3 datasheet [1], see 5.1.1. PCI Bus interface. This decode mode is
on by default and there is no documentation of a hw bootstrap that could
disable it.

For ICH7 onwards there are HW bootstraps to select between LPC/SPI/PCI.
If you don't know where the bootstraps are, go with SPI and forget about
this PCI add-on boot.


To try this, I have modified a PCI PATA-RAID card as follows: I cut the
PCI RST# signal from card edge to controller, put a jumper to close it
for normal boots and placed a weak 10kOhm pull-up to Vio on the chip
side.

With this I have

Support of the MS-7091 mainboard

Paul Du — 2012-05-18T21:13:04

Hello,I would like to know if my motherboard is or could be supported by coreboot. Thanks :)I was inspired from http://www.coreboot.org/pipermail/coreboot/2010-April/057128.html because I didn't find the answer of this mail so sorry if you've already answer for this motherboard.( Sorry if I didn't do the right things, it's my first mailing list. )
Step 1:My motherboard is a MSI-7091 (OEM-Board by MEDION) socket 775.The CPU is an Intel Pentium 4 524 3.06 Ghz with Hyperthreading.I found the Host bridge : Intel Corporation 82915G/P/GV/GL/PL/910GL Memory Controller HubThe PCI Bridge : Intel Corporation 82915G/P/GV/GL/PL/910GL PCI Express Root PortAnother PCI Bridge : Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) PCI Express Port 1A third PCI Bridge : Intel Corporation 82801 PCI BridgeAn ISA Bridge : Intel Corporation 82801FB/FR (ICH6/ICH6R) LPC Interface BridgeA SMBUS : Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) SMBus ControllerMy System Operation is in 64 bits.
Step 2 :-[0000:00]-+-00.0  Int

Trac reminder: list of new ticket(s)

coreboot tracker — 2012-05-14T14:00:02

wget fails to fetch from acpica.org

Raymond Danks — 2012-05-11T22:18:58

I ran into an issue yesterday with wget fetching the source packages for 
the iasl build from the acpica.org website.  It seems that they have 
changed their SSL implementation.  Specifically, this site, as of 
yesterday, uses TLS-SNI on the backend.  Wget versions that I have 
tried, 1.12 and the latest 1.13.4, fail with:

ERROR: cannot verify www.acpica.org's certificate, issued by 
`/C=US/ST=Arizona/L=Scottsdale/O=GoDaddy.com, 
Inc./OU=http://certificates.godaddy.com/repository/CN=Go Daddy Secure 
Certification Authority/serialNumber=07969287':
   Issued certificate has expired.
ERROR: certificate common name `ofono.org' doesn't match requested host 
name `www.acpica.org'.
To connect to www.acpica.org insecurely, use `--no-check-certificate'.

The suggestion back from acpica.org is to use curl, which can properly 
handle TLS-SNI.   It appears that there may be patches around for 
TLS-SNI implementation within wget.  So, as an alternative, we can build 
our own wget in coreboot.  Or, we could simply pass i

please check coreboot supports for this givenconfiguration

manasa gv — 2012-05-12T09:13:50

Hi,

     I have given below information about my system.. please let me
know will coreboot support for this configuration..


Step 1:
          Board Vendor:  TOSHIBA
          Board Name :  Satellite L500 (Montevina_Fab)
          CPU            :   Pentium(R) Dual-Core CPU       T4300  < at > 2.10GHz
          CPU Vendor :  Intel Corp

   I didn't find northbridge and southbridge information..So i added
the output of 'lshw' ..

   description: Notebook
    product: Satellite L500 (Montevina_Fab)
    vendor: TOSHIBA
    version: PSLLTG-007003
    serial: Z9070791Q
    width: 64 bits
    capabilities: smbios-2.4 dmi-2.4 vsyscall32
    configuration: boot=normal chassis=notebook family=Intel_Mobile
sku=Montevina_Fab uuid=9A1C7C40-DAFE-11DE-BBA9-00266C35CC82
  *-core
       description: Motherboard
       product: Portable PC
       vendor: TOSHIBA
       physical id: 0
       version: Base Board Version
       serial: Base Board Serial Number
       slot: Base Board Chassis Location
     *-firmware
          desc

memory

ali hagigat — 2012-05-12T08:43:05

If the CPU wb (write back) cache is enabled for the memory range,
ramstage() is OK. But CPU can not work with UC(uncached) memory type
in Coreboot code. If i define the whole memory  un-cached right before
jumping to ramstage code ( cbfs_and_run()), CPU does not execute
C_start.S and it is actually restarted!
Any clue or idea will be much appreciated.

Visit coreboot at LinuxTag in Berlin,May 23rd - May 26th 2012

Peter Stuge — 2012-05-12T00:36:25

It is our pleasure to invite you to the coreboot booth at LinuxTag
in Berlin again this year. See http://linuxtag.org/2012/ for details.

We are located in hall 7.2b, booth 278, in the corner to the right of
the Open Source Arena stage, the same location as the last few years.

As usual we will showcase a nice system or two booting coreboot, this
time it's all about laptops!

We hope to also have some fun surprises for visitors in the booth,
but the final confirmation is not in just yet. Stop by and see if we
could make our ideas a reality in time! :)


Please be aware that if you plan to visit Messe Berlin by car, the
usual parking lot by the entrance is not available this year, since
the hall right in front of the entrance has been blown up, and the
whole area is currently a big construction site.


See you at the booth!

//Peter, Björn, and Paul

seabios feature request : reboot VM or retry boot devices when no valid boot disk is found

Maurits van de Lande — 2012-05-11T13:28:45

Hello,

I'm  using KVM on Centos 6.2. Currently I switched to iSCSI storage to host the virtual machines.

When I was  simulation some worst case scenario's I noticed that when no boot device is found the bios just stops at displaying "No bootable device"

I would prefer to automatically reboot the VM (or retry the boot devices) when no bootable device is found, then when the iSCSI storage is available again the VM can boot normally.
(when I manually sent CTRL+ALT+DEL to the VM the system booted normaly again)

Is there  a way to use seabios this way?
If  not, can it be added to the bios?

Best regards,

Maurits van de Lande

Adding Supermicro X9SCV-QV4

Nachiketh G — 2012-05-10T16:05:31

Hi,
I have started working on porting coreboot for Supermicro X9SCV-QV4
motherboard which is based on a Intel QM67 chipset, it does support the
Intel core 15/i7 processor families and I wanted to know if there is any
existing code base which I can have a look at for reuse/reference.
Since i'm new to coreboot if someone could point me  the approach I need to
take to add new Board support for coreboot would be of great help.
Thanks & Regards,
Nachiketh

Trac reminder: list of new ticket(s)

coreboot tracker — 2012-05-07T14:00:02

[flashrom] Flashing capability in coreboot

Carl-Daniel Hailfinger — 2012-05-03T22:16:26

Hi,

coreboot has a requirement to store some data in flash to get some
chipsets to work well. There are multiple ways to achieve this:

1. Write flashing code from scratch. Pointless.

2. Use parts of the flashrom codebase or libflashrom. Advantages:
coreboot and flashrom developers often work on both projects, enabling
better cooperation. flashrom has the best chipset/flash support out there.

3. Use parts of the U-Boot codebase (which has drivers derived from
flashrom). Advantages: The codebase is designed with firmware
constraints in mind. http://review.coreboot.org/997 seems to implement this.


As a flashrom developer, I would like to see flashrom code used in
coreboot, and I'm very interested in finding and fixing any obstacles to
that goal.
Patrick, I think you worked on the coreboot patch mentioned above. Could
you tell us about your reasons for choosing option 3, and how we can
make option 2 viable?

Regards,
Carl-Daniel

Regarding patch review 707

manasa gv — 2012-05-03T09:38:30

Hi,



I am posting this question again because did not got any solution..
How to compile and test the assemebly program of patch 707 that is
'.inc file' ?? Specially entry16.inc file in coreboot,because
privileged instruction that is LIDT is used..please provide me any
document or suggest me where do i get more information related to
this..

Below given is the File path.
src/cpu/x86/16bit/entry16.inc


I am new to this coreboot..please guide me ...



Thanks,
Manasa

Definition of _boot_

Svante Signell — 2012-05-02T08:51:50

Dear coreboot developers,

I'm trying to get the boot process definition cleared out in a
discussion at debian-devel on replacing the sysvint script system with
something event based like systemd or upstart. In the list below,
please help me to refine it, and especially make a distinction on what
is needed to:
1) get the computer up and running 
2) all services needed are completed

Of special interest is what parts is taken care of different tasks in
the boot procedure, and where serial/parallel processes are possible.

As I see it we have several tools in the boot process:
1) coreboot/BIOS
2) A workload, like grub2
3) The init scripts/systemd/upstart
4) On linux: udev communicating with the kernel, something else on other architectures

In my opinion the boot process definition can be split in two parts:
1) Initial boot, taken care of by sysvinit: Mainly order based or serial
2) secondary boot, taken care of by udev on Linux, something else on
other arches: Mainly event-based or parallel

Am I completely o

bluetooth on Thinkpad X60s

Motiejus Jakštys — 2012-05-01T14:03:33

Hi,

bluetooth was not working for me on Thinkpad X60s. Rfkill was not
showing the device and the bluetooth led was off. The way I managed to
make it work is with this patch:

diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c
index ecd34b2..b13d687 100644
--- a/src/ec/lenovo/h8/h8.c
+++ b/src/ec/lenovo/h8/h8.c
< at >< at > -151,8 +151,7 < at >< at > static void h8_enable(device_t dev)
                ec_write(H8_VOLUME_CONTROL, val);


-       if (!get_option(&val, "bluetooth"))
-               h8_bluetooth_enable(val);
+    h8_bluetooth_enable(1);

        if (!get_option(&val, "first_battery")) {
                tmp = ec_read(H8_CONFIG3);

What would be a better way to do it?

List of possible porting targets

Paul Menzel — 2012-04-30T18:43:06

Dear coreboot folks,


since it is also quite a lot of work to find an appropriate board to
port coreboot easily to (socketed flash chip, no embedded control), I
think it would be a good to have such a list.

The Wiki is probably a good place, but not all people want to request an
account just for this.

Therefore I think a thread on this list is good enough for this purpose.

So if you find some board and you make some discoveries please reply to
this message and report your findings.


Thanks,

Paul

Trac reminder: list of new ticket(s)

coreboot tracker — 2012-04-30T14:00:01