http://blog.gmane.org/gmane.linux.bios hourly 1 1901-01-01T00:00+00:00 http://gmane.org/img/gmane-25t.png http://gmane.org http://comments.gmane.org/gmane.linux.bios/77421 <pre>I've tested it on loongson 3aserver mainboard, but I don't have a x86 mainboard, is there anyone test the patch for me on a x86 mainboard, thanks. </pre> yili0568< at >gmail.com 2013-06-18T08:39:28 http://comments.gmane.org/gmane.linux.bios/77418 <pre>Hi folks, Thanks #coreboot for all your help with my laptop, I learnt a lot today from you all. Unfortunately my first attempt at installing coreboot has resulted in a bricked laptop. I tried to cheat by making an educated guess of the SPI chip model without pulling my laptop to bits to verify. However, it seemed right according to the responses i was getting from flashrom -V for the failed chips, since the manufacturer id and model id I was getting from flashrom matched the datasheet specs for a particular chip. I downloaded and compiled the crossgcc toolchain. I created a patch for flashrom and proceeded to read my flash. I got a successful read from flashrom and dumped my vgabios. I compiled coreboot for T60 and followed the wiki grabbing the 3 patches for Lenovo stuff and inserting my custom SMBIOS details in the config. Once i felt happy with my coreboot.rom I followed exactly the procedure on the coreboot Lenovo wiki to flash my laptop internally. I have attached here the coreboot config i us</pre> Damien Zammit 2013-06-16T23:23:37 http://comments.gmane.org/gmane.linux.bios/77413 <pre>Per advice of the #coreboot channel, I will ask this question here. Does coreboot support intel's haswell arch, specifically the z87 chipset? </pre> Eric Sherouse 2013-06-16T21:19:23 http://comments.gmane.org/gmane.linux.bios/77411 <pre>Hello, I tried to build and flash coreboot and SeaBIOS onto a Samsung Chromebox. I built coreboot from master of the coreboot tree (no chromiumos patches). My problem is that the Chromebox now only boots from a complete cold boot. In other words, I need to unplug both the AC power and the RTC battery, then plug in the AC power, and then push the power button. If I run "shut down" from Ubuntu and try to press the power button, the board does not boot. If I hold the power button until the box shuts off and push the power button again, it also does not boot. If I suspend from Ubuntu, the box suspends and the blue LED starts blinking. However, if I push the power, it doesn't resume. One thing I observed is that all the boots that don't work involve the power LED either never turning on or turning on instantly. The complete cold boot that does work has the power LED blinking very briefly, turning off for several seconds, and then turning back on. Does anybody know what is going on here? Attached is a cbmem conso</pre> Robert Ou 2013-06-16T01:17:31 http://comments.gmane.org/gmane.linux.bios/77400 <pre>Hello, all. In order to build X201 rom, you need management engine firmware. For chromebook the appropriate blobs are in 3rdparty repo, I suppose supplied by Intel. The only place where I could get ME firmware for X201 is by dumping chip with external programmer. It's probably not appropriate for coreboot to distribute those blobs (I'm unsure on their license) and given that it writes a log to its section which may contain private data, I don't want to distribute it either. Yet without this blob the build legitimately fails. Any suggestions on handling this? </pre> Vladimir 'φ-coder/phcoder' Serbinenko 2013-06-12T23:16:19 http://comments.gmane.org/gmane.linux.bios/77397 <pre>It's attached. You may want to remove/tweak some of the bits. I haven't used the cc part in quite some time. There are no options as this was quick and dirty. It will need an upstream tracking branch in git config to work. i.e. git checkout -b my_work upstream/master $ gitreview.sh adurbin git push --receive-pack='git receive-pack --reviewer=adurbin --cc=&lt;cc_someone&gt;' upstream HEAD:refs/for/master I then just paste the output because I don't always trust it. I find it useful. -Aaron </pre> Aaron Durbin 2013-06-12T13:26:43 http://comments.gmane.org/gmane.linux.bios/77385 <pre>Hello! I have some troubles with southbridge i82801gx. I can boot Windows on my board, but S3 from OS doesn't work properly if i resume with USB keyboard. In this case, i have Wake signal and coreboot starts to boot, but it stucks with endless messages about SMI# "GPE0_STS: USB1": .. SMI# #0 GPE0_STS: USB1 SMI# #0 GPE0_STS: USB1 SMI# #0 GPE0_STS: USB1 ... These messages come from file "\southbridge\intel\i82801gx\smihandler.c", function "dump_gpe0_status". According to i82801gx datasheet: ___ USB1_STS - R/WC. Software clears this bit by writing a 1 to it. 0 = USB UHCI controller 1 does Not need to cause a wake. 1 = Set by hardware when USB UHCI controller 1 needs to cause a wake. Wake event will be generated if the corresponding USB1_EN bit is set. ___ Clearing of GPE0_STS bits properly done in function reset_gpe0_status /** * &lt; at &gt;brief read and clear GPE0_STS * &lt; at &gt;return GPE0_STS register */ static u32 reset_gpe0_status(void) { u32 reg32; reg32 = inl(pmbase + GPE0_STS); /* set status</pre> Константин Аладышев 2013-06-11T14:33:12 http://comments.gmane.org/gmane.linux.bios/77375 <pre>Hi, try to collect information about the chromebooks to write things up in the wiki. Which of the following things are true (for the lastest coreboot version): 0. all 5 Chromebooks are supported by coreboot (http://www.google.com/intl/en/chrome/devices/chromebooks.html) Ok 5 names show in the config menu, so are there maybe unsupported older version of the chromebooks (ones with other working names then 1. Butterfly (BOARD_GOOGLE_BUTTERFLY) (NEW) 2. Link (BOARD_GOOGLE_LINK) (NEW) 3. Parrot (BOARD_GOOGLE_PARROT) (NEW) 4. Snow (BOARD_GOOGLE_SNOW) (NEW) 5. Stout (BOARD_GOOGLE_STOUT) (NEW)! 1. all chromebooks need to be flashed by an external programmer to get your own coreboot version (and payload) running (but it is doable without breaking things) Is there information about where the spi chips can be found? +++++Offtopic++++++ which ones don't require any proprietary drivers? +++++offtopic++++++ Thanks Tim </pre> Tim Zander 2013-06-10T21:45:59 http://comments.gmane.org/gmane.linux.bios/77369 <pre> Hi, CPU: haswell chipset:lynxpoint c226 I use Intel wtm2 board. SATA controller in ahci mode. disk can be detect but no phy link. log file see attach. Thanks! roger </pre> 朱晓元 2013-06-10T02:00:28 http://comments.gmane.org/gmane.linux.bios/77355 <pre>Hello i bought brand new pc500e from ebay as i really like via - and have been interested in coreboot for a long time. board is exactly the same as in Uve Hermanns image - http://www.coreboot.org/VIA_pc2500e . i have been using Linux for ages ( from kernel 1.2.13 or so ) and built my stuff mostly myself using some aschetic distribution, like early slackware and now CRUX to get started. after reading coreboot pages, getting coreboot, filo and flashrom sources from git, configuring and building them to best of my understanding, system does not boot. i have spare w39v040bfz, which works with original bios burned into it, but not w coreboot. would someone like to help me - i can of course deliver config, dmesg, what-ever ? /mc ---keep-IT-simple--- </pre> matti christensen 2013-06-07T16:07:40 http://comments.gmane.org/gmane.linux.bios/77349 <pre>Dear Corebooters, I want to flash coreboot onto my x60s. Is the only way to find out the chip model of my x60s by disassembling and inspecting? If I have the data written on my chip, what I have to then to find the information necessary to do the first part of the flashing instruction of http://www.coreboot.org/Lenovo_x60x ? What do I need to change in the patch then? Or don't I need to find out about the chip: http://www.coreboot.org/pipermail/coreboot/2013-January/073801.html? You see I'm totally confused thanks for enlightment. Best wishes, Tim &lt;http://www.coreboot.org/Lenovo_x60x&gt; </pre> Tim Zander 2013-06-07T09:52:23 http://comments.gmane.org/gmane.linux.bios/77346 <pre>Hi Everyone, I was looking at the wiki's Getting Started | QEMU section [1] and I noticed that all examples are outdated: coreboot V2 or V3. I understand that for most coreboot developers QEMU will provide no benefits, but for me it seem a good idea to practice building coreboot for QEMU in order to gain better understanding about coreboot before I start working with hardware. So my question is: Why listed examples are out of date? Is it because there is no much of benefit to play with QEMU/coreboot, or just because there is no human resources to maintain up to date version of the tutorial and ready-build images? Thank you, Svetoslav Trochev [1] http://www.coreboot.org/QEMU </pre> Svetoslav Trochev 2013-06-07T01:11:26 http://comments.gmane.org/gmane.linux.bios/77344 <pre> Hi, Is it possible to build a single rom which is able to run on two different boards? Background: qemu recently got an emulation for a more recent chipset. Current seabios roms detect at runtime whenever runs on the old (i440fx + piix4) or the new (q35 + ich9) and initializes the hardware accordingly. I'd like to do the same with coreboot if possible. Drivers seem to be kicked by hardware detection (struct pci_driver), so it looks like simply compiling in two southbridges could work. Tried, got duplicate symbols. Hmm. There also is no obvious way to have two devicetrees and pick one of them at runtime. Same with acpi tables. Comments? Suggestions? thanks, Gerd </pre> Gerd Hoffmann 2013-06-06T14:44:13 http://comments.gmane.org/gmane.linux.bios/77338 <pre>Looking at src / northbridge / amd / lx / northbridge.c I see a the following lines: 400 static void pci_domain_enable(device_t dev) 401 { 402 printk(BIOS_SPEW, "&gt;&gt; Entering northbridge.c: %s\n", __func__); 403 404 // do this here for now -- this chip really breaks our device model 405 northbridge_init_early(); 406 cpubug(); 407 chipsetinit(); http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/northbridge/amd/lx/northbridge.c;h=6eae35298ac13b29b3815a72378b9f09e90d8dd5;hb=HEAD#l404 Can somebody tell me why "this chip really breaks our device model"? And what would be the correct way to do it? thanks -- Christian Gmeiner, MSc </pre> Christian Gmeiner 2013-06-03T08:39:02 http://comments.gmane.org/gmane.linux.bios/77337 <pre>Hi, Which supported laptop is the most free? According to the laptop section of: http://www.coreboot.org/Supported_Motherboards#Laptops The the status of the Roda and Getac board (both "OK") doesn't link to anything. Is the implication that coreboot works flawlessly on these boards? And how bad is the proprietary code? Can Getac and Roda still spy on me with it? I'd like to get a chromebook. The status is "OK" but links to a page that says there are proprietary components. What is microcode? What is MRC.bin and ME.bin? Again, can google control my laptop with this code? Finally, if the above options don't pan out, I could get a Lenovo. The X60[s] and T60[p] made no mention of proprietary code. :) Can anyone confirm this? That would be pretty sweet! The Lenovo X201 supports a faster cpu, but the status links to a page that says it has proprietary components too...anyone know anything about these proprietary components? I don't want Lenovo sending my laptop secret messages! Any advice would be greatly </pre> slhac tivist 2013-06-03T01:54:04 http://comments.gmane.org/gmane.linux.bios/77321 <pre>Hi, I am that guy that never seems to get VX900 working properly. I've recently received some code[1] for the VX900 from VIA. It is based on a coreboot fork from about 2009. Rather than try to continue my own VX900 effort, I think it is better to use the code provided by VIA, and clean that one up. I don't have the SVN history for the code, but Cristi was able to trace it back to somewhere around hash a9c5ea08d07d343d32d4c083a232107bd84d8064 VIA has no interest in maintaining or rebasing the code, so we're on our own here. The good news is that using this code will reduce the time needed to complete the VX900 port significantly. I therefore ask the gurus, "What is the best way to go about this?" Let's hope we can get this code working with our current master. If we manage to rebase it, I can clean it up, and optimize it a bit. Alex [1] http://g-tech.no-ip.org/~mrnuke/coreboot_vx900_vt8595a.tgz </pre> Alex G. 2013-05-30T05:33:08 http://comments.gmane.org/gmane.linux.bios/77317 <pre>As I am not subscribed to this mailing list, I ask that all responders CC me. Please let me know if someone responded and didn't CC me so I can check the archives; it would be a shame for me not to get that message. After searching the mailing list archives, Google, &lt;http://www.coreboot.org/Supported_Motherboards&gt;, and &lt;http://www.coreboot.org/Supported_Chipsets_and_Devices&gt;, I was pretty surprised to find that there isn't a lot of information on newer motherboards for Coreboot installation. I asked on the #coreboot IRC channel, and they said that the Supported Motherboards page just isn't updated as frequently any more, so I went to this list. From what I gather, if I want to build a PC with an Intel i7 CPU and some higher-end NVidia GPU, I'll need a motherboard that supports the LGA1155 socket, and it seems that none of the boards on the Supported Motherboards page support that socket. How is Coreboot support for motherboards that support these sockets? Would, for example, the AMD FX 4300, AMD FX 6300, </pre> Harry Prevor 2013-05-26T03:41:58 http://comments.gmane.org/gmane.linux.bios/77308 <pre>Hello Students, Congratulations, your projects have been selected for coreboot GSoC 2013. We are now in the bonding period where students get to become more familiar with the community and mentors. Students should feel free to contact any mentor, student, or the community in general about their project or general coreboot development. Please start a dialog with your assigned mentors in IRC and email. Student - Mentors ---------------------------- Kyösti Mälkki (kmalkki) - Marc (marcj), Aaron (adurbin) Stefan (stefanct) - Carl-Daniel Hailfinger (carldani), David Hendricks (dhendrix) Alex Gagniuc (mrnuke) - Peter Stuge (CareBear\) Josh Roys () Alex () - Patrick Georgi (patrickg), Martin Roth (martinr) Ayush Sagar() - Stefan Reinauer (stepan), Dave Frodin (sage_dave) Standby mentors: Ron (rminnich), Jason Wang(), Rodolf Marek (ruik) Patrick will send you each student a coreboot blog account. By June 7, You should post an introductory blog post to introduce yourself and your project. Maybe make som</pre> Marc Jones 2013-05-28T18:41:45 http://comments.gmane.org/gmane.linux.bios/77305 <pre>Hi all, I read the kernel sources today, looking for a way of doing native init for AMD boards like the F2A85-M. My CPU has a Radeon HD 7660D built in; lspci says 00:01.0 VGA ... Trinity [Radeon HD 7660D] drivers/gpu/drm/radeon/radeon_asic.c - int radeon_asic_init() handles Trinity like this: case CHIP_ARUBA: rdev-&gt;asic = &amp;trinity_asic; /* set num crtcs */ rdev-&gt;num_crtc = 4; break; trinity_asic.init = cayman_init(), which can be summarized as - radeon_get_bios() - radeon_atombios_init() - if (!radeon_card_posted()) atom_asic_init() - bring up device: r600_scratch_init(), radeon_surface_init(), radeon_get_clock_inf() - bring up memory: evergreen_mc_init(), radeon_bo_init(), r600_ring_init() - cayman_startup(): load ucode, ... Once cayman_init() and radeon_asic_init() are done, control goes back to drivers/gpu/drm/radeon/radeon_kms.c - int radeon_driver_load_kms(), with: r = radeon_modeset_init(rdev); if (r) dev_err(&amp;dev-&gt;pdev-&gt;dev, "Fatal error during modeset init\n"); /* Call </pre> David Hubbard 2013-05-28T04:45:09 http://comments.gmane.org/gmane.linux.bios/77303 <pre>Hi, are there any plans in the coreboot community to support the Freescale i.MX6 ARM Cortex A8 processor in the near future. The new wandboard platform (http://www.wandboard.org) could be interesting for this. Regards, Wolfgang Kamp </pre> Wolfgang Kamp - datakamp 2013-05-27T11:08:38 http://comments.gmane.org/gmane.linux.bios/77300 <pre>Hi, I am working on a Micros WS4 that's built around the AMD SC3200 (the GX1 and companion chip integrated into one silicon) and boots Windows CE from ROM. I need to turn it into a generic purpose PC, so I am trying to extend Coreboot to handle it. The SC3200 datasheet is at http://www.manualslib.com/manual/5433/Amd-Geode-Sc3200.html Since Coreboot already supports the GX1, I hope it won't take too much time to support this board. The attached patches are the first steps to allow hardware discovery on this machine. The first patch adds mingw32ce support to superiotool: - direct inb/outb allowed under WinCE without iopl/ioperm - to handle I/O, sys/io.h is copied from Fedora, slightly modified and renamed to mingwce-io.h - executable suffix support is added to the Makefile - a script to compile superiotool.exe for WinCE CONFIG_PCI=yes is also supported with zlib support and I have modified sources for pciutils-3.1.9 (lspci only) and zlib-1.2.7. Now I can run lspci and superiotool under Windows CE 4.2 fo</pre> Boszormenyi Zoltan 2013-05-26T15:26:09 Search the mailing list at Gmane query http://search.gmane.org/?group=$group=gmane.linux.bios