gmane.technology.electronics.signal-integrity

AC DC SPEC FOR POWER PINS

vinod ah — 2013-05-24T05:01:51

Hi All,
Have a very basic question on AC DC spec provided to power pins of an
ASIC/IO Controller.

I am working on PLL Characterisation and i find that supply voltage for
that PLL is from an Pin which is 1.2V powered. AC spec is +-2% while DC
spec is +-4%.

I assume that AC spec means ripple while DC spec means supply voltage
tolerance (not ripple).

So was wondering how is the AC DC spec derived in the first place?

Regards
Vinod A H


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the relationship of tck(avg) and CL in DDR3 spec

jackle zheng — 2013-05-23T03:18:05

hi, member,
I was testing my EP board on DDR3 compliance, my  tck(avg) was smaller than
spec. So, i checked the DDR3 spec, i found tck(avg) is correlated with CL
value. my question is what is the relationship of the two parameters???
any comment is appreciated.

Presentation on bidirectional SET2DIL May 30 8:00AM and 5:00PM PDT

Loyer, Jeff — 2013-05-22T14:44:56

For those who are using SET2DIL (Single Ended TDR to Differential Insertion Loss),
I will be offering a 1 hour on-line presentation (and audio bridge) on a forthcoming improvement to the technique Thursday, May 30 at 8:00AM and 5:00PM PDT.
In short, we have found that due to the asymmetric nature of soldermask on microstrip traces, SET2DIL should excite the DUT from both directions and sum all terms for best results.

We haven't studied stripline traces enough to know if they are similarly affected by asymmetric factor(s).

If you would like to attend but haven't yet received an invitation to the presentation, please e-mail me and I will send you the logistics.

Thank you,
Jeff Loyer


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DDR2 length matching address and clock

Balamanikandan K — 2013-05-22T06:38:16

Dear Experts,

This is regarding the trace length matching between DDR2 address and clock
signals.

*As per my understanding, **the CLK should be centered within** **address
eye to measure and match the trace length.  i.e. signals should like as
shown in figure.*


**
*[image: Inline image 1]*
**

**

I am using Hyperlynx tool for simulation.


Address line is connected from a processor to only one DDR2 DRAM(Not DIMM).

I am using a separate PLL clock driver which drives the clock to only one
DRAM.

No transmission lines are used (direct connection between driver and
memory). Terminations are provided.

*Under direct connections and equal load ( only one DRAM) :*

*
*

If the length adjustment measurement is to be right, then there should not
be any time difference (skew) between the clock signal and address signal
when the signal rises at the output of the drivers.


We have probed signals at the die as well as the pin of the driver output.


But the simulation results show the time difference. Clock signal advances
by 200 ps when compared the address signal.


When the skew at the output of the drivers is equal to zero, then only it
makes sense in probing the signals at the receiver and we can adjust and
keep the clock in center of the address eye.


Why there is a shift? Is this something related to ibis model? How to
correct it?


*Please clarify the doubts. Please Suggest me good guidelines if the
procedure followed by me is wrong.*

Employment opportunity at Qualcomm for High-Speed Digital Hardware Characterization Engineer

Jagadeesh Gownipalli — 2013-05-21T20:49:37

We have immediate openings in our High-Speed SERDES design
validation/Characterization team. We are looking for people with 3-10 years
experience in High Speed SERDES validation/characterization, signal
integrity, PCB design
Below is the description of the Job . If you are intrested please apply at
the link High-Speed Digital Hardware Test
Engineer<http://jobs.qualcomm.com/public/jobDetails.xhtml?requisitionId=1886271>

  Posting Title

High-Speed Digital Hardware Characterization Engineer





  Job Function

As part of the HSWP (High-Speed Wired Peripheral) organization within QCT,
you will be responsible for bench characterization of Digital High-Speed
Physical Layer SERDES (USB, SATA, PCIe,SGMII/QSGMII, MIPI PHY ,
HDMI,LVDS,eDP). Our goal/mission is to ensure that our products are
manufacturable, and exceed the performance expectations of our global
customers.







  Skills/Experience

Candidate must be proficient in test/characterization of High-Speed SERDES
(USB, SATA, PCIe,SGMII/QSGMII, MIPI PHY , HDMI, LVDS,eDP) on custom bench
test platforms. Position requires a working knowledge in the areas of board
design, transmission line theory, High-Speed signal integrity,
de-embedding, and port extension. Hands on knowledge of oscilloscopes,
network / spectrum analyzers, signal generators, and logic analyzers is a
must; experience with Agilent test equipment a plus. Software programming
skills must include C-Sharp (or equivalent) and LabView. Position requires
the ability to work with cross-functional teams, and candidate must have
excellent communication skills.







  Educational Requirements

Preferred: MSEE with 3+ yrs experience Minimum: BSEE 5+ yrs experience
*LI-SRC


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mlcc capacitors with silver-palladium termination

Jan Vercammen — 2013-05-21T08:37:19

Hi,
can anyone point me to a vendor who can supply 0201 size capacitors with
a 6.3V rating (capacitance values 47nF, 68nF, 100nF and 1uf (or 470nf)
but with a silver-palladium termination for conductive epoxy assembly

I have checked DigiKey, Farnell and several large manufacturers of
passive components  but without success

Kind Regards,

Jan Vercammen | Agfa HealthCare
Hardware/RF/EMC/Analog Designer | HE/Architecture & Design Mortsel
T  +32 3444 6233 | F  +32 3 444 6268

Agfa HealthCare NV, Septestraat 27, 2640 Mortsel, Belgium
http://www.agfahealthcare.com
http://blog.agfahealthcare.com
R.O.: Septestraat 27, B-2640 Mortsel, Belgium | RLE Antwerp | VAT BE 
0403.003.524 | IBAN Operational Account BE81363012356224 | IBAN Customer 
Account BE20375104592856 | ING Belgium NV, B-1000 Brussels
Click on link to read important disclaimer: 
http://www.agfahealthcare.com/maildisclaimer 



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Causality Condition -why real and imaginary part of a Frequency response of causal system need to be even and odd respectively

piyush bhatt — 2013-05-18T10:46:48

Hi All
An LTI system is causal if and only if h(t)=0 for t<0.

As derivation goes h(t)=h(t)sgn(t).Taking Freq transform both side and
doing some manipulations.We get to point that H(jw) = Hilbert transform of
itself.

Then they say we can divide H(jw) into real and imaginary part.And real
part will be even function and imaginary part will be odd function.

Can you tell me why real part will be even function and imaginary part will
be odd function?

regards
Piyush


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POE Circuitry

sunil bharadwaz — 2013-05-18T09:45:38

Hi Friends ,
I was going through some of the POE ( Power over Ethernet ) circuits available .
Design spec is 48V to 5V or 48V to 3.3V < at > 2.5 to 3 Amps .

I will be helpful if some one can share the info or point me to the 

right links .Are there any simulation models available ?


Thanks in Advance !!


Regards
Sunil


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Employment Opportunity with Oracle (Burlington, MA)

Jason Miller — 2013-05-17T16:49:07

We have an opening within the Oracle SPARC Processor Group for a signal 
integrity engineer with 3-7 years of relevant industry experience in 
packaging and board design/analysis. The job location is Burlington, MA. 
Please find the job description and requirements below. To apply for 
this position, please use the link below.

Please email me directly at jason.miller-QHcLZuEGTsvQT0dZR+AlfA< at >public.gmane.org with any questions.

------------------------------------------------------------------------------------------------------------------------------------
Description
Our organization is looking for a highly motivated, dedicated team 
member to perform signal integrity modeling, design and characterization 
of server hardware including packages and PCBs.

Signal Integrity engineers participate in all phases of the system 
life-cycle including:
-         Initial concept/architecture
-         Simulation/correlation of high speed passive channels
-         Creation of design rules, driving physical layout and review
-         Bring-up and validation of systems

Job Requirements
- Duties and tasks are varied and complex needing independent judgment
- May have project lead role and or supervise junior engineers
- Ideal candidate will have M.S. or Ph.D in Electrical Engineering or 
Computer Science
- 3-7 years relevant experience in signal integrity
- Experience with printed circuit board design and/or packages
- Background in high-frequency design techniques
- Experience analyzing and optimizing  passive channels in both time and 
frequency domain
- Experience with high-speed simulation tools and field solvers (ADS, 
CST, HFSS, MATLAB)
- Ability to perform multi-GB/s VNA measurements
- Familiar with N-port network analysis (S-parameters, ABCD-parameters)
- Familiar with Cadence Allegro layout tools

To apply:
http://tinyurl.com/IRC2135772
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enforcing passivity on s-parameter

Amit Kumar — 2013-05-16T05:41:13

Hello Experts,
Many a times I face convergence issues in simulation because of s-parameter.
I then enforce passivity on s-parameter and it does work most of the times.
The question I have is : Can we trust the results we get after enforcing passivity on s-parameter or enforcing passivity spoils the s-parameter?

Regards
Amit

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PCB Simulations

Brendan Simpson — 2013-05-13T20:24:53

Hello Experts,

Does anybody know of a cheap (read: Free) PCB simulation software for doing somewhat basic SI evaluations? I had a thought that maybe I could make a program to import a netlist and gerber files to generate the models necessary for analysis, but if someone else has already done this, it would be better. It doesn't have to be super powerful or super accurate. I do a lot of board layout work, but I do not have a lot of experience modeling complete PCBs. 

Thanks in advance,
Brendan------------------------------------------------------------------
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REG:setting the crosstalk voltage limit

Balajy Kumar -ERS, HCL Tech — 2013-05-13T09:50:12

Hi
I am doing crosstalk analysis for my board. Could you please explain how to set the max allowable crosstalk voltage limit?

Thanks
Balajy

From: Balajy Kumar -ERS, HCL Tech
Sent: Monday, April 22, 2013 7:48 PM
To: 'si-list-uGLqWuYN4qMgsBAKwltoeQ< at >public.gmane.org'
Subject: REG:Splitting LVDS signals into T topology

Hi

I split the differential LVDS pair signals into a T-topology for my project and the simulated it. But I observed more ringing in the signals. Can please clarify how it will affect the functionality of the system?

Thanks
Balajy

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where is the differnence about the JK paired jitter, KJ paired jitter, consecutive jitter in USB compliance test

jackle zheng — 2013-05-13T04:30:14

hi, all,
this is my first time to do USB2.0 compliacne test. Equiped the tek's USB
compliance test kit. I get the data of differnent jitters, but it is only
some value, i want to know the backside of these data.
There are some questions about these jitters:
1. why there are so many jitter test case, if me, there is JK jitter the
only needed?
2. where is the different among the three jitter test cases?

DDR3 derate

jun li — 2013-05-10T03:29:53

Hi experts,
Some Register of RDIMM compliance to JEDEC spec and there is no derating information in the JEDEC spec. Under this condition, are formula below accurate enough for penalty calculation?
thanks
Jun

Derating < at >AC175 = 175ps - 175mV/SR, where SR is Slew Rate Derating < at >AC150 = 150ps - 150mV/SR Derating < at >DC100 = 100ps - 100mV/SR

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anti-resonance point when use Embedded Capacitance Material

Bruce — 2013-05-09T06:26:39

Hi Expert

We use Embedded Capacitance Material for better PDN and less capacitor
component. According to PDN Simulation. We notice that is an anti-resonance
point between capacitor and Plane.

We can find that when use Embedded Capacitance Material. There are much
better in most frequency but near anti-resonance point.

In this case. We have to solution.

1. Try to reduce the anti-resonance point. We need many high frequency
capacitor component. That is not good because we want to reduce the number
of capacitor component. Our purpose is reduce 70% number of capacitor
component.

2. Keep this anti-resonance point. That maybe have a risk if there is
some noise by chance in this frequency

How about your suggestion? Please let me know if my question is not clear
enough.

Thanks

Best Regards,

Bruce Wu

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test

Heyfitch — 2013-05-06T23:32:22

test

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European IBIS Summit Agenda - May 15, 2013

Bob Ross — 2013-05-06T17:52:05

All:
 

The 16th European IBIS Summit is on Wednesday afternoon and

follows the IEEE Workshop on Signal and Power Integrity:

 

  http://www.spi2013.org/

 

Below is the meeting agenda.  The IBIS meeting is free.  If

you plan to attend, please register with Lance Wang as noted at

the end.

 

Lance Wang

IO Methodology

 

------------------------------------------------------------------

 

                AGENDA, EUROPEAN IBIS SUMMIT MEETING

                      Wednesday, May 15, 2013

 

                     Hyatt Regency Paris Etoile

             (NOTE: formerly Hotel Concorde La Fayette)

                     3, Place du Général Koenig 

                         Paris, France, 75017

 

                     http://tinyurl.com/bna6xrz

                                          

               Room: Pissaro-Cezanne (Check at Entrance)

 

------------------------------------------------------------------

 

13:00  SIGN IN

 

13:15  WELCOME AND INTRODUCTIONS

       Lance WANG, IO Methodology, IBIS Vice Chair, USA

 

13:30  IBIS Modeling for Load Dependent Current Model Differential

       Driver

       Lance WANG, IO Methodology, USA

 

13:50  X2IBIS: Using X-parameters to Generate IBIS Models

       Thomas COMBERIATE and Jose SCHUTT-AINE

       University of Illinois, USA

       (Presented by Thomas COMBERIATE, USA)

 

14:30  Thevenin's Theorem Revisited. A New Approach to IC Buffer

       Modeling and It's Relation to IBIS

       Igor STIEVANO*, Cherif DIOUF**, Mihai TELESCU**, N. TANGUY**,

       and Flavio CANAVERO*

       *Politecnico di Torino, Italy;      

       **Université Européenne de Bretagne, Université de Brest,

       France

       (Presented by Mihai TELESCU, France)      

 

15:00  A Novel Two-Port Behavioral Model for I/O Buffer

       Overclocking Simulation

       Wael DGHAIS,

       University of Averio, Institue of Telecommunications,

       Portugal

 

15:30  BREAK (15 Minutes)

 

15:45  Novel Extraction of Table-Based I-Q Behavioral Model for

       High-Speed Digital Buffers/Drivers

       Wael DGHAIS,

       University of Averio, Institue of Telecommunications,

       Portugal

 

16:15  Interconnect Modeling Update - EMD Specification

       Randy WOLFF, Micron Technology, USA

 

16:45  Ibischk5 Specification and Parser

       Bob ROSS* and Mike LABONTE**,

       *Teraspeed Consulting Group and

       **Signal Integrity Software (SiSoft), USA

       (Presented by Anders EKHOLM, Ericsson, Sweden)

 

17:30  DISCUSSION AND CLOSING REMARKS

       Lance WANG, IO Methodology, USA

 

18:00  END OF MEETING

 

------------------------------------------------------------------

 

REGISTRATION INFORMATION

 

People involved in IBIS Model development, EDA tool development, and

digital circuit design are invited to participate to the Summit

meeting. If you plan to participate, please register with the

information below:

 

   Name:

   E-mail address:

   Company:

   Telephone:

 

Send to:

 

   Lance WANG (lwang-3BVGG/wVSPbQT0dZR+AlfA< at >public.gmane.org)

 

SPONSORS:

 

   Micron Technology and Zuken

SPI CONFERENCE INFORMATION AND TRAVEL DIRECTIONS

 

   See http://www.spi2013.org/ for travel directions,

   IBIS meeting hotel and other information.

 

------------------------------------------------------------------

 

--

Bob Ross

Teraspeed Consulting Group, LCC

http://www.teraspeed.com

bob-3mpTjvN7S/4yY3YROqfsYA< at >public.gmane.org

Direct : 503-246-8048

Teraspeed Labs: 971-279-5325

Headquarters: 401-284-1827

 

Teraspeed is a registered service mark of Teraspeed Consulting Group LLC

 

 


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BER Failure due to Sj

vinod ah — 2013-05-06T04:16:28

Hi All,
I was trying to characterize the USB3 Rx section using loopback testing
where i feed a stressed eye on Rx (180mV eye height, Rj of 2.4ps rms) and
loop it back on Tx and measure BER for various Sj (Sinusoidal Jitter)
amplitude & frequency i.e. Jitter tolerance test.

What i see is, if i increase Sj frequency beyond the 10MHz (CDR in Rx is
having JTF of 3.5MHz), then i see lot of bit errors. Tried increasing the
eye height fed to Rx pins, still the errors are seen, thus concluding the
issue is with eye width, but not eye height.

I am using DFE equalisation to open up the eye in Rx. Need
suggestions/experiments to be done so as to further narrow down the issue.
I am not sure on what else to check for to debug this issue as the
Sj frequencies at which failure is seen is out of CDR tracking frequency,
thus eating up the eye width.

Regards
Vinod A H


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Using terminations instead of Receiver AMI

Balaji G — 2013-05-04T07:34:25

Hi all,
   Compliance of High speed signals like PCIe, SAS are generally done with
external adapter board which captures only the transmitter waveform based
on the cursor coefficients < at >transmitter, but using IBIS-AMI models for High
speed SERDES links in simulation help us to get the reconstructed eye
< at >receiver after equalization. In order to correlate the measured and
simulated results, Is it possible to simulate with receiver  end terminated
and use only transmitter AMI?. Is this a correct method of correlating
with measurement?  I guess we had a discussion on this earlier here, but I
am not still sure on the possibility.


Regards,
Balaji


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Reply: sunil_bharadwaz

sunil bharadwaz — 2013-04-30T21:15:01

http://dtmf-china.com/greatst.php





**********************************************************************
_____

sunil bharadwaz


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perturbation of conductor

bala — 2013-04-30T11:39:38

Hi,
While defining stripline in Hspice netlist,I could see perturbation of
conductor width added(XW),Could you please explain the importance of this
parameter in Hspcie simulation.