http://blog.gmane.org/gmane.linux.uclinux.devel hourly 1 1901-01-01T00:00+00:00 http://gmane.org/img/gmane-25t.png http://gmane.org http://comments.gmane.org/gmane.linux.uclinux.devel/20458 <pre>The m5441x enet-fec aren't quite the same as the fec found on other Coldfire parts, so we need a quirk to help the fec do the right thing and on the twr-mcf5441x atleast, we need to force the phy into RMII mode. Signed-off-by: Steven King &lt;sfking&lt; at &gt;fdwdc.com&gt; --- arch/m68k/platform/coldfire/device.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/arch/m68k/platform/coldfire/device.c b/arch/m68k/platform/coldfire/device.c index 11ecd23..ab88b69 100644 --- a/arch/m68k/platform/coldfire/device.c +++ b/arch/m68k/platform/coldfire/device.c &lt; at &gt;&lt; at &gt; -13,6 +13,7 &lt; at &gt;&lt; at &gt; #include &lt;linux/io.h&gt; #include &lt;linux/spi/spi.h&gt; #include &lt;linux/gpio.h&gt; +#include &lt;linux/fec.h&gt; #include &lt;asm/traps.h&gt; #include &lt;asm/coldfire.h&gt; #include &lt;asm/mcfsim.h&gt; &lt; at &gt;&lt; at &gt; -89,6 +90,18 &lt; at &gt;&lt; at &gt; static struct platform_device mcf_uart = { }; #ifdef CONFIG_FEC + +#ifdef CONFIG_M5441x +#define FEC_NAME"enet-fec" +static struct fec_platform_data fec_pdata = { +.phy= PHY_INTERFACE_MODE_RMII, +}; +#define FEC_PDATA(&amp;fec_pdata) +#else +#define FEC_NAME"fec" +#define FEC_PDATANULL +#endif + /* *Some ColdFire cores contain the Fast Ethernet Controller (FEC) *block. It is Freescale's own hardware block. Some ColdFires &lt; at &gt;&lt; at &gt; -118,10 +131,11 &lt; at &gt;&lt; at &gt; static struct resource mcf_fec0_resources[] = { }; static struct platform_device mcf_fec0 = { -.name= "fec", +.name= FEC_NAME, .id= 0, .num_resources= ARRAY_SIZE(mcf_fec0_resources), .resource= mcf_fec0_resources, +.dev.platform_data= FEC_PDATA, }; #ifdef MCFFEC_BASE1 &lt; at &gt;&lt; at &gt; -149,10 +163,11 &lt; at &gt;&lt; at &gt; static struct resource mcf_fec1_resources[] = { }; static struct platform_device mcf_fec1 = { -.name= "fec", +.name= FEC_NAME, .id= 1, .num_resources= ARRAY_SIZE(mcf_fec1_resources), .resource= mcf_fec1_resources, +.dev.platform_data= FEC_PDATA, }; #endif /* MCFFEC_BASE1 */ #endif /* CONFIG_FEC */ _______________________________________________ uClinux-dev mailing list uClinux-dev&lt; at &gt;uclinux.org http://mailman.uclinux.org/mailman/listinfo/uclinux-dev This message was resent by uclinux-dev&lt; at &gt;uclinux.org To unsubscribe see: http://mailman.uclinux.org/mailman/options/uclinux-dev </pre> Steven King 2012-05-23T21:52:40 http://comments.gmane.org/gmane.linux.uclinux.devel/20454 <pre>The 5441x (54410/54415/54416/54417/54418) is similar to the 532x in the same way the 532x is similar to the 5208; it doesn't have either IPSBAR nor MBAR, instead everything resides at a fixed address. Many of the registers common between the 5441x and the 532x live at the same address as the 532x, but of course the 5441x has a v4e core, cache and mmu, along with 10 uarts! 6 i2c controllers, 4 dma capable spi controllers, usb and much more. This patch is just a quick and dirty hack to get it booting on the twr-mcf5441x board. Its currently nommu only (well, I havent even tried it with the mmu), It doesnt include support for the 2 fec controllers, the ones on the 5441x are just slightly different in some non obvious way so they dont quite work yet. Signed-off-by: Steven King &lt;sfking&lt; at &gt;fdwdc.com&gt; --- arch/m68k/Kconfig.cpu | 7 + arch/m68k/Kconfig.machine | 1 - arch/m68k/Makefile | 1 + arch/m68k/include/asm/gpio.h | 11 +- arch/m68k/include/asm/m5441xsim.h | 252 +++++++++++++++++++++++++++++++ arch/m68k/include/asm/m54xxacr.h | 4 + arch/m68k/include/asm/mcfsim.h | 2 + arch/m68k/include/asm/mcftimer.h | 2 +- arch/m68k/platform/coldfire/Makefile | 1 + arch/m68k/platform/coldfire/device.c | 38 ++++- arch/m68k/platform/coldfire/intc-simr.c | 24 ++- arch/m68k/platform/coldfire/m5441x.c | 51 +++++++ arch/m68k/platform/coldfire/timers.c | 2 +- 13 files changed, 382 insertions(+), 14 deletions(-) diff --git a/arch/m68k/Kconfig.cpu b/arch/m68k/Kconfig.cpu index 8a9c767..3221433 100644 --- a/arch/m68k/Kconfig.cpu +++ b/arch/m68k/Kconfig.cpu &lt; at &gt;&lt; at &gt; -252,6 +252,13 &lt; at &gt;&lt; at &gt; config M548x help Freescale ColdFire 5480/5481/5482/5483/5484/5485 processor support. +config M5441x +bool "MCF5441x" +select MMU_COLDFIRE if MMU +select HAVE_CACHE_CB +help + Freescale Coldfire 54410/54415/54416/54417/54418 processor support. + endif # COLDFIRE diff --git a/arch/m68k/Kconfig.machine b/arch/m68k/Kconfig.machine index 7cdf6b0..7031173 100644 --- a/arch/m68k/Kconfig.machine +++ b/arch/m68k/Kconfig.machine &lt; at &gt;&lt; at &gt; -428,7 +428,6 &lt; at &gt;&lt; at &gt; config SAVANTrosie1 help Support for the Savant Rosie1 board. - if !MMU || COLDFIRE comment "Machine Options" diff --git a/arch/m68k/Makefile b/arch/m68k/Makefile index 804f139..6940baf 100644 --- a/arch/m68k/Makefile +++ b/arch/m68k/Makefile &lt; at &gt;&lt; at &gt; -34,6 +34,7 &lt; at &gt;&lt; at &gt; cpuflags-$(CONFIG_M68030):= cpuflags-$(CONFIG_M68020):= cpuflags-$(CONFIG_M68360):= -m68332 cpuflags-$(CONFIG_M68000):= -m68000 +cpuflags-$(CONFIG_M5441x):= $(call cc-option,-mcpu=54455,-mcfv4e) cpuflags-$(CONFIG_M54xx):= $(call cc-option,-mcpu=5475,-m5200) cpuflags-$(CONFIG_M5407):= $(call cc-option,-mcpu=5407,-m5200) cpuflags-$(CONFIG_M532x):= $(call cc-option,-mcpu=532x,-m5307) diff --git a/arch/m68k/include/asm/gpio.h b/arch/m68k/include/asm/gpio.h index 00d0071..f5b462a 100644 --- a/arch/m68k/include/asm/gpio.h +++ b/arch/m68k/include/asm/gpio.h &lt; at &gt;&lt; at &gt; -37,7 +37,8 &lt; at &gt;&lt; at &gt; #if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \ defined(CONFIG_M520x) || defined(CONFIG_M523x) || \ defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ - defined(CONFIG_M532x) || defined(CONFIG_M54xx) + defined(CONFIG_M532x) || defined(CONFIG_M54xx) || \ + defined(CONFIG_M5441x) /* These parts have GPIO organized by 8 bit ports */ &lt; at &gt;&lt; at &gt; -70,7 +71,8 &lt; at &gt;&lt; at &gt; #define mcfgpio_port(gpio)((gpio) / MCFGPIO_PORTSIZE) #if defined(CONFIG_M520x) || defined(CONFIG_M523x) || \ - defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x) + defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ + defined(CONFIG_M532x) || defined(CONFIG_M5441x) /* * These parts have an 'Edge' Port module (external interrupt/GPIO) which uses * read-modify-write to change an output and a GPIO module which has separate &lt; at &gt;&lt; at &gt; -82,6 +84,11 &lt; at &gt;&lt; at &gt; * read-modify-write as well as those controlled by the EPORT and GPIO modules. */ #define MCFGPIO_SCR_START40 +#elif defined(CONFIG_M5441x) +/* + * The 5441x EPORT can't be used for GPIO. + */ +#define MCFGPIO_SCR_START0 #else #define MCFGPIO_SCR_START8 #endif diff --git a/arch/m68k/include/asm/m5441xsim.h b/arch/m68k/include/asm/m5441xsim.h new file mode 100644 index 0000000..a7900a5 --- /dev/null +++ b/arch/m68k/include/asm/m5441xsim.h &lt; at &gt;&lt; at &gt; -0,0 +1,252 &lt; at &gt;&lt; at &gt; +/* + *m5441xsim.h -- Coldfire 5441x register definitions + * + *(C) Copyright 2012, Steven King &lt;sfking&lt; at &gt;fdwdc.com&gt; +*/ + +#ifndef m5441xsim_h +#define m5441xsim_h + +#define CPU_NAME"COLDFIRE(m5441x)" +#define CPU_INSTR_PER_JIFFY2 +#define MCF_BUSCLK(MCF_CLK / 2) + +#include &lt;asm/m54xxacr.h&gt; + +/* + * Reset Controller Module. + */ + +#defineMCF_RCR0xFC0A0000 +#defineMCF_RSR0xFC0A0001 + +#defineMCF_RCR_SWRESET0x80/* Software reset bit */ +#defineMCF_RCR_FRCSTOUT0x40/* Force external reset */ + +/* + * Interrupt Controller Modules. + */ +/* the 5441x have 3 interrupt controllers, each control 64 interrupts */ +#define MCFINT_VECBASE64 +#define MCFINT0_VECBASEMCFINT_VECBASE +#define MCFINT1_VECBASE(MCFINT0_VECBASE + 64) +#define MCFINT2_VECBASE(MCFINT1_VECBASE + 64) + +/* interrupt controller 0 */ +#define MCFINTC0_SIMR0xfc04801c +#define MCFINTC0_CIMR0xfc04801d +#defineMCFINTC0_ICR00xfc048040 +/* interrupt controller 1 */ +#define MCFINTC1_SIMR0xfc04c01c +#define MCFINTC1_CIMR0xfc04c01d +#defineMCFINTC1_ICR00xfc04c040 +/* interrupt controller 2 */ +#define MCFINTC2_SIMR0xfc05001c +#define MCFINTC2_CIMR0xfc05001d +#defineMCFINTC2_ICR00xfc050040 + +/* on interrupt controller 0 */ +#define MCFINT0_EPORT01 +#define MCFINT0_UART026 +#define MCFINT0_UART127 +#define MCFINT0_UART228 +#define MCFINT0_UART329 +#define MCFINT0_I2C030 +#define MCFINT0_DSPI031 + +#define MCFINT0_TIMER032 +#define MCFINT0_TIMER133 +#define MCFINT0_TIMER234 +#define MCFINT0_TIMER335 + +#define MCFINT0_FECRX036 +#define MCFINT0_FECTX040 +#define MCFINT0_FECENTC042 + +#define MCFINT0_FECRX149 +#define MCFINT0_FECTX153 +#define MCFINT0_FECENTC155 + +/* on interrupt controller 1 */ +#define MCFINT1_UART448 +#define MCFINT1_UART549 +#define MCFINT1_UART650 +#define MCFINT1_UART751 +#define MCFINT1_UART852 +#define MCFINT1_UART953 +#define MCFINT1_DSPI154 +#define MCFINT1_DSPI255 +#define MCFINT1_DSPI356 +#define MCFINT1_I2C157 +#define MCFINT1_I2C258 +#define MCFINT1_I2C359 +#define MCFINT1_I2C460 +#define MCFINT1_I2C561 + +/* on interrupt controller 2 */ +#define MCFINTC2_RTC26 + +/* + * TIMER module. + */ +#define MCFTIMER_BASE10xFC070000/* Base address of TIMER1 */ +#define MCFTIMER_BASE20xFC074000/* Base address of TIMER2 */ +#define MCFTIMER_BASE30xFC078000/* Base address of TIMER3 */ +#define MCFTIMER_BASE40xFC07C000/* Base address of TIMER4 */ + +#define MCF_IRQ_TIMER(MCFINT0_VECBASE + MCFINT0_TIMER0) +#define MCF_IRQ_PROFILER(MCFINT0_VECBASE + MCFINT0_TIMER1) + +/* + * UART module. + */ +#define MCFUART_BASE00xfc060000/* Base address of UART0 */ +#define MCFUART_BASE10xfc064000/* Base address of UART1 */ +#define MCFUART_BASE20xfc068000/* Base address of UART2 */ +#define MCFUART_BASE30xfc06c000/* Base address of UART3 */ +#define MCFUART_BASE40xec060000/* Base address of UART4 */ +#define MCFUART_BASE50xec064000/* Base address of UART5 */ +#define MCFUART_BASE60xec068000/* Base address of UART6 */ +#define MCFUART_BASE70xec06c000/* Base address of UART7 */ +#define MCFUART_BASE80xec070000/* Base address of UART8 */ +#define MCFUART_BASE90xec074000/* Base address of UART9 */ + +#define MCF_IRQ_UART0(MCFINT0_VECBASE + MCFINT0_UART0) +#define MCF_IRQ_UART1(MCFINT0_VECBASE + MCFINT0_UART1) +#define MCF_IRQ_UART2(MCFINT0_VECBASE + MCFINT0_UART2) +#define MCF_IRQ_UART3(MCFINT0_VECBASE + MCFINT0_UART3) +#define MCF_IRQ_UART4(MCFINT1_VECBASE + MCFINT1_UART4) +#define MCF_IRQ_UART5(MCFINT1_VECBASE + MCFINT1_UART5) +#define MCF_IRQ_UART6(MCFINT1_VECBASE + MCFINT1_UART6) +#define MCF_IRQ_UART7(MCFINT1_VECBASE + MCFINT1_UART7) +#define MCF_IRQ_UART8(MCFINT1_VECBASE + MCFINT1_UART8) +#define MCF_IRQ_UART9(MCFINT1_VECBASE + MCFINT1_UART9) +/* + * FEC modules. + */ +#define MCFFEC_BASE00xfc0d4004 +#define MCFFEC_SIZE00x800 +#define MCF_IRQ_FECRX0(MCFINT0_VECBASE + MCFINT0_FECRX0) +#define MCF_IRQ_FECTX0(MCFINT0_VECBASE + MCFINT0_FECTX0) +#define MCF_IRQ_FECENTC0(MCFINT0_VECBASE + MCFINT0_FECENTC0) + +#define MCFFEC_BASE10xfc0d8004 +#define MCFFEC_SIZE10x800 +#define MCF_IRQ_FECRX1(MCFINT0_VECBASE + MCFINT0_FECRX1) +#define MCF_IRQ_FECTX1(MCFINT0_VECBASE + MCFINT0_FECTX1) +#define MCF_IRQ_FECENTC1(MCFINT0_VECBASE + MCFINT0_FECENTC1) +/* + * I2C modules. + */ +#define MCFI2C_BASE00xfc058000 +#define MCFI2C_SIZE00x20 +#define MCFI2C_BASE10xfc038000 +#define MCFI2C_SIZE10x20 +#define MCFI2C_BASE20xfc010000 +#define MCFI2C_SIZE20x20 +#define MCFI2C_BASE30xfc014000 +#define MCFI2C_SIZE30x20 +#define MCFI2C_BASE40xfc018000 +#define MCFI2C_SIZE40x20 +#define MCFI2C_BASE50xfc01c000 +#define MCFI2C_SIZE50x20 + +#define MCF_IRQ_I2C0(MCFINT0_VECBASE + MCFINT0_I2C0) +#define MCF_IRQ_I2C1(MCFINT1_VECBASE + MCFINT1_I2C1) +#define MCF_IRQ_I2C2(MCFINT1_VECBASE + MCFINT1_I2C2) +#define MCF_IRQ_I2C3(MCFINT1_VECBASE + MCFINT1_I2C3) +#define MCF_IRQ_I2C4(MCFINT1_VECBASE + MCFINT1_I2C4) +#define MCF_IRQ_I2C5(MCFINT1_VECBASE + MCFINT1_I2C5) +/* + * EPORT Module. + */ +#define MCFEPORT_EPPAR0xfc090000 +#define MCFEPORT_EPIER0xfc090003 +#define MCFEPORT_EPFR0xfc090006 + +/* + * GPIO Module. + */ +#define MCFGPIO_PODR_A0xec094000 +#define MCFGPIO_PODR_B0xec094001 +#define MCFGPIO_PODR_C0xec094002 +#define MCFGPIO_PODR_D0xec094003 +#define MCFGPIO_PODR_E0xec094004 +#define MCFGPIO_PODR_F0xec094005 +#define MCFGPIO_PODR_G0xec094006 +#define MCFGPIO_PODR_H0xec094007 +#define MCFGPIO_PODR_I0xec094008 +#define MCFGPIO_PODR_J0xec094009 +#define MCFGPIO_PODR_K0xec09400a + +#define MCFGPIO_PDDR_A0xec09400c +#define MCFGPIO_PDDR_B0xec09400d +#define MCFGPIO_PDDR_C0xec09400e +#define MCFGPIO_PDDR_D0xec09400f +#define MCFGPIO_PDDR_E0xec094010 +#define MCFGPIO_PDDR_F0xec094011 +#define MCFGPIO_PDDR_G0xec094012 +#define MCFGPIO_PDDR_H0xec094013 +#define MCFGPIO_PDDR_I0xec094014 +#define MCFGPIO_PDDR_J0xec094015 +#define MCFGPIO_PDDR_K0xec094016 + +#define MCFGPIO_PPDSDR_A0xec094018 +#define MCFGPIO_PPDSDR_B0xec094019 +#define MCFGPIO_PPDSDR_C0xec09401a +#define MCFGPIO_PPDSDR_D0xec09401b +#define MCFGPIO_PPDSDR_E0xec09401c +#define MCFGPIO_PPDSDR_F0xec09401d +#define MCFGPIO_PPDSDR_G0xec09401e +#define MCFGPIO_PPDSDR_H0xec09401f +#define MCFGPIO_PPDSDR_I0xec094020 +#define MCFGPIO_PPDSDR_J0xec094021 +#define MCFGPIO_PPDSDR_K0xec094022 + +#define MCFGPIO_PCLRR_A0xec094024 +#define MCFGPIO_PCLRR_B0xec094025 +#define MCFGPIO_PCLRR_C0xec094026 +#define MCFGPIO_PCLRR_D0xec094027 +#define MCFGPIO_PCLRR_E0xec094028 +#define MCFGPIO_PCLRR_F0xec094029 +#define MCFGPIO_PCLRR_G0xec09402a +#define MCFGPIO_PCLRR_H0xec09402b +#define MCFGPIO_PCLRR_I0xec09402c +#define MCFGPIO_PCLRR_J0xec09402d +#define MCFGPIO_PCLRR_K0xec09402e + +#define MCFGPIO_PAR_FBCTL0xec094048 +#define MCFGPIO_PAR_BE0xec094049 +#define MCFGPIO_PAR_CS0xec09404a +#define MCFGPIO_PAR_CANI2C0xec09404b +#define MCFGPIO_PAR_IRQ0H0xec09404c +#define MCFGPIO_PAR_IRQ0L0xec09404d +#define MCFGPIO_PAR_DSPIOWH0xec09404e +#define MCFGPIO_PAR_DSPIOWL0xec09404f +#define MCFGPIO_PAR_TIMER0xec094050 +#define MCFGPIO_PAR_UART20xec094051 +#define MCFGPIO_PAR_UART10xec094052 +#define MCFGPIO_PAR_UART00xec094053 +#define MCFGPIO_PAR_SDHCH0xec094054 +#define MCFGPIO_PAR_SDHCL0xec094055 +#define MCFGPIO_PAR_SIMP0H0xec094056 +#define MCFGPIO_PAR_SIMP0L0xec094057 +#define MCFGPIO_PAR_SSI0H0xec094058 +#define MCFGPIO_PAR_SSI0L0xec094059 +#define MCFGPIO_PAR_DEBUGH10xec09405a +#define MCFGPIO_PAR_DEBUGH00xec09405b +#define MCFGPIO_PAR_DEBUGl0xec09405c +#define MCFGPIO_PAR_FEC0xec09405e + +/* generalization for generic gpio support */ +#define MCFGPIO_PODRMCFGPIO_PODR_A +#define MCFGPIO_PDDRMCFGPIO_PDDR_A +#define MCFGPIO_PPDRMCFGPIO_PPDSDR_A +#define MCFGPIO_SETRMCFGPIO_PPDSDR_A +#define MCFGPIO_CLRRMCFGPIO_PCLRR_A + +#define MCFGPIO_IRQ_MAX8 +#define MCFGPIO_IRQ_VECBASEMCFINT_VECBASE +#define MCFGPIO_PIN_MAX112 + +#endif /* m5441xsim_h */ diff --git a/arch/m68k/include/asm/m54xxacr.h b/arch/m68k/include/asm/m54xxacr.h index 47906aa..192bbfe 100644 --- a/arch/m68k/include/asm/m54xxacr.h +++ b/arch/m68k/include/asm/m54xxacr.h &lt; at &gt;&lt; at &gt; -55,6 +55,10 &lt; at &gt;&lt; at &gt; #define ICACHE_SIZE 0x8000/* instruction - 32k */ #define DCACHE_SIZE 0x8000/* data - 32k */ +#elif defined(CONFIG_M5441x) + +#define ICACHE_SIZE 0x2000/* instruction - 8k */ +#define DCACHE_SIZE 0x2000/* data - 8k */ #endif #define CACHE_LINE_SIZE 0x0010/* 16 bytes */ diff --git a/arch/m68k/include/asm/mcfsim.h b/arch/m68k/include/asm/mcfsim.h index ebd0304..6e5a8cd 100644 --- a/arch/m68k/include/asm/mcfsim.h +++ b/arch/m68k/include/asm/mcfsim.h &lt; at &gt;&lt; at &gt; -43,6 +43,8 &lt; at &gt;&lt; at &gt; #include &lt;asm/mcfintc.h&gt; #elif defined(CONFIG_M54xx) #include &lt;asm/m54xxsim.h&gt; +#elif defined(CONFIG_M5441x) +#include &lt;asm/m5441xsim.h&gt; #endif /****************************************************************************/ diff --git a/arch/m68k/include/asm/mcftimer.h b/arch/m68k/include/asm/mcftimer.h index 351c272..da2fa43 100644 --- a/arch/m68k/include/asm/mcftimer.h +++ b/arch/m68k/include/asm/mcftimer.h &lt; at &gt;&lt; at &gt; -19,7 +19,7 &lt; at &gt;&lt; at &gt; #defineMCFTIMER_TRR0x04/* Timer Reference (r/w) */ #defineMCFTIMER_TCR0x08/* Timer Capture reg (r/w) */ #defineMCFTIMER_TCN0x0C/* Timer Counter reg (r/w) */ -#if defined(CONFIG_M532x) +#if defined(CONFIG_M532x) || defined(CONFIG_M5441x) #defineMCFTIMER_TER0x03/* Timer Event reg (r/w) */ #else #defineMCFTIMER_TER0x11/* Timer Event reg (r/w) */ diff --git a/arch/m68k/platform/coldfire/Makefile b/arch/m68k/platform/coldfire/Makefile index 76d389d..51e85e5 100644 --- a/arch/m68k/platform/coldfire/Makefile +++ b/arch/m68k/platform/coldfire/Makefile &lt; at &gt;&lt; at &gt; -27,6 +27,7 &lt; at &gt;&lt; at &gt; obj-$(CONFIG_M5307)+= m5307.o timers.o intc.o reset.o obj-$(CONFIG_M532x)+= m532x.o timers.o intc-simr.o reset.o obj-$(CONFIG_M5407)+= m5407.o timers.o intc.o reset.o obj-$(CONFIG_M54xx)+= m54xx.o sltimers.o intc-2.o +obj-$(CONFIG_M5441x)+= m5441x.o timers.o intc-simr.o reset.o obj-$(CONFIG_NETtel)+= nettel.o obj-$(CONFIG_CLEOPATRA)+= nettel.o diff --git a/arch/m68k/platform/coldfire/device.c b/arch/m68k/platform/coldfire/device.c index 3aa77dd..11ecd23 100644 --- a/arch/m68k/platform/coldfire/device.c +++ b/arch/m68k/platform/coldfire/device.c &lt; at &gt;&lt; at &gt; -20,7 +20,7 &lt; at &gt;&lt; at &gt; #include &lt;asm/mcfqspi.h&gt; /* - *All current ColdFire parts contain from 2, 3 or 4 UARTS. + *All current ColdFire parts contain from 2, 3, 4 or 10 UARTS. */ static struct mcf_platform_uart mcf_uart_platform_data[] = { { &lt; at &gt;&lt; at &gt; -43,6 +43,42 &lt; at &gt;&lt; at &gt; static struct mcf_platform_uart mcf_uart_platform_data[] = { .irq= MCF_IRQ_UART3, }, #endif +#ifdef MCFUART_BASE4 +{ +.mapbase= MCFUART_BASE4, +.irq= MCF_IRQ_UART4, +}, +#endif +#ifdef MCFUART_BASE5 +{ +.mapbase= MCFUART_BASE5, +.irq= MCF_IRQ_UART5, +}, +#endif +#ifdef MCFUART_BASE6 +{ +.mapbase= MCFUART_BASE6, +.irq= MCF_IRQ_UART6, +}, +#endif +#ifdef MCFUART_BASE7 +{ +.mapbase= MCFUART_BASE7, +.irq= MCF_IRQ_UART7, +}, +#endif +#ifdef MCFUART_BASE8 +{ +.mapbase= MCFUART_BASE8, +.irq= MCF_IRQ_UART8, +}, +#endif +#ifdef MCFUART_BASE9 +{ +.mapbase= MCFUART_BASE9, +.irq= MCF_IRQ_UART9, +}, +#endif { }, }; diff --git a/arch/m68k/platform/coldfire/intc-simr.c b/arch/m68k/platform/coldfire/intc-simr.c index 650d52e..81571fb 100644 --- a/arch/m68k/platform/coldfire/intc-simr.c +++ b/arch/m68k/platform/coldfire/intc-simr.c &lt; at &gt;&lt; at &gt; -59,16 +59,18 &lt; at &gt;&lt; at &gt; static unsigned int inline irq2ebit(unsigned int irq) #endif /* - *There maybe one or two interrupt control units, each has 64 - *interrupts. If there is no second unit then MCFINTC1_* defines - *will be 0 (and code for them optimized away). + *There maybe one, two or three interrupt control units, each has 64 + *interrupts. If there is no second or third unit then MCFINTC1_* or + *MCFINTC2_* defines will be 0 (and code for them optimized away). */ static void intc_irq_mask(struct irq_data *d) { unsigned int irq = d-&gt;irq - MCFINT_VECBASE; -if (MCFINTC1_SIMR &amp;&amp; (irq &gt; 64)) +if (MCFINTC2_SIMR &amp;&amp; (irq &gt; 128)) +__raw_writeb(irq - 128, MCFINTC2_SIMR); +else if (MCFINTC1_SIMR &amp;&amp; (irq &gt; 64)) __raw_writeb(irq - 64, MCFINTC1_SIMR); else __raw_writeb(irq, MCFINTC0_SIMR); &lt; at &gt;&lt; at &gt; -78,7 +80,9 &lt; at &gt;&lt; at &gt; static void intc_irq_unmask(struct irq_data *d) { unsigned int irq = d-&gt;irq - MCFINT_VECBASE; -if (MCFINTC1_CIMR &amp;&amp; (irq &gt; 64)) +if (MCFINTC2_SIMR &amp;&amp; (irq &gt; 128)) +__raw_writeb(irq - 128, MCFINTC2_SIMR); +else if (MCFINTC1_CIMR &amp;&amp; (irq &gt; 64)) __raw_writeb(irq - 64, MCFINTC1_CIMR); else __raw_writeb(irq, MCFINTC0_CIMR); &lt; at &gt;&lt; at &gt; -99,9 +103,11 &lt; at &gt;&lt; at &gt; static unsigned int intc_irq_startup(struct irq_data *d) unsigned int ebit = irq2ebit(irq); u8 v; +#if defined(MCFEPORT_EPDDR) /* Set EPORT line as input */ v = __raw_readb(MCFEPORT_EPDDR); __raw_writeb(v &amp; ~(0x1 &lt;&lt; ebit), MCFEPORT_EPDDR); +#endif /* Set EPORT line as interrupt source */ v = __raw_readb(MCFEPORT_EPIER); &lt; at &gt;&lt; at &gt; -109,12 +115,13 &lt; at &gt;&lt; at &gt; static unsigned int intc_irq_startup(struct irq_data *d) } irq -= MCFINT_VECBASE; -if (MCFINTC1_ICR0 &amp;&amp; (irq &gt; 64)) +if (MCFINTC2_ICR0 &amp;&amp; (irq &gt; 128)) +__raw_writeb(5, MCFINTC2_ICR0 + irq - 128); +else if (MCFINTC1_ICR0 &amp;&amp; (irq &gt; 64)) __raw_writeb(5, MCFINTC1_ICR0 + irq - 64); else __raw_writeb(5, MCFINTC0_ICR0 + irq); - intc_irq_unmask(d); return 0; } &lt; at &gt;&lt; at &gt; -176,7 +183,8 &lt; at &gt;&lt; at &gt; void __init init_IRQ(void) if (MCFINTC1_SIMR) __raw_writeb(0xff, MCFINTC1_SIMR); -eirq = MCFINT_VECBASE + 64 + (MCFINTC1_ICR0 ? 64 : 0); +eirq = MCFINT_VECBASE + 64 + (MCFINTC1_ICR0 ? 64 : 0) + +(MCFINTC2_ICR0 ? 64 : 0); for (irq = MCFINT_VECBASE; (irq &lt; eirq); irq++) { if ((irq &gt;= EINT1) &amp;&amp; (irq &lt;= EINT7)) irq_set_chip(irq, &amp;intc_irq_chip_edge_port); diff --git a/arch/m68k/platform/coldfire/m5441x.c b/arch/m68k/platform/coldfire/m5441x.c new file mode 100644 index 0000000..edffaff --- /dev/null +++ b/arch/m68k/platform/coldfire/m5441x.c &lt; at &gt;&lt; at &gt; -0,0 +1,51 &lt; at &gt;&lt; at &gt; +/* + *m5441x.c -- support for Coldfire m5441x processors + * + *(C) Copyright Steven King &lt;sfking&lt; at &gt;fdwdc.com&gt; + */ + +#include &lt;linux/kernel.h&gt; +#include &lt;linux/param.h&gt; +#include &lt;linux/init.h&gt; +#include &lt;linux/io.h&gt; +#include &lt;asm/machdep.h&gt; +#include &lt;asm/coldfire.h&gt; +#include &lt;asm/mcfsim.h&gt; +#include &lt;asm/mcfuart.h&gt; +#include &lt;asm/mcfdma.h&gt; +#include &lt;asm/mcfgpio.h&gt; + +struct mcf_gpio_chip mcf_gpio_chips[] = { +MCFGPF(A, 0, 8), +MCFGPF(B, 8, 8), +MCFGPF(C, 16, 8), +MCFGPF(D, 24, 8), +MCFGPF(E, 32, 8), +MCFGPF(F, 40, 8), +MCFGPF(G, 48, 8), +MCFGPF(H, 56, 8), +MCFGPF(I, 64, 8), +MCFGPF(J, 72, 8), +MCFGPF(K, 80, 8), +}; + +unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips); + +static void __init m5441x_uarts_init(void) +{ +__raw_writeb(0x0f, MCFGPIO_PAR_UART0); +__raw_writeb(0x00, MCFGPIO_PAR_UART1); +__raw_writeb(0x00, MCFGPIO_PAR_UART2); +} + +static void __init m5441x_fec_init(void) +{ +__raw_writeb(0x03, MCFGPIO_PAR_FEC); +} + +void __init config_BSP(char *commandp, int size) +{ +mach_sched_init = hw_timer_init; +m5441x_uarts_init(); +m5441x_fec_init(); +} diff --git a/arch/m68k/platform/coldfire/timers.c b/arch/m68k/platform/coldfire/timers.c index ed96ce5..0a273e7 100644 --- a/arch/m68k/platform/coldfire/timers.c +++ b/arch/m68k/platform/coldfire/timers.c &lt; at &gt;&lt; at &gt; -36,7 +36,7 &lt; at &gt;&lt; at &gt; */ void coldfire_profile_init(void); -#if defined(CONFIG_M532x) +#if defined(CONFIG_M532x) || defined(CONFIG_M5441x) #define__raw_readtrr__raw_readl #define__raw_writetrr__raw_writel #else _______________________________________________ uClinux-dev mailing list uClinux-dev&lt; at &gt;uclinux.org http://mailman.uclinux.org/mailman/listinfo/uclinux-dev This message was resent by uclinux-dev&lt; at &gt;uclinux.org To unsubscribe see: http://mailman.uclinux.org/mailman/options/uclinux-dev </pre> Steven King 2012-05-23T02:03:59 http://comments.gmane.org/gmane.linux.uclinux.devel/20452 <pre>If we're not connecting external GPIO extenders via i2c or spi or whatever, we probably don't need GPIOLIB. If we provide an alternate implementation of the GPIOLIB functions to use when only on-chip GPIO is needed, we can change ARCH_REQUIRE_GPIOLIB to ARCH_WANTS_OPTIONAL_GPIOLIB so that GPIOLIB becomes optional. The downside is that in the GPIOLIB=n case, we lose all error checking done by gpiolib, ie multiply allocating the gpio, free'ing gpio etc., so that the only checking that can be done is if we reference a gpio on an external part. Targets that need the extra error checking can still select GPIOLIB=y. For the case where GPIOLIB=y, we can simplify the table of gpio chips to use a single chip, eliminating the tables of chips in the 5xxx.c files. The original motivation for the definition of multiple chips was to match the way many of the Coldfire variants defined their gpio as a spare array in memory. However, all this really gains us is some error checking when we request a gpio, gpiolib can check that it doesn't fall in one of the holes. If thats important, I think we can still come up with a better way of accomplishing that. Also in this patch is some general cleanup and reorganizing of the gpio header files (I'm sure I must have had a reason why I sometimes used a prefix of mcf_gpio and other times mcfgpio but for the life of me I can't think of it now). Signed-off-by: Steven King &lt;sfking&lt; at &gt;fdwdc.com&gt; --- arch/m68k/Kconfig.cpu | 2 +- arch/m68k/include/asm/gpio.h | 169 +---------------- arch/m68k/include/asm/mcfgpio.h | 329 +++++++++++++++++++++++++++------- arch/m68k/include/asm/pinmux.h | 30 ---- arch/m68k/platform/coldfire/Makefile | 2 +- arch/m68k/platform/coldfire/gpio.c | 172 +++++++++++------- arch/m68k/platform/coldfire/m5206.c | 9 - arch/m68k/platform/coldfire/m520x.c | 16 -- arch/m68k/platform/coldfire/m523x.c | 22 --- arch/m68k/platform/coldfire/m5249.c | 10 -- arch/m68k/platform/coldfire/m5272.c | 11 -- arch/m68k/platform/coldfire/m527x.c | 43 ----- arch/m68k/platform/coldfire/m528x.c | 33 +--- arch/m68k/platform/coldfire/m5307.c | 9 - arch/m68k/platform/coldfire/m532x.c | 25 --- arch/m68k/platform/coldfire/m5407.c | 9 - arch/m68k/platform/coldfire/m54xx.c | 7 - arch/m68k/platform/coldfire/pinmux.c | 28 --- 18 files changed, 375 insertions(+), 551 deletions(-) diff --git a/arch/m68k/Kconfig.cpu b/arch/m68k/Kconfig.cpu index 8a9c767..f468413 100644 --- a/arch/m68k/Kconfig.cpu +++ b/arch/m68k/Kconfig.cpu &lt; at &gt;&lt; at &gt; -23,7 +23,7 &lt; at &gt;&lt; at &gt; config M68KCLASSIC config COLDFIRE bool "Coldfire CPU family support" select GENERIC_GPIO -select ARCH_REQUIRE_GPIOLIB +select ARCH_WANT_OPTIONAL_GPIOLIB select CPU_HAS_NO_BITFIELDS select CPU_HAS_NO_MULDIV64 select GENERIC_CSUM diff --git a/arch/m68k/include/asm/gpio.h b/arch/m68k/include/asm/gpio.h index 00d0071..5308622 100644 --- a/arch/m68k/include/asm/gpio.h +++ b/arch/m68k/include/asm/gpio.h &lt; at &gt;&lt; at &gt; -17,170 +17,9 &lt; at &gt;&lt; at &gt; #define coldfire_gpio_h #include &lt;linux/io.h&gt; -#include &lt;asm-generic/gpio.h&gt; #include &lt;asm/coldfire.h&gt; #include &lt;asm/mcfsim.h&gt; - -/* - * The Freescale Coldfire family is quite varied in how they implement GPIO. - * Some parts have 8 bit ports, some have 16bit and some have 32bit; some have - * only one port, others have multiple ports; some have a single data latch - * for both input and output, others have a separate pin data register to read - * input; some require a read-modify-write access to change an output, others - * have set and clear registers for some of the outputs; Some have all the - * GPIOs in a single control area, others have some GPIOs implemented in - * different modules. - * - * This implementation attempts accommodate the differences while presenting - * a generic interface that will optimize to as few instructions as possible. - */ -#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \ - defined(CONFIG_M520x) || defined(CONFIG_M523x) || \ - defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ - defined(CONFIG_M532x) || defined(CONFIG_M54xx) - -/* These parts have GPIO organized by 8 bit ports */ - -#define MCFGPIO_PORTTYPEu8 -#define MCFGPIO_PORTSIZE8 -#define mcfgpio_read(port)__raw_readb(port) -#define mcfgpio_write(data, port)__raw_writeb(data, port) - -#elif defined(CONFIG_M5307) || defined(CONFIG_M5407) || defined(CONFIG_M5272) - -/* These parts have GPIO organized by 16 bit ports */ - -#define MCFGPIO_PORTTYPEu16 -#define MCFGPIO_PORTSIZE16 -#define mcfgpio_read(port)__raw_readw(port) -#define mcfgpio_write(data, port)__raw_writew(data, port) - -#elif defined(CONFIG_M5249) - -/* These parts have GPIO organized by 32 bit ports */ - -#define MCFGPIO_PORTTYPEu32 -#define MCFGPIO_PORTSIZE32 -#define mcfgpio_read(port)__raw_readl(port) -#define mcfgpio_write(data, port)__raw_writel(data, port) - -#endif - -#define mcfgpio_bit(gpio)(1 &lt;&lt; ((gpio) % MCFGPIO_PORTSIZE)) -#define mcfgpio_port(gpio)((gpio) / MCFGPIO_PORTSIZE) - -#if defined(CONFIG_M520x) || defined(CONFIG_M523x) || \ - defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x) -/* - * These parts have an 'Edge' Port module (external interrupt/GPIO) which uses - * read-modify-write to change an output and a GPIO module which has separate - * set/clr registers to directly change outputs with a single write access. - */ -#if defined(CONFIG_M528x) -/* - * The 528x also has GPIOs in other modules (GPT, QADC) which use - * read-modify-write as well as those controlled by the EPORT and GPIO modules. - */ -#define MCFGPIO_SCR_START40 -#else -#define MCFGPIO_SCR_START8 -#endif - -#define MCFGPIO_SETR_PORT(gpio)(MCFGPIO_SETR + \ -mcfgpio_port(gpio - MCFGPIO_SCR_START)) - -#define MCFGPIO_CLRR_PORT(gpio)(MCFGPIO_CLRR + \ -mcfgpio_port(gpio - MCFGPIO_SCR_START)) -#else - -#define MCFGPIO_SCR_STARTMCFGPIO_PIN_MAX -/* with MCFGPIO_SCR == MCFGPIO_PIN_MAX, these will be optimized away */ -#define MCFGPIO_SETR_PORT(gpio)0 -#define MCFGPIO_CLRR_PORT(gpio)0 - -#endif -/* - * Coldfire specific helper functions - */ - -/* return the port pin data register for a gpio */ -static inline u32 __mcf_gpio_ppdr(unsigned gpio) -{ -#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \ - defined(CONFIG_M5307) || defined(CONFIG_M5407) -return MCFSIM_PADAT; -#elif defined(CONFIG_M5272) -if (gpio &lt; 16) -return MCFSIM_PADAT; -else if (gpio &lt; 32) -return MCFSIM_PBDAT; -else -return MCFSIM_PCDAT; -#elif defined(CONFIG_M5249) -if (gpio &lt; 32) -return MCFSIM2_GPIOREAD; -else -return MCFSIM2_GPIO1READ; -#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \ - defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x) -if (gpio &lt; 8) -return MCFEPORT_EPPDR; -#if defined(CONFIG_M528x) -else if (gpio &lt; 16) -return MCFGPTA_GPTPORT; -else if (gpio &lt; 24) -return MCFGPTB_GPTPORT; -else if (gpio &lt; 32) -return MCFQADC_PORTQA; -else if (gpio &lt; 40) -return MCFQADC_PORTQB; -#endif -else -return MCFGPIO_PPDR + mcfgpio_port(gpio - MCFGPIO_SCR_START); -#else -return 0; -#endif -} - -/* return the port output data register for a gpio */ -static inline u32 __mcf_gpio_podr(unsigned gpio) -{ -#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \ - defined(CONFIG_M5307) || defined(CONFIG_M5407) -return MCFSIM_PADAT; -#elif defined(CONFIG_M5272) -if (gpio &lt; 16) -return MCFSIM_PADAT; -else if (gpio &lt; 32) -return MCFSIM_PBDAT; -else -return MCFSIM_PCDAT; -#elif defined(CONFIG_M5249) -if (gpio &lt; 32) -return MCFSIM2_GPIOWRITE; -else -return MCFSIM2_GPIO1WRITE; -#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \ - defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x) -if (gpio &lt; 8) -return MCFEPORT_EPDR; -#if defined(CONFIG_M528x) -else if (gpio &lt; 16) -return MCFGPTA_GPTPORT; -else if (gpio &lt; 24) -return MCFGPTB_GPTPORT; -else if (gpio &lt; 32) -return MCFQADC_PORTQA; -else if (gpio &lt; 40) -return MCFQADC_PORTQB; -#endif -else -return MCFGPIO_PODR + mcfgpio_port(gpio - MCFGPIO_SCR_START); -#else -return 0; -#endif -} - +#include &lt;asm/mcfgpio.h&gt; /* * The Generic GPIO functions * &lt; at &gt;&lt; at &gt; -191,7 +30,7 &lt; at &gt;&lt; at &gt; static inline u32 __mcf_gpio_podr(unsigned gpio) static inline int gpio_get_value(unsigned gpio) { if (__builtin_constant_p(gpio) &amp;&amp; gpio &lt; MCFGPIO_PIN_MAX) -return mcfgpio_read(__mcf_gpio_ppdr(gpio)) &amp; mcfgpio_bit(gpio); +return mcfgpio_read(__mcfgpio_ppdr(gpio)) &amp; mcfgpio_bit(gpio); else return __gpio_get_value(gpio); } &lt; at &gt;&lt; at &gt; -204,12 +43,12 &lt; at &gt;&lt; at &gt; static inline void gpio_set_value(unsigned gpio, int value) MCFGPIO_PORTTYPE data; local_irq_save(flags); -data = mcfgpio_read(__mcf_gpio_podr(gpio)); +data = mcfgpio_read(__mcfgpio_podr(gpio)); if (value) data |= mcfgpio_bit(gpio); else data &amp;= ~mcfgpio_bit(gpio); -mcfgpio_write(data, __mcf_gpio_podr(gpio)); +mcfgpio_write(data, __mcfgpio_podr(gpio)); local_irq_restore(flags); } else { if (value) diff --git a/arch/m68k/include/asm/mcfgpio.h b/arch/m68k/include/asm/mcfgpio.h index fe468ea..d982464 100644 --- a/arch/m68k/include/asm/mcfgpio.h +++ b/arch/m68k/include/asm/mcfgpio.h &lt; at &gt;&lt; at &gt; -16,82 +16,275 &lt; at &gt;&lt; at &gt; #ifndef mcfgpio_h #define mcfgpio_h -#include &lt;linux/io.h&gt; +#ifdef CONFIG_GPIOLIB #include &lt;asm-generic/gpio.h&gt; +#else + +int __mcfgpio_get_value(unsigned gpio); +void __mcfgpio_set_value(unsigned gpio, int value); +int __mcfgpio_direction_input(unsigned gpio); +int __mcfgpio_direction_output(unsigned gpio, int value); +int __mcfgpio_request(unsigned gpio); +void __mcfgpio_free(unsigned gpio); + +/* our alternate 'gpiolib' functions */ +static inline int __gpio_get_value(unsigned gpio) +{ +if (gpio &lt; MCFGPIO_PIN_MAX) +return __mcfgpio_get_value(gpio); +else +return -EINVAL; +} + +static inline void __gpio_set_value(unsigned gpio, int value) +{ +if (gpio &lt; MCFGPIO_PIN_MAX) +__mcfgpio_set_value(gpio, value); +} + +static inline int __gpio_cansleep(unsigned gpio) +{ +if (gpio &lt; MCFGPIO_PIN_MAX) +return 0; +else +return -EINVAL; +} + +static inline int __gpio_to_irq(unsigned gpio) +{ +return -EINVAL; +} + +static inline int gpio_direction_input(unsigned gpio) +{ +if (gpio &lt; MCFGPIO_PIN_MAX) +return __mcfgpio_direction_input(gpio); +else +return -EINVAL; +} + +static inline int gpio_direction_output(unsigned gpio, int value) +{ +if (gpio &lt; MCFGPIO_PIN_MAX) +return __mcfgpio_direction_output(gpio, value); +else +return -EINVAL; +} + +static inline int gpio_request(unsigned gpio, const char *label) +{ +if (gpio &lt; MCFGPIO_PIN_MAX) +return __mcfgpio_request(gpio); +else +return -EINVAL; +} + +static inline void gpio_free(unsigned gpio) +{ +if (gpio &lt; MCFGPIO_PIN_MAX) +__mcfgpio_free(gpio); +} + +#endif /* CONFIG_GPIOLIB */ -struct mcf_gpio_chip { -struct gpio_chip gpio_chip; -void __iomem *pddr; -void __iomem *podr; -void __iomem *ppdr; -void __iomem *setr; -void __iomem *clrr; -const u8 *gpio_to_pinmux; -}; - -extern struct mcf_gpio_chip mcf_gpio_chips[]; -extern unsigned int mcf_gpio_chips_size; - -int mcf_gpio_direction_input(struct gpio_chip *, unsigned); -int mcf_gpio_get_value(struct gpio_chip *, unsigned); -int mcf_gpio_direction_output(struct gpio_chip *, unsigned, int); -void mcf_gpio_set_value(struct gpio_chip *, unsigned, int); -void mcf_gpio_set_value_fast(struct gpio_chip *, unsigned, int); -int mcf_gpio_request(struct gpio_chip *, unsigned); -void mcf_gpio_free(struct gpio_chip *, unsigned); /* - *Define macros to ease the pain of setting up the GPIO tables. There - *are two cases we need to deal with here, they cover all currently - *available ColdFire GPIO hardware. There are of course minor differences - *in the layout and number of bits in each ColdFire part, but the macros - *take all that in. + * The Freescale Coldfire family is quite varied in how they implement GPIO. + * Some parts have 8 bit ports, some have 16bit and some have 32bit; some have + * only one port, others have multiple ports; some have a single data latch + * for both input and output, others have a separate pin data register to read + * input; some require a read-modify-write access to change an output, others + * have set and clear registers for some of the outputs; Some have all the + * GPIOs in a single control area, others have some GPIOs implemented in + * different modules. * - *Firstly is the conventional GPIO registers where we toggle individual - *bits in a register, preserving the other bits in the register. For - *lack of a better term I have called this the slow method. + * This implementation attempts accommodate the differences while presenting + * a generic interface that will optimize to as few instructions as possible. + */ +#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \ + defined(CONFIG_M520x) || defined(CONFIG_M523x) || \ + defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ + defined(CONFIG_M532x) || defined(CONFIG_M54xx) + +/* These parts have GPIO organized by 8 bit ports */ + +#define MCFGPIO_PORTTYPEu8 +#define MCFGPIO_PORTSIZE8 +#define mcfgpio_read(port)__raw_readb(port) +#define mcfgpio_write(data, port)__raw_writeb(data, port) + +#elif defined(CONFIG_M5307) || defined(CONFIG_M5407) || defined(CONFIG_M5272) + +/* These parts have GPIO organized by 16 bit ports */ + +#define MCFGPIO_PORTTYPEu16 +#define MCFGPIO_PORTSIZE16 +#define mcfgpio_read(port)__raw_readw(port) +#define mcfgpio_write(data, port)__raw_writew(data, port) + +#elif defined(CONFIG_M5249) + +/* These parts have GPIO organized by 32 bit ports */ + +#define MCFGPIO_PORTTYPEu32 +#define MCFGPIO_PORTSIZE32 +#define mcfgpio_read(port)__raw_readl(port) +#define mcfgpio_write(data, port)__raw_writel(data, port) + +#endif + +#define mcfgpio_bit(gpio)(1 &lt;&lt; ((gpio) % MCFGPIO_PORTSIZE)) +#define mcfgpio_port(gpio)((gpio) / MCFGPIO_PORTSIZE) + +#if defined(CONFIG_M520x) || defined(CONFIG_M523x) || \ + defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x) +/* + * These parts have an 'Edge' Port module (external interrupt/GPIO) which uses + * read-modify-write to change an output and a GPIO module which has separate + * set/clr registers to directly change outputs with a single write access. + */ +#if defined(CONFIG_M528x) +/* + * The 528x also has GPIOs in other modules (GPT, QADC) which use + * read-modify-write as well as those controlled by the EPORT and GPIO modules. */ -#defineMCFGPS(mlabel, mbase, mngpio, mpddr, mpodr, mppdr) \ -{ \ -.gpio_chip= { \ -.label= #mlabel, \ -.request= mcf_gpio_request, \ -.free= mcf_gpio_free, \ -.direction_input= mcf_gpio_direction_input, \ -.direction_output= mcf_gpio_direction_output,\ -.get= mcf_gpio_get_value, \ -.set= mcf_gpio_set_value, \ -.base= mbase, \ -.ngpio= mngpio, \ -}, \ -.pddr= (void __iomem *) mpddr, \ -.podr= (void __iomem *) mpodr, \ -.ppdr= (void __iomem *) mppdr, \ -} +#define MCFGPIO_SCR_START40 +#else +#define MCFGPIO_SCR_START8 +#endif + +#define MCFGPIO_SETR_PORT(gpio)(MCFGPIO_SETR + \ +mcfgpio_port(gpio - MCFGPIO_SCR_START)) + +#define MCFGPIO_CLRR_PORT(gpio)(MCFGPIO_CLRR + \ +mcfgpio_port(gpio - MCFGPIO_SCR_START)) +#else + +#define MCFGPIO_SCR_STARTMCFGPIO_PIN_MAX +/* with MCFGPIO_SCR == MCFGPIO_PIN_MAX, these will be optimized away */ +#define MCFGPIO_SETR_PORT(gpio)0 +#define MCFGPIO_CLRR_PORT(gpio)0 +#endif /* - *Secondly is the faster case, where we have set and clear registers - *that allow us to set or clear a bit with a single write, not having - *to worry about preserving other bits. + * Coldfire specific helper functions */ -#defineMCFGPF(mlabel, mbase, mngpio) \ -{ \ -.gpio_chip= { \ -.label= #mlabel, \ -.request= mcf_gpio_request, \ -.free= mcf_gpio_free, \ -.direction_input= mcf_gpio_direction_input, \ -.direction_output= mcf_gpio_direction_output,\ -.get= mcf_gpio_get_value, \ -.set= mcf_gpio_set_value_fast, \ -.base= mbase, \ -.ngpio= mngpio, \ -}, \ -.pddr= (void __iomem *) MCFGPIO_PDDR_##mlabel, \ -.podr= (void __iomem *) MCFGPIO_PODR_##mlabel, \ -.ppdr= (void __iomem *) MCFGPIO_PPDSDR_##mlabel, \ -.setr= (void __iomem *) MCFGPIO_PPDSDR_##mlabel, \ -.clrr= (void __iomem *) MCFGPIO_PCLRR_##mlabel, \ -} +/* return the port pin data register for a gpio */ +static inline u32 __mcfgpio_ppdr(unsigned gpio) +{ +#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \ + defined(CONFIG_M5307) || defined(CONFIG_M5407) +return MCFSIM_PADAT; +#elif defined(CONFIG_M5272) +if (gpio &lt; 16) +return MCFSIM_PADAT; +else if (gpio &lt; 32) +return MCFSIM_PBDAT; +else +return MCFSIM_PCDAT; +#elif defined(CONFIG_M5249) +if (gpio &lt; 32) +return MCFSIM2_GPIOREAD; +else +return MCFSIM2_GPIO1READ; +#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \ + defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x) +if (gpio &lt; 8) +return MCFEPORT_EPPDR; +#if defined(CONFIG_M528x) +else if (gpio &lt; 16) +return MCFGPTA_GPTPORT; +else if (gpio &lt; 24) +return MCFGPTB_GPTPORT; +else if (gpio &lt; 32) +return MCFQADC_PORTQA; +else if (gpio &lt; 40) +return MCFQADC_PORTQB; +#endif +else +return MCFGPIO_PPDR + mcfgpio_port(gpio - MCFGPIO_SCR_START); +#else +return 0; +#endif +} + +/* return the port output data register for a gpio */ +static inline u32 __mcfgpio_podr(unsigned gpio) +{ +#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \ + defined(CONFIG_M5307) || defined(CONFIG_M5407) +return MCFSIM_PADAT; +#elif defined(CONFIG_M5272) +if (gpio &lt; 16) +return MCFSIM_PADAT; +else if (gpio &lt; 32) +return MCFSIM_PBDAT; +else +return MCFSIM_PCDAT; +#elif defined(CONFIG_M5249) +if (gpio &lt; 32) +return MCFSIM2_GPIOWRITE; +else +return MCFSIM2_GPIO1WRITE; +#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \ + defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x) +if (gpio &lt; 8) +return MCFEPORT_EPDR; +#if defined(CONFIG_M528x) +else if (gpio &lt; 16) +return MCFGPTA_GPTPORT; +else if (gpio &lt; 24) +return MCFGPTB_GPTPORT; +else if (gpio &lt; 32) +return MCFQADC_PORTQA; +else if (gpio &lt; 40) +return MCFQADC_PORTQB; +#endif +else +return MCFGPIO_PODR + mcfgpio_port(gpio - MCFGPIO_SCR_START); +#else +return 0; #endif +} + +/* return the port direction data register for a gpio */ +static inline u32 __mcfgpio_pddr(unsigned gpio) +{ +#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \ + defined(CONFIG_M5307) || defined(CONFIG_M5407) +return MCFSIM_PADDR; +#elif defined(CONFIG_M5272) +if (gpio &lt; 16) +return MCFSIM_PADDR; +else if (gpio &lt; 32) +return MCFSIM_PBDDR; +else +return MCFSIM_PCDDR; +#elif defined(CONFIG_M5249) +if (gpio &lt; 32) +return MCFSIM2_GPIOENABLE; +else +return MCFSIM2_GPIO1ENABLE; +#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \ + defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x) +if (gpio &lt; 8) +return MCFEPORT_EPDDR; +#if defined(CONFIG_M528x) +else if (gpio &lt; 16) +return MCFGPTA_GPTDDR; +else if (gpio &lt; 24) +return MCFGPTB_GPTDDR; +else if (gpio &lt; 32) +return MCFQADC_DDRQA; +else if (gpio &lt; 40) +return MCFQADC_DDRQB; +#endif +else +return MCFGPIO_PDDR + mcfgpio_port(gpio - MCFGPIO_SCR_START); +#else +return 0; +#endif +} + +#endif /* mcfgpio_h */ diff --git a/arch/m68k/include/asm/pinmux.h b/arch/m68k/include/asm/pinmux.h deleted file mode 100644 index 119ee68..0000000 --- a/arch/m68k/include/asm/pinmux.h +++ /dev/null &lt; at &gt;&lt; at &gt; -1,30 +0,0 &lt; at &gt;&lt; at &gt; -/* - * Coldfire generic GPIO pinmux support. - * - * (C) Copyright 2009, Steven King &lt;sfking&lt; at &gt;fdwdc.com&gt; - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef pinmux_h -#define pinmux_h - -#define MCFPINMUX_NONE-1 - -extern int mcf_pinmux_request(unsigned, unsigned); -extern void mcf_pinmux_release(unsigned, unsigned); - -static inline int mcf_pinmux_is_valid(unsigned pinmux) -{ -return pinmux != MCFPINMUX_NONE; -} - -#endif - diff --git a/arch/m68k/platform/coldfire/Makefile b/arch/m68k/platform/coldfire/Makefile index 76d389d..69bc0ae 100644 --- a/arch/m68k/platform/coldfire/Makefile +++ b/arch/m68k/platform/coldfire/Makefile &lt; at &gt;&lt; at &gt; -32,5 +32,5 &lt; at &gt;&lt; at &gt; obj-$(CONFIG_NETtel)+= nettel.o obj-$(CONFIG_CLEOPATRA)+= nettel.o obj-$(CONFIG_FIREBEE)+= firebee.o -obj-y+= pinmux.o gpio.o +obj-y+= gpio.o extra-y := head.o diff --git a/arch/m68k/platform/coldfire/gpio.c b/arch/m68k/platform/coldfire/gpio.c index 4c8c424..9cd2b5c 100644 --- a/arch/m68k/platform/coldfire/gpio.c +++ b/arch/m68k/platform/coldfire/gpio.c &lt; at &gt;&lt; at &gt; -14,119 +14,161 &lt; at &gt;&lt; at &gt; */ #include &lt;linux/kernel.h&gt; +#include &lt;linux/module.h&gt; #include &lt;linux/init.h&gt; #include &lt;linux/device.h&gt; -#include &lt;asm/gpio.h&gt; -#include &lt;asm/pinmux.h&gt; +#include &lt;linux/io.h&gt; +#include &lt;asm/coldfire.h&gt; +#include &lt;asm/mcfsim.h&gt; #include &lt;asm/mcfgpio.h&gt; -#define MCF_CHIP(chip) container_of(chip, struct mcf_gpio_chip, gpio_chip) +int __mcfgpio_get_value(unsigned gpio) +{ +return mcfgpio_read(__mcfgpio_ppdr(gpio)) &amp; mcfgpio_bit(gpio); +} +EXPORT_SYMBOL(__mcfgpio_get_value); + +void __mcfgpio_set_value(unsigned gpio, int value) +{ +if (gpio &lt; MCFGPIO_SCR_START) { +unsigned long flags; +MCFGPIO_PORTTYPE data; + +local_irq_save(flags); +data = mcfgpio_read(__mcfgpio_podr(gpio)); +if (value) +data |= mcfgpio_bit(gpio); +else +data &amp;= ~mcfgpio_bit(gpio); +mcfgpio_write(data, __mcfgpio_podr(gpio)); +local_irq_restore(flags); +} else { +if (value) +mcfgpio_write(mcfgpio_bit(gpio), +MCFGPIO_SETR_PORT(gpio)); +else +mcfgpio_write(~mcfgpio_bit(gpio), +MCFGPIO_CLRR_PORT(gpio)); +} +} +EXPORT_SYMBOL(__mcfgpio_set_value); -int mcf_gpio_direction_input(struct gpio_chip *chip, unsigned offset) +int __mcfgpio_direction_input(unsigned gpio) { unsigned long flags; MCFGPIO_PORTTYPE dir; -struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip); local_irq_save(flags); -dir = mcfgpio_read(mcf_chip-&gt;pddr); -dir &amp;= ~mcfgpio_bit(chip-&gt;base + offset); -mcfgpio_write(dir, mcf_chip-&gt;pddr); +dir = mcfgpio_read(__mcfgpio_pddr(gpio)); +dir &amp;= ~mcfgpio_bit(gpio); +mcfgpio_write(dir, __mcfgpio_pddr(gpio)); local_irq_restore(flags); return 0; } +EXPORT_SYMBOL(__mcfgpio_direction_input); -int mcf_gpio_get_value(struct gpio_chip *chip, unsigned offset) -{ -struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip); - -return mcfgpio_read(mcf_chip-&gt;ppdr) &amp; mcfgpio_bit(chip-&gt;base + offset); -} - -int mcf_gpio_direction_output(struct gpio_chip *chip, unsigned offset, -int value) +int __mcfgpio_direction_output(unsigned gpio, int value) { unsigned long flags; MCFGPIO_PORTTYPE data; -struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip); local_irq_save(flags); -/* write the value to the output latch */ -data = mcfgpio_read(mcf_chip-&gt;podr); +data = mcfgpio_read(__mcfgpio_pddr(gpio)); if (value) -data |= mcfgpio_bit(chip-&gt;base + offset); +data |= mcfgpio_bit(gpio); else -data &amp;= ~mcfgpio_bit(chip-&gt;base + offset); -mcfgpio_write(data, mcf_chip-&gt;podr); - -/* now set the direction to output */ -data = mcfgpio_read(mcf_chip-&gt;pddr); -data |= mcfgpio_bit(chip-&gt;base + offset); -mcfgpio_write(data, mcf_chip-&gt;pddr); +data &amp;= mcfgpio_bit(gpio); +mcfgpio_write(data, __mcfgpio_pddr(gpio)); + +/* now set the data to output */ +if (gpio &lt; MCFGPIO_SCR_START) { +data = mcfgpio_read(__mcfgpio_podr(gpio)); +if (value) +data |= mcfgpio_bit(gpio); +else +data &amp;= ~mcfgpio_bit(gpio); +mcfgpio_write(data, __mcfgpio_podr(gpio)); +} else { + if (value) +mcfgpio_write(mcfgpio_bit(gpio), +MCFGPIO_SETR_PORT(gpio)); + else + mcfgpio_write(~mcfgpio_bit(gpio), + MCFGPIO_CLRR_PORT(gpio)); +} local_irq_restore(flags); +return 0; +} +EXPORT_SYMBOL(__mcfgpio_direction_output); +int __mcfgpio_request(unsigned gpio) +{ return 0; } +EXPORT_SYMBOL(__mcfgpio_request); -void mcf_gpio_set_value(struct gpio_chip *chip, unsigned offset, int value) +void __mcfgpio_free(unsigned gpio) { -struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip); +__mcfgpio_direction_input(gpio); +} +EXPORT_SYMBOL(__mcfgpio_free); -unsigned long flags; -MCFGPIO_PORTTYPE data; +#ifdef CONFIG_GPIOLIB -local_irq_save(flags); -data = mcfgpio_read(mcf_chip-&gt;podr); -if (value) -data |= mcfgpio_bit(chip-&gt;base + offset); -else -data &amp;= ~mcfgpio_bit(chip-&gt;base + offset); -mcfgpio_write(data, mcf_chip-&gt;podr); -local_irq_restore(flags); +int mcfgpio_direction_input(struct gpio_chip *chip, unsigned offset) +{ +return __mcfgpio_direction_input(offset); } -void mcf_gpio_set_value_fast(struct gpio_chip *chip, unsigned offset, int value) +int mcfgpio_get_value(struct gpio_chip *chip, unsigned offset) { -struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip); - -if (value) -mcfgpio_write(mcfgpio_bit(chip-&gt;base + offset), mcf_chip-&gt;setr); -else -mcfgpio_write(~mcfgpio_bit(chip-&gt;base + offset), mcf_chip-&gt;clrr); +return __mcfgpio_get_value(offset); } -int mcf_gpio_request(struct gpio_chip *chip, unsigned offset) +int mcfgpio_direction_output(struct gpio_chip *chip, unsigned offset, int value) { -struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip); - -return mcf_chip-&gt;gpio_to_pinmux ? -mcf_pinmux_request(mcf_chip-&gt;gpio_to_pinmux[offset], 0) : 0; +return __mcfgpio_direction_output(offset, value); } -void mcf_gpio_free(struct gpio_chip *chip, unsigned offset) +void mcfgpio_set_value(struct gpio_chip *chip, unsigned offset, int value) { -struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip); +__mcfgpio_set_value(offset, value); +} -mcf_gpio_direction_input(chip, offset); +int mcfgpio_request(struct gpio_chip *chip, unsigned offset) +{ +return __mcfgpio_request(offset); +} -if (mcf_chip-&gt;gpio_to_pinmux) -mcf_pinmux_release(mcf_chip-&gt;gpio_to_pinmux[offset], 0); +void mcfgpio_free(struct gpio_chip *chip, unsigned offset) +{ +__mcfgpio_free(offset); } -struct bus_type mcf_gpio_subsys = { +struct bus_type mcfgpio_subsys = { .name= "gpio", .dev_name= "gpio", }; -static int __init mcf_gpio_sysinit(void) -{ -unsigned int i = 0; +static struct gpio_chip mcfgpio_chip = { +.label= "mcfgpio", +.request= mcfgpio_request, +.free= mcfgpio_free, +.direction_input= mcfgpio_direction_input, +.direction_output= mcfgpio_direction_output, +.get= mcfgpio_get_value, +.set= mcfgpio_set_value, +.base= 0, +.ngpio= MCFGPIO_PIN_MAX, +}; -while (i &lt; mcf_gpio_chips_size) -gpiochip_add((struct gpio_chip *)&amp;mcf_gpio_chips[i++]); -return subsys_system_register(&amp;mcf_gpio_subsys, NULL); +static int __init mcfgpio_sysinit(void) +{ +gpiochip_add(&amp;mcfgpio_chip); +return subsys_system_register(&amp;mcfgpio_subsys, NULL); } -core_initcall(mcf_gpio_sysinit); +core_initcall(mcfgpio_sysinit); +#endif diff --git a/arch/m68k/platform/coldfire/m5206.c b/arch/m68k/platform/coldfire/m5206.c index a8b81df..6bfbeeb 100644 --- a/arch/m68k/platform/coldfire/m5206.c +++ b/arch/m68k/platform/coldfire/m5206.c &lt; at &gt;&lt; at &gt; -16,15 +16,6 &lt; at &gt;&lt; at &gt; #include &lt;asm/machdep.h&gt; #include &lt;asm/coldfire.h&gt; #include &lt;asm/mcfsim.h&gt; -#include &lt;asm/mcfgpio.h&gt; - -/***************************************************************************/ - -struct mcf_gpio_chip mcf_gpio_chips[] = { -MCFGPS(PP, 0, 8, MCFSIM_PADDR, MCFSIM_PADAT, MCFSIM_PADAT), -}; - -unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips); /***************************************************************************/ diff --git a/arch/m68k/platform/coldfire/m520x.c b/arch/m68k/platform/coldfire/m520x.c index 3264b88..09df4b8 100644 --- a/arch/m68k/platform/coldfire/m520x.c +++ b/arch/m68k/platform/coldfire/m520x.c &lt; at &gt;&lt; at &gt; -19,22 +19,6 &lt; at &gt;&lt; at &gt; #include &lt;asm/coldfire.h&gt; #include &lt;asm/mcfsim.h&gt; #include &lt;asm/mcfuart.h&gt; -#include &lt;asm/mcfgpio.h&gt; - -/***************************************************************************/ - -struct mcf_gpio_chip mcf_gpio_chips[] = { -MCFGPS(PIRQ, 0, 8, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR), -MCFGPF(CS, 9, 3), -MCFGPF(FECI2C, 16, 4), -MCFGPF(QSPI, 24, 4), -MCFGPF(TIMER, 32, 4), -MCFGPF(UART, 40, 8), -MCFGPF(FECH, 48, 8), -MCFGPF(FECL, 56, 8), -}; - -unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips); /***************************************************************************/ diff --git a/arch/m68k/platform/coldfire/m523x.c b/arch/m68k/platform/coldfire/m523x.c index 5d57a42..d47dfd8 100644 --- a/arch/m68k/platform/coldfire/m523x.c +++ b/arch/m68k/platform/coldfire/m523x.c &lt; at &gt;&lt; at &gt; -19,28 +19,6 &lt; at &gt;&lt; at &gt; #include &lt;asm/machdep.h&gt; #include &lt;asm/coldfire.h&gt; #include &lt;asm/mcfsim.h&gt; -#include &lt;asm/mcfgpio.h&gt; - -/***************************************************************************/ - -struct mcf_gpio_chip mcf_gpio_chips[] = { -MCFGPS(PIRQ, 1, 7, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR), -MCFGPF(ADDR, 13, 3), -MCFGPF(DATAH, 16, 8), -MCFGPF(DATAL, 24, 8), -MCFGPF(BUSCTL, 32, 8), -MCFGPF(BS, 40, 4), -MCFGPF(CS, 49, 7), -MCFGPF(SDRAM, 56, 6), -MCFGPF(FECI2C, 64, 4), -MCFGPF(UARTH, 72, 2), -MCFGPF(UARTL, 80, 8), -MCFGPF(QSPI, 88, 5), -MCFGPF(TIMER, 96, 8), -MCFGPF(ETPU, 104, 3), -}; - -unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips); /***************************************************************************/ diff --git a/arch/m68k/platform/coldfire/m5249.c b/arch/m68k/platform/coldfire/m5249.c index fdfa1ed..300e729 100644 --- a/arch/m68k/platform/coldfire/m5249.c +++ b/arch/m68k/platform/coldfire/m5249.c &lt; at &gt;&lt; at &gt; -16,16 +16,6 &lt; at &gt;&lt; at &gt; #include &lt;asm/machdep.h&gt; #include &lt;asm/coldfire.h&gt; #include &lt;asm/mcfsim.h&gt; -#include &lt;asm/mcfgpio.h&gt; - -/***************************************************************************/ - -struct mcf_gpio_chip mcf_gpio_chips[] = { -MCFGPS(GPIO0, 0, 32, MCFSIM2_GPIOENABLE, MCFSIM2_GPIOWRITE, MCFSIM2_GPIOREAD), -MCFGPS(GPIO1, 32, 32, MCFSIM2_GPIO1ENABLE, MCFSIM2_GPIO1WRITE, MCFSIM2_GPIO1READ), -}; - -unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips); /***************************************************************************/ diff --git a/arch/m68k/platform/coldfire/m5272.c b/arch/m68k/platform/coldfire/m5272.c index 43e3606..e68bc7a 100644 --- a/arch/m68k/platform/coldfire/m5272.c +++ b/arch/m68k/platform/coldfire/m5272.c &lt; at &gt;&lt; at &gt; -19,7 +19,6 &lt; at &gt;&lt; at &gt; #include &lt;asm/coldfire.h&gt; #include &lt;asm/mcfsim.h&gt; #include &lt;asm/mcfuart.h&gt; -#include &lt;asm/mcfgpio.h&gt; /***************************************************************************/ &lt; at &gt;&lt; at &gt; -31,16 +30,6 &lt; at &gt;&lt; at &gt; unsigned char ledbank = 0xff; /***************************************************************************/ -struct mcf_gpio_chip mcf_gpio_chips[] = { -MCFGPS(PA, 0, 16, MCFSIM_PADDR, MCFSIM_PADAT, MCFSIM_PADAT), -MCFGPS(PB, 16, 16, MCFSIM_PBDDR, MCFSIM_PBDAT, MCFSIM_PBDAT), -MCFGPS(Pc, 32, 16, MCFSIM_PCDDR, MCFSIM_PCDAT, MCFSIM_PCDAT), -}; - -unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips); - -/***************************************************************************/ - static void __init m5272_uarts_init(void) { u32 v; diff --git a/arch/m68k/platform/coldfire/m527x.c b/arch/m68k/platform/coldfire/m527x.c index 9b0b66a..b3cb378 100644 --- a/arch/m68k/platform/coldfire/m527x.c +++ b/arch/m68k/platform/coldfire/m527x.c &lt; at &gt;&lt; at &gt; -20,49 +20,6 &lt; at &gt;&lt; at &gt; #include &lt;asm/coldfire.h&gt; #include &lt;asm/mcfsim.h&gt; #include &lt;asm/mcfuart.h&gt; -#include &lt;asm/mcfgpio.h&gt; - -/***************************************************************************/ - -struct mcf_gpio_chip mcf_gpio_chips[] = { -#if defined(CONFIG_M5271) -MCFGPS(PIRQ, 1, 7, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR), -MCFGPF(ADDR, 13, 3), -MCFGPF(DATAH, 16, 8), -MCFGPF(DATAL, 24, 8), -MCFGPF(BUSCTL, 32, 8), -MCFGPF(BS, 40, 4), -MCFGPF(CS, 49, 7), -MCFGPF(SDRAM, 56, 6), -MCFGPF(FECI2C, 64, 4), -MCFGPF(UARTH, 72, 2), -MCFGPF(UARTL, 80, 8), -MCFGPF(QSPI, 88, 5), -MCFGPF(TIMER, 96, 8), -#elif defined(CONFIG_M5275) -MCFGPS(PIRQ, 1, 7, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR), -MCFGPF(BUSCTL, 8, 8), -MCFGPF(ADDR, 21, 3), -MCFGPF(CS, 25, 7), -MCFGPF(FEC0H, 32, 8), -MCFGPF(FEC0L, 40, 8), -MCFGPF(FECI2C, 48, 6), -MCFGPF(QSPI, 56, 7), -MCFGPF(SDRAM, 64, 8), -MCFGPF(TIMERH, 72, 4), -MCFGPF(TIMERL, 80, 4), -MCFGPF(UARTL, 88, 8), -MCFGPF(FEC1H, 96, 8), -MCFGPF(FEC1L, 104, 8), -MCFGPF(BS, 114, 2), -MCFGPF(IRQ, 121, 7), -MCFGPF(USBH, 128, 1), -MCFGPF(USBL, 136, 8), -MCFGPF(UARTH, 144, 4), -#endif -}; - -unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips); /***************************************************************************/ diff --git a/arch/m68k/platform/coldfire/m528x.c b/arch/m68k/platform/coldfire/m528x.c index 7ed1276b..f1319e5 100644 --- a/arch/m68k/platform/coldfire/m528x.c +++ b/arch/m68k/platform/coldfire/m528x.c &lt; at &gt;&lt; at &gt; -21,37 +21,6 &lt; at &gt;&lt; at &gt; #include &lt;asm/coldfire.h&gt; #include &lt;asm/mcfsim.h&gt; #include &lt;asm/mcfuart.h&gt; -#include &lt;asm/mcfgpio.h&gt; - -/***************************************************************************/ - -struct mcf_gpio_chip mcf_gpio_chips[] = { -MCFGPS(NQ, 1, 7, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR), -MCFGPS(TA, 8, 4, MCFGPTA_GPTDDR, MCFGPTA_GPTPORT, MCFGPTB_GPTPORT), -MCFGPS(TB, 16, 4, MCFGPTB_GPTDDR, MCFGPTB_GPTPORT, MCFGPTB_GPTPORT), -MCFGPS(QA, 24, 4, MCFQADC_DDRQA, MCFQADC_PORTQA, MCFQADC_PORTQA), -MCFGPS(QB, 32, 4, MCFQADC_DDRQB, MCFQADC_PORTQB, MCFQADC_PORTQB), -MCFGPF(A, 40, 8), -MCFGPF(B, 48, 8), -MCFGPF(C, 56, 8), -MCFGPF(D, 64, 8), -MCFGPF(E, 72, 8), -MCFGPF(F, 80, 8), -MCFGPF(G, 88, 8), -MCFGPF(H, 96, 8), -MCFGPF(J, 104, 8), -MCFGPF(DD, 112, 8), -MCFGPF(EH, 120, 8), -MCFGPF(EL, 128, 8), -MCFGPF(AS, 136, 6), -MCFGPF(QS, 144, 7), -MCFGPF(SD, 152, 6), -MCFGPF(TC, 160, 4), -MCFGPF(TD, 168, 4), -MCFGPF(UA, 176, 4), -}; - -unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips); /***************************************************************************/ &lt; at &gt;&lt; at &gt; -74,7 +43,7 &lt; at &gt;&lt; at &gt; static void __init m528x_uarts_init(void) /* make sure PUAPAR is set for UART0 and UART1 */ port = readb(MCF5282_GPIO_PUAPAR); port |= 0x03 | (0x03 &lt;&lt; 2); -writeb(port, MCF5282_GPIO_PUAPAR); +writeb(port, MCFGPIO_PUAPAR); } /***************************************************************************/ diff --git a/arch/m68k/platform/coldfire/m5307.c b/arch/m68k/platform/coldfire/m5307.c index 93b4849..a568d28 100644 --- a/arch/m68k/platform/coldfire/m5307.c +++ b/arch/m68k/platform/coldfire/m5307.c &lt; at &gt;&lt; at &gt; -16,7 +16,6 &lt; at &gt;&lt; at &gt; #include &lt;asm/machdep.h&gt; #include &lt;asm/coldfire.h&gt; #include &lt;asm/mcfsim.h&gt; -#include &lt;asm/mcfgpio.h&gt; #include &lt;asm/mcfwdebug.h&gt; /***************************************************************************/ &lt; at &gt;&lt; at &gt; -29,14 +28,6 &lt; at &gt;&lt; at &gt; unsigned char ledbank = 0xff; /***************************************************************************/ -struct mcf_gpio_chip mcf_gpio_chips[] = { -MCFGPS(PP, 0, 16, MCFSIM_PADDR, MCFSIM_PADAT, MCFSIM_PADAT), -}; - -unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips); - -/***************************************************************************/ - void __init config_BSP(char *commandp, int size) { #if defined(CONFIG_NETtel) || \ diff --git a/arch/m68k/platform/coldfire/m532x.c b/arch/m68k/platform/coldfire/m532x.c index 8e9476d..37082d0 100644 --- a/arch/m68k/platform/coldfire/m532x.c +++ b/arch/m68k/platform/coldfire/m532x.c &lt; at &gt;&lt; at &gt; -26,35 +26,10 &lt; at &gt;&lt; at &gt; #include &lt;asm/mcfsim.h&gt; #include &lt;asm/mcfuart.h&gt; #include &lt;asm/mcfdma.h&gt; -#include &lt;asm/mcfgpio.h&gt; #include &lt;asm/mcfwdebug.h&gt; /***************************************************************************/ -struct mcf_gpio_chip mcf_gpio_chips[] = { -MCFGPS(PIRQ, 0, 8, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR), -MCFGPF(FECH, 8, 8), -MCFGPF(FECL, 16, 8), -MCFGPF(SSI, 24, 5), -MCFGPF(BUSCTL, 32, 4), -MCFGPF(BE, 40, 4), -MCFGPF(CS, 49, 5), -MCFGPF(PWM, 58, 4), -MCFGPF(FECI2C, 64, 4), -MCFGPF(UART, 72, 8), -MCFGPF(QSPI, 80, 6), -MCFGPF(TIMER, 88, 4), -MCFGPF(LCDDATAH, 96, 2), -MCFGPF(LCDDATAM, 104, 8), -MCFGPF(LCDDATAL, 112, 8), -MCFGPF(LCDCTLH, 120, 1), -MCFGPF(LCDCTLL, 128, 8), -}; - -unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips); - -/***************************************************************************/ - #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) static void __init m532x_qspi_init(void) diff --git a/arch/m68k/platform/coldfire/m5407.c b/arch/m68k/platform/coldfire/m5407.c index faa6680..bb6c746 100644 --- a/arch/m68k/platform/coldfire/m5407.c +++ b/arch/m68k/platform/coldfire/m5407.c &lt; at &gt;&lt; at &gt; -16,15 +16,6 &lt; at &gt;&lt; at &gt; #include &lt;asm/machdep.h&gt; #include &lt;asm/coldfire.h&gt; #include &lt;asm/mcfsim.h&gt; -#include &lt;asm/mcfgpio.h&gt; - -/***************************************************************************/ - -struct mcf_gpio_chip mcf_gpio_chips[] = { -MCFGPS(PP, 0, 16, MCFSIM_PADDR, MCFSIM_PADAT, MCFSIM_PADAT), -}; - -unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips); /***************************************************************************/ diff --git a/arch/m68k/platform/coldfire/m54xx.c b/arch/m68k/platform/coldfire/m54xx.c index 20672da..2081c6c 100644 --- a/arch/m68k/platform/coldfire/m54xx.c +++ b/arch/m68k/platform/coldfire/m54xx.c &lt; at &gt;&lt; at &gt; -21,19 +21,12 &lt; at &gt;&lt; at &gt; #include &lt;asm/m54xxsim.h&gt; #include &lt;asm/mcfuart.h&gt; #include &lt;asm/m54xxgpt.h&gt; -#include &lt;asm/mcfgpio.h&gt; #ifdef CONFIG_MMU #include &lt;asm/mmu_context.h&gt; #endif /***************************************************************************/ -struct mcf_gpio_chip mcf_gpio_chips[] = { }; - -unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips); - -/***************************************************************************/ - static void __init m54xx_uarts_init(void) { /* enable io pins */ diff --git a/arch/m68k/platform/coldfire/pinmux.c b/arch/m68k/platform/coldfire/pinmux.c deleted file mode 100644 index 8c62b82..0000000 --- a/arch/m68k/platform/coldfire/pinmux.c +++ /dev/null &lt; at &gt;&lt; at &gt; -1,28 +0,0 &lt; at &gt;&lt; at &gt; -/* - * Coldfire generic GPIO pinmux support. - * - * (C) Copyright 2009, Steven King &lt;sfking&lt; at &gt;fdwdc.com&gt; - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include &lt;linux/kernel.h&gt; - -#include &lt;asm/pinmux.h&gt; - -int mcf_pinmux_request(unsigned pinmux, unsigned func) -{ -return 0; -} - -void mcf_pinmux_release(unsigned pinmux, unsigned func) -{ -} _______________________________________________ uClinux-dev mailing list uClinux-dev&lt; at &gt;uclinux.org http://mailman.uclinux.org/mailman/listinfo/uclinux-dev This message was resent by uclinux-dev&lt; at &gt;uclinux.org To unsubscribe see: http://mailman.uclinux.org/mailman/options/uclinux-dev </pre> Steven King 2012-05-21T20:10:19 http://comments.gmane.org/gmane.linux.uclinux.devel/20433 <pre>D'oh! I really dropped the ball on this, but I figure better late than never ;-). Changes since V2: drivers/i2c/busses/i2c-coldfire.c: * As Ben suggested, making the interrupt handler do most of the message processing and wake the thread when its done vastly improves performance. * preliminary support for PM_RUNTIME; but as there isn't arch support for for PM_RUNTIME it doesn't do anything yet. * fixed a bug when the driver would hang on waiting for bus busy if the bus never went busy. drivers/i2c/busses/Kconfig: * its easier to list the Coldfire MCUs that don't have I2C. arch/m68k/include/asm/mcfi2c.h: * moved the defines for the various Coldfire MCUs to the specific header file for the various Coldfire MCUs. Support for the Freescale Coldfire I2C controller. Signed-off-by: Steven King &lt;sfking&lt; at &gt;fedc.com&gt; --- arch/m68k/include/asm/mcfi2c.h | 15 ++ drivers/i2c/busses/Kconfig | 10 + drivers/i2c/busses/Makefile | 1 + drivers/i2c/busses/i2c-coldfire.c | 497 +++++++++++++++++++++++++++++++++++++ 4 files changed, 523 insertions(+) diff --git a/arch/m68k/include/asm/mcfi2c.h b/arch/m68k/include/asm/mcfi2c.h new file mode 100644 index 0000000..24b0453 --- /dev/null +++ b/arch/m68k/include/asm/mcfi2c.h &lt; at &gt;&lt; at &gt; -0,0 +1,15 &lt; at &gt;&lt; at &gt; +/* + * Definitions for Coldfire I2C interface +*/ +#ifndef mcfi2c_h +#define mcfi2c_h + +/** + * struct mcfi2c_platform_data - platform data for the coldfire i2c driver + * &lt; at &gt;bitrate: bitrate to use for this i2c controller. +*/ +struct mcfi2c_platform_data { +u32bitrate; +}; + +#endif /* mcfi2c_h */ diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index d2c5095..159404e 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig &lt; at &gt;&lt; at &gt; -327,6 +327,16 &lt; at &gt;&lt; at &gt; config I2C_BLACKFIN_TWI_CLK_KHZ help The unit of the TWI clock is kHz. +config I2C_COLDFIRE +tristate "Freescale Coldfire I2C driver" +depends on !M5272 +help + This driver supports the I2C interface availible on most Freescale + Coldfire processors. + + This driver can be built as a module. If so, the module + will be called i2c-coldfire. + config I2C_CPM tristate "Freescale CPM1 or CPM2 (MPC8xx/826x)" depends on (CPM1 || CPM2) &amp;&amp; OF_I2C diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile index 569567b..2c88c4a 100644 --- a/drivers/i2c/busses/Makefile +++ b/drivers/i2c/busses/Makefile &lt; at &gt;&lt; at &gt; -31,6 +31,7 &lt; at &gt;&lt; at &gt; obj-$(CONFIG_I2C_POWERMAC)+= i2c-powermac.o obj-$(CONFIG_I2C_AT91)+= i2c-at91.o obj-$(CONFIG_I2C_AU1550)+= i2c-au1550.o obj-$(CONFIG_I2C_BLACKFIN_TWI)+= i2c-bfin-twi.o +obj-$(CONFIG_I2C_COLDFIRE)+= i2c-coldfire.o obj-$(CONFIG_I2C_CPM)+= i2c-cpm.o obj-$(CONFIG_I2C_DAVINCI)+= i2c-davinci.o obj-$(CONFIG_I2C_DESIGNWARE_PLATFORM)+= i2c-designware-platform.o diff --git a/drivers/i2c/busses/i2c-coldfire.c b/drivers/i2c/busses/i2c-coldfire.c new file mode 100644 index 0000000..97351c0 --- /dev/null +++ b/drivers/i2c/busses/i2c-coldfire.c &lt; at &gt;&lt; at &gt; -0,0 +1,497 &lt; at &gt;&lt; at &gt; +/* Freescale/Motorola Coldfire I2C driver. + * + * Copyright 2010, 2012 Steven King &lt;sfking&lt; at &gt;fdwdc.com&gt; + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include &lt;linux/kernel.h&gt; +#include &lt;linux/module.h&gt; +#include &lt;linux/interrupt.h&gt; +#include &lt;linux/errno.h&gt; +#include &lt;linux/platform_device.h&gt; +#include &lt;linux/io.h&gt; +#include &lt;linux/clk.h&gt; +#include &lt;linux/err.h&gt; +#include &lt;linux/i2c.h&gt; +#include &lt;linux/slab.h&gt; +#include &lt;linux/pm_runtime.h&gt; +#include &lt;asm/mcfi2c.h&gt; + +#defineDRIVER_NAME "mcfi2c" + +#defineMCFI2C_ADR0x00 +#defineMCFI2C_FDR0x04 +#defineMCFI2C_CR0x08 +#defineMCFI2C_CR_IEN0x80 +#defineMCFI2C_CR_IIEN0x40 +#defineMCFI2C_CR_MSTA0x20 +#defineMCFI2C_CR_MTX0x10 +#defineMCFI2C_CR_TXAK0x08 +#defineMCFI2C_CR_RSTA0x04 +#defineMCFI2C_DR0x10 +#defineMCFI2C_SR0x0C +#defineMCFI2C_SR_ICF0x80 +#defineMCFI2C_SR_IAAS0x40 +#defineMCFI2C_SR_IBB0x20 +#defineMCFI2C_SR_IAL0x10 +#defineMCFI2C_SR_SRW0x04 +#defineMCFI2C_SR_IIF0x02 +#defineMCFI2C_SR_RXAK0x01 + +#defineDEFAULT_I2C_BUS_SPEED100000 + +struct mcfi2c { +struct i2c_adapteradapter; +void __iomem*iobase; +intirq; +struct clk*clk; +struct completioncompletion; + +u8*buf; +u16flags; +u16len; +intmore; +intstatus; +}; + +static u8 mcfi2c_rd_cr(struct mcfi2c *mcfi2c) +{ +return readb(mcfi2c-&gt;iobase + MCFI2C_CR); +} + +static void mcfi2c_wr_cr(struct mcfi2c *mcfi2c, u8 val) +{ +writeb(val, mcfi2c-&gt;iobase + MCFI2C_CR); +} + +static u8 mcfi2c_rd_sr(struct mcfi2c *mcfi2c) +{ +return readb(mcfi2c-&gt;iobase + MCFI2C_SR); +} + +static void mcfi2c_wr_sr(struct mcfi2c *mcfi2c, u8 val) +{ +writeb(val, mcfi2c-&gt;iobase + MCFI2C_SR); +} + +static u8 mcfi2c_rd_dr(struct mcfi2c *mcfi2c) +{ +return readb(mcfi2c-&gt;iobase + MCFI2C_DR); +} + +static void mcfi2c_wr_dr(struct mcfi2c *mcfi2c, u8 val) +{ +writeb(val, mcfi2c-&gt;iobase + MCFI2C_DR); +} + +static void mcfi2c_start(struct mcfi2c *mcfi2c) +{ +mcfi2c_wr_cr(mcfi2c, MCFI2C_CR_IEN | MCFI2C_CR_IIEN | MCFI2C_CR_MSTA | + MCFI2C_CR_MTX); +} + +static void mcfi2c_repeat_start(struct mcfi2c *mcfi2c) +{ +mcfi2c_wr_cr(mcfi2c, MCFI2C_CR_IEN | MCFI2C_CR_IIEN | MCFI2C_CR_MSTA | + MCFI2C_CR_MTX | MCFI2C_CR_RSTA); +} + +static void mcfi2c_stop(struct mcfi2c *mcfi2c) +{ +mcfi2c_wr_cr(mcfi2c, MCFI2C_CR_IEN); +} + +static void mcfi2c_tx_ack(struct mcfi2c *mcfi2c) +{ +mcfi2c_wr_cr(mcfi2c, MCFI2C_CR_IEN | MCFI2C_CR_IIEN | MCFI2C_CR_MSTA); +} + +static void mcfi2c_tx_nak(struct mcfi2c *mcfi2c) +{ +mcfi2c_wr_cr(mcfi2c, MCFI2C_CR_IEN | MCFI2C_CR_IIEN | MCFI2C_CR_MSTA | + MCFI2C_CR_TXAK); +} + +static irqreturn_t mcfi2c_irq_handler(int this_irq, void *dev_id) +{ +struct mcfi2c *mcfi2c = dev_id; +u8 sr; + +if (pm_runtime_suspended(&amp;mcfi2c-&gt;adapter.dev)) +return IRQ_NONE; + +/* clear interrupt */ +mcfi2c_wr_sr(mcfi2c, 0); + +sr = mcfi2c_rd_sr(mcfi2c); +if (sr &amp; MCFI2C_SR_IAL) { +mcfi2c_wr_sr(mcfi2c, ~MCFI2C_SR_IAL); +mcfi2c-&gt;status = -EIO; +} else if (mcfi2c_rd_cr(mcfi2c) &amp; MCFI2C_CR_MTX) { +if (sr &amp; MCFI2C_SR_RXAK) { +mcfi2c_stop(mcfi2c); +mcfi2c-&gt;status = -EIO; +} else if (mcfi2c-&gt;flags &amp; I2C_M_RD) { +if (mcfi2c-&gt;len &gt; 1) +mcfi2c_tx_ack(mcfi2c); +else +mcfi2c_tx_nak(mcfi2c); +/* dummy read */ +mcfi2c_rd_dr(mcfi2c); +goto not_complete; + +} else if (mcfi2c-&gt;len--) { +mcfi2c_wr_dr(mcfi2c, *(mcfi2c-&gt;buf++)); +goto not_complete; +} else { +if (mcfi2c-&gt;more) +mcfi2c_repeat_start(mcfi2c); +else +mcfi2c_stop(mcfi2c); +} +} else if (--mcfi2c-&gt;len) { +if (!(mcfi2c-&gt;len &gt; 1)) +mcfi2c_tx_nak(mcfi2c); +*(mcfi2c-&gt;buf++) = mcfi2c_rd_dr(mcfi2c); +goto not_complete; +} else { +if (mcfi2c-&gt;more) +mcfi2c_repeat_start(mcfi2c); +else +mcfi2c_stop(mcfi2c); +*(mcfi2c-&gt;buf++) = mcfi2c_rd_dr(mcfi2c); +} +complete(&amp;mcfi2c-&gt;completion); +not_complete: +return IRQ_HANDLED; +} + +static void mcfi2c_reset(struct mcfi2c *mcfi2c) +{ +mcfi2c_wr_cr(mcfi2c, 0); +mcfi2c_wr_cr(mcfi2c, MCFI2C_CR_IEN | MCFI2C_CR_MSTA); +mcfi2c_rd_dr(mcfi2c); +mcfi2c_wr_sr(mcfi2c, 0); +mcfi2c_wr_cr(mcfi2c, 0); +mcfi2c_wr_cr(mcfi2c, MCFI2C_CR_IEN); +} + +static int mcfi2c_wait_for_bus_idle(struct mcfi2c *mcfi2c) +{ +unsigned long timeout = jiffies + HZ / 2; +while (mcfi2c_rd_sr(mcfi2c) &amp; MCFI2C_SR_IBB) { +if (time_after(jiffies, timeout)) +return -EIO; /* bus is busy, try again */ +cond_resched(); +} +return 0; +} + +static int mcfi2c_wait_for_bus_busy(struct mcfi2c *mcfi2c) +{ +unsigned long timeout = jiffies + HZ / 10; +u8 sr; +while (!((sr = mcfi2c_rd_sr(mcfi2c)) &amp; MCFI2C_SR_IBB)) { +if (sr &amp; MCFI2C_SR_IAL) +return -EIO; /* lost arbitration, try again */ +if (time_after(jiffies, timeout)) { +/* if we dont get bus busy and dont get an arbitration + * loss, then the bus is probably glitched, see if we + * can recover. +*/ +dev_dbg(&amp;mcfi2c-&gt;adapter.dev, +"unable to send START, trying to reset the bus\n"); +mcfi2c_reset(mcfi2c); +return -EIO; +} +cond_resched(); +} +return 0; +} + +static int mcfi2c_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, +int num) +{ +struct mcfi2c *mcfi2c = i2c_get_adapdata(adapter); +int cnt = 0; + +pm_runtime_get_sync(&amp;adapter-&gt;dev); + +while (num--) { +int retries = adapter-&gt;retries; +if (msgs-&gt;flags &amp; ~I2C_M_RD) { +mcfi2c-&gt;status = -EINVAL; +goto done; +} +do { +mcfi2c-&gt;flags = msgs-&gt;flags; +mcfi2c-&gt;buf = msgs-&gt;buf; +mcfi2c-&gt;len = msgs-&gt;len; +mcfi2c-&gt;more = num; +mcfi2c-&gt;status = 0; + +if (!(mcfi2c_rd_cr(mcfi2c) &amp; MCFI2C_CR_MSTA)) { +mcfi2c-&gt;status = + mcfi2c_wait_for_bus_idle(mcfi2c); +if (mcfi2c-&gt;status) +continue; + +INIT_COMPLETION(mcfi2c-&gt;completion); +mcfi2c_start(mcfi2c); + +mcfi2c-&gt;status = + mcfi2c_wait_for_bus_busy(mcfi2c); +if (mcfi2c-&gt;status) +continue; +} + +mcfi2c_wr_dr(mcfi2c, (msgs-&gt;addr &lt;&lt; 1) | +(msgs-&gt;flags &amp; I2C_M_RD)); +if (!wait_for_completion_timeout(&amp;mcfi2c-&gt;completion, +adapter-&gt;timeout * msgs-&gt;len)) { +mcfi2c-&gt;status = -ETIMEDOUT; +mcfi2c_stop(mcfi2c); +} + +} while (mcfi2c-&gt;status &amp;&amp; retries--); +if (mcfi2c-&gt;status) +goto done; +++cnt; +++msgs; +} +done: +pm_runtime_put(&amp;adapter-&gt;dev); + +return mcfi2c-&gt;status ?: cnt; +} + +static u32 mcfi2c_func(struct i2c_adapter *adapter) +{ +return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; +} + +static const struct i2c_algorithm mcfi2c_algo = { +.master_xfer= mcfi2c_xfer, +.functionality= mcfi2c_func, +}; + +static const u16 mcfi2c_fdr[] = { + 28, 30, 34, 40, 44, 48, 56, 68, + 80, 88, 104, 128, 144, 160, 192, 240, + 288, 320, 384, 480, 576, 640, 768, 960, +1152, 1280, 1536, 1920, 2304, 2560, 3072, 3840, + 20, 22, 24, 26, 28, 32, 36, 40, + 48, 56, 64, 72, 80, 96, 112, 128, + 160, 192, 224, 256, 320, 384, 448, 512, + 640, 768, 896, 1024, 1280, 1536, 1792, 2048 +}; + +static u8 __devinit mcfi2c_calc_fdr(struct mcfi2c *mcfi2c, + struct mcfi2c_platform_data *pdata) +{ +u32 bitrate = (pdata &amp;&amp; pdata-&gt;bitrate) ? +pdata-&gt;bitrate : DEFAULT_I2C_BUS_SPEED; +int div = clk_get_rate(mcfi2c-&gt;clk)/bitrate; +int r = 0, i = 0; + +do +if (abs(mcfi2c_fdr[i] - div) &lt; abs(mcfi2c_fdr[r] - div)) +r = i; +while (++i &lt; ARRAY_SIZE(mcfi2c_fdr)); + +return r; +} + +static int __devinit mcfi2c_probe(struct platform_device *pdev) +{ +struct mcfi2c *mcfi2c; +struct resource *res; +int status; + +mcfi2c = kzalloc(sizeof(*mcfi2c), GFP_KERNEL); +if (!mcfi2c) { +dev_dbg(&amp;pdev-&gt;dev, "kzalloc failed\n"); + +return -ENOMEM; +} + +res = platform_get_resource(pdev, IORESOURCE_MEM, 0); +if (!res) { +dev_dbg(&amp;pdev-&gt;dev, "platform_get_resource failed\n"); +status = -ENXIO; +goto fail0; +} + +if (!request_mem_region(res-&gt;start, resource_size(res), pdev-&gt;name)) { +dev_dbg(&amp;pdev-&gt;dev, "request_mem_region failed\n"); +status = -EBUSY; +goto fail0; +} + +mcfi2c-&gt;iobase = ioremap(res-&gt;start, resource_size(res)); +if (!mcfi2c-&gt;iobase) { +dev_dbg(&amp;pdev-&gt;dev, "ioremap failed\n"); +status = -ENOMEM; +goto fail1; +} + +mcfi2c-&gt;irq = platform_get_irq(pdev, 0); +if (mcfi2c-&gt;irq &lt; 0) { +dev_dbg(&amp;pdev-&gt;dev, "platform_get_irq failed\n"); +status = -ENXIO; +goto fail2; +} +status = request_irq(mcfi2c-&gt;irq, mcfi2c_irq_handler, 0, pdev-&gt;name, +mcfi2c); +if (status) { +dev_dbg(&amp;pdev-&gt;dev, "request_irq failed\n"); +goto fail2; +} + +mcfi2c-&gt;clk = clk_get(&amp;pdev-&gt;dev, NULL); +if (IS_ERR(mcfi2c-&gt;clk)) { +dev_dbg(&amp;pdev-&gt;dev, "clk_get failed\n"); +status = PTR_ERR(mcfi2c-&gt;clk); +goto fail3; +} +clk_enable(mcfi2c-&gt;clk); + +platform_set_drvdata(pdev, mcfi2c); + +init_completion(&amp;mcfi2c-&gt;completion); + +writeb(mcfi2c_calc_fdr(mcfi2c, pdev-&gt;dev.platform_data), + mcfi2c-&gt;iobase + MCFI2C_FDR); + +writeb(0x00, mcfi2c-&gt;iobase + MCFI2C_ADR); + +mcfi2c_wr_cr(mcfi2c, MCFI2C_CR_IEN); + +pm_runtime_enable(&amp;pdev-&gt;dev); +pm_runtime_get_sync(&amp;pdev-&gt;dev); + +/* if the bus busy (IBB) is set, reset the controller */ +if (mcfi2c_rd_sr(mcfi2c) &amp; MCFI2C_SR_IBB) +mcfi2c_reset(mcfi2c); + +mcfi2c-&gt;adapter.algo= &amp;mcfi2c_algo; +mcfi2c-&gt;adapter.class= I2C_CLASS_HWMON | I2C_CLASS_SPD; +mcfi2c-&gt;adapter.dev.parent= &amp;pdev-&gt;dev; +mcfi2c-&gt;adapter.nr= pdev-&gt;id; +mcfi2c-&gt;adapter.retries= 2; +snprintf(mcfi2c-&gt;adapter.name, sizeof(mcfi2c-&gt;adapter.name), +DRIVER_NAME ".%d", pdev-&gt;id); + +i2c_set_adapdata(&amp;mcfi2c-&gt;adapter, mcfi2c); + +status = i2c_add_numbered_adapter(&amp;mcfi2c-&gt;adapter); +if (status &lt; 0) { +dev_dbg(&amp;pdev-&gt;dev, "i2c_add_numbered_adapter failed\n"); +goto fail4; +} + +pm_runtime_put(&amp;pdev-&gt;dev); + +dev_info(&amp;pdev-&gt;dev, "Coldfire I2C bus driver\n"); + +return 0; + +fail4: +pm_runtime_put(&amp;pdev-&gt;dev); + +clk_disable(mcfi2c-&gt;clk); +clk_put(mcfi2c-&gt;clk); +fail3: +free_irq(mcfi2c-&gt;irq, mcfi2c); +fail2: +iounmap(mcfi2c-&gt;iobase); +fail1: +release_mem_region(res-&gt;start, resource_size(res)); +fail0: +kfree(mcfi2c); + +return status; +} + +static int __devexit mcfi2c_remove(struct platform_device *pdev) +{ +struct mcfi2c *mcfi2c = platform_get_drvdata(pdev); +struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + +/* disable the hardware */ +mcfi2c_wr_cr(mcfi2c, 0); + +platform_set_drvdata(pdev, NULL); +i2c_del_adapter(&amp;mcfi2c-&gt;adapter); +clk_disable(mcfi2c-&gt;clk); +clk_put(mcfi2c-&gt;clk); +free_irq(mcfi2c-&gt;irq, mcfi2c); +iounmap(mcfi2c-&gt;iobase); +release_mem_region(res-&gt;start, resource_size(res)); +kfree(mcfi2c); + +return 0; +} + +#ifdef CONFIG_PM_RUNTIME +static int mcfi2c_runtime_suspend(struct device *dev) +{ +struct mcfi2c *mcfi2c = platform_get_drvdata(to_platform_device(dev)); + +mcfi2c_wr_cr(mcfi2c, 0); +clk_disable(mcfi2c-&gt;clk); + +return 0; +} + +static int mcfi2c_runtime_resume(struct device *dev) +{ +struct mcfi2c *mcfi2c = platform_get_drvdata(to_platform_device(dev)); + +clk_enable(mcfi2c-&gt;clk); +mcfi2c_wr_cr(mcfi2c, MCFI2C_CR_IEN); + +return 0; +} +#endif + +static const struct dev_pm_ops mcfi2c_pm = { +SET_RUNTIME_PM_OPS(mcfi2c_runtime_suspend, mcfi2c_runtime_resume, NULL) +}; + +static struct platform_driver mcfi2c_driver = { +.driver.name= DRIVER_NAME, +.driver.owner= THIS_MODULE, +.driver.pm= &amp;mcfi2c_pm, +.remove= __devexit_p(mcfi2c_remove), +}; + +static int __init mcfi2c_init(void) +{ +return platform_driver_probe(&amp;mcfi2c_driver, mcfi2c_probe); +} +module_init(mcfi2c_init); + +static void __exit mcfi2c_exit(void) +{ +platform_driver_unregister(&amp;mcfi2c_driver); +} +module_exit(mcfi2c_exit); + +MODULE_AUTHOR("Steven King &lt;sfking&lt; at &gt;fdwdc.com&gt;"); +MODULE_DESCRIPTION("I2C-Bus support for Freescale Coldfire processors"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:" DRIVER_NAME); _______________________________________________ uClinux-dev mailing list uClinux-dev&lt; at &gt;uclinux.org http://mailman.uclinux.org/mailman/listinfo/uclinux-dev This message was resent by uclinux-dev&lt; at &gt;uclinux.org To unsubscribe see: http://mailman.uclinux.org/mailman/options/uclinux-dev </pre> Steven King 2012-05-17T02:10:35 http://comments.gmane.org/gmane.linux.uclinux.devel/20413 <pre>From: Greg Ungerer &lt;gerg&lt; at &gt;uclinux.org&gt; Add a default configuration for the newly supported ColdFire CPUs running with MMU enabled. This is based on Freescales own M5475EVB demo board. Signed-off-by: Greg Ungerer &lt;gerg&lt; at &gt;uclinux.org&gt; --- arch/m68k/configs/m5475evb_defconfig | 62 ++++++++++++++++++++++++++++++++++ 1 files changed, 62 insertions(+), 0 deletions(-) create mode 100644 arch/m68k/configs/m5475evb_defconfig diff --git a/arch/m68k/configs/m5475evb_defconfig b/arch/m68k/configs/m5475evb_defconfig new file mode 100644 index 0000000..c5018a6 --- /dev/null +++ b/arch/m68k/configs/m5475evb_defconfig &lt; at &gt;&lt; at &gt; -0,0 +1,62 &lt; at &gt;&lt; at &gt; +CONFIG_EXPERIMENTAL=y +# CONFIG_SWAP is not set +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +CONFIG_SYSCTL_SYSCALL=y +# CONFIG_KALLSYMS is not set +# CONFIG_HOTPLUG is not set +# CONFIG_FUTEX is not set +# CONFIG_EPOLL is not set +# CONFIG_SIGNALFD is not set +# CONFIG_TIMERFD is not set +# CONFIG_EVENTFD is not set +# CONFIG_SHMEM is not set +# CONFIG_AIO is not set +CONFIG_EMBEDDED=y +CONFIG_MODULES=y +# CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_COLDFIRE=y +CONFIG_M547x=y +CONFIG_CLOCK_SET=y +CONFIG_CLOCK_FREQ=266000000 +# CONFIG_4KSTACKS is not set +CONFIG_RAMBASE=0x0 +CONFIG_RAMSIZE=0x2000000 +CONFIG_VECTORBASE=0x0 +CONFIG_MBAR=0xff000000 +CONFIG_KERNELBASE=0x20000 +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_FW_LOADER is not set +CONFIG_MTD=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_RAM=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_UCLINUX=y +CONFIG_BLK_DEV_RAM=y +# CONFIG_INPUT is not set +# CONFIG_VT is not set +# CONFIG_UNIX98_PTYS is not set +CONFIG_SERIAL_MCF=y +CONFIG_SERIAL_MCF_CONSOLE=y +# CONFIG_HW_RANDOM is not set +# CONFIG_HWMON is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_EXT2_FS=y +# CONFIG_FILE_LOCKING is not set +# CONFIG_DNOTIFY is not set +# CONFIG_INOTIFY_USER is not set +# CONFIG_PROC_PAGE_MONITOR is not set +CONFIG_ROMFS_FS=y +CONFIG_ROMFS_BACKED_BY_MTD=y +# CONFIG_SCHED_DEBUG is not set +CONFIG_BOOTPARAM=y +CONFIG_BOOTPARAM_STRING="root=/dev/mtdblock0" </pre> gerg< at >snapgear.com 2012-05-15T06:42:58 http://comments.gmane.org/gmane.linux.uclinux.devel/20410 <pre>From: Greg Ungerer &lt;gerg&lt; at &gt;uclinux.org&gt; Perform a number of cleanups on the uclinux.c map driver. No structural or semantic changes, only minor cleanups. . insert appropriate prefix into printk() calls . remove redundant "if" checks in the module exit code . remove unnecessary includes . make the struct uclinux_ram_map static . cast the virtual address calculations to keep them sparse clean Signed-off-by: Greg Ungerer &lt;gerg&lt; at &gt;uclinux.org&gt; --- drivers/mtd/maps/uclinux.c | 34 +++++++++++++--------------------- 1 files changed, 13 insertions(+), 21 deletions(-) diff --git a/drivers/mtd/maps/uclinux.c b/drivers/mtd/maps/uclinux.c index 6d43c75..d91b5b4 100644 --- a/drivers/mtd/maps/uclinux.c +++ b/drivers/mtd/maps/uclinux.c &lt; at &gt;&lt; at &gt; -12,19 +12,16 &lt; at &gt;&lt; at &gt; #include &lt;linux/types.h&gt; #include &lt;linux/init.h&gt; #include &lt;linux/kernel.h&gt; -#include &lt;linux/fs.h&gt; #include &lt;linux/mm.h&gt; -#include &lt;linux/major.h&gt; #include &lt;linux/mtd/mtd.h&gt; #include &lt;linux/mtd/map.h&gt; #include &lt;linux/mtd/partitions.h&gt; -#include &lt;asm/io.h&gt; /****************************************************************************/ extern char _ebss; -struct map_info uclinux_ram_map = { +static struct map_info uclinux_ram_map = { .name = "RAM", .phys = (unsigned long)&amp;_ebss, .size = 0, &lt; at &gt;&lt; at &gt; -46,11 +43,11 &lt; at &gt;&lt; at &gt; static int uclinux_point(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, void **virt, resource_size_t *phys) { struct map_info *map = mtd-&gt;priv; -*virt = map-&gt;virt + from; +*virt = (void *) (unsigned long) map-&gt;virt + from; if (phys) *phys = map-&gt;phys + from; *retlen = len; -return(0); +return 0; } /****************************************************************************/ &lt; at &gt;&lt; at &gt; -65,22 +62,22 &lt; at &gt;&lt; at &gt; static int __init uclinux_mtd_init(void) mapp-&gt;size = PAGE_ALIGN(ntohl(*((unsigned long *)(mapp-&gt;phys + 8)))); mapp-&gt;bankwidth = 4; -printk("uclinux[mtd]: RAM probe address=0x%x size=0x%x\n", +printk(KERN_NOTICE "uclinux[mtd]: RAM probe address=0x%x size=0x%x\n", (int) mapp-&gt;phys, (int) mapp-&gt;size); -mapp-&gt;virt = phys_to_virt(mapp-&gt;phys); +mapp-&gt;virt = (void __iomem *) (unsigned long) phys_to_virt(mapp-&gt;phys); -if (mapp-&gt;virt == 0) { -printk("uclinux[mtd]: no virtual mapping?\n"); -return(-EIO); +if (mapp-&gt;virt == NULL) { +printk(KERN_ERR "uclinux[mtd]: no virtual mapping?\n"); +return -EIO; } simple_map_init(mapp); mtd = do_map_probe("map_ram", mapp); if (!mtd) { -printk("uclinux[mtd]: failed to find a mapping?\n"); -return(-ENXIO); +printk(KERN_ERR "uclinux[mtd]: failed to find a mapping?\n"); +return -ENXIO; } mtd-&gt;owner = THIS_MODULE; &lt; at &gt;&lt; at &gt; -90,20 +87,15 &lt; at &gt;&lt; at &gt; static int __init uclinux_mtd_init(void) uclinux_ram_mtdinfo = mtd; mtd_device_register(mtd, uclinux_romfs, NUM_PARTITIONS); -return(0); +return 0; } /****************************************************************************/ static void __exit uclinux_mtd_cleanup(void) { -if (uclinux_ram_mtdinfo) { -mtd_device_unregister(uclinux_ram_mtdinfo); -map_destroy(uclinux_ram_mtdinfo); -uclinux_ram_mtdinfo = NULL; -} -if (uclinux_ram_map.virt) -uclinux_ram_map.virt = 0; +mtd_device_unregister(uclinux_ram_mtdinfo); +map_destroy(uclinux_ram_mtdinfo); } /****************************************************************************/ </pre> gerg< at >snapgear.com 2012-05-15T04:08:48 http://comments.gmane.org/gmane.linux.uclinux.devel/20405 <pre>Hi, I'm currently using the 'experimental' pre-built gcc toolchain from &lt;http://www.uclinux.org/pub/uClinux/arm-elf-tools/tools-20080626/m68k-uclinux-tools-20080626.sh&gt; to build my uClinux-dist. I've never found any issue with that package, so I didn't even bother to build my own toolchain. But now I'm wondering: Is there a newer/better pre-built toolchain, or sorces for building a more recent one. Thanks, Luis _______________________________________________ uClinux-dev mailing list uClinux-dev&lt; at &gt;uclinux.org http://mailman.uclinux.org/mailman/listinfo/uclinux-dev This message was resent by uclinux-dev&lt; at &gt;uclinux.org To unsubscribe see: http://mailman.uclinux.org/mailman/options/uclinux-dev </pre> Luis Alves 2012-05-14T15:07:52 http://comments.gmane.org/gmane.linux.uclinux.devel/20397 <pre>Basic support for the m5253demo board from Freescale. This is a work in progress, currently only the dm9000 ethernet interface is supported. More patches to come ;) This patch is against the v3.4-rc6 for_next branch of the m68knommu.git Signed-off-by: Steven King &lt;sfking&lt; at &gt;fdwdc.com&gt; --- arch/m68k/Kconfig.machine | 7 ++ arch/m68k/include/asm/io_no.h | 8 ++ arch/m68k/include/asm/m525xsim.h | 4 + arch/m68k/platform/coldfire/Makefile | 1 + arch/m68k/platform/coldfire/m5253demo.c | 125 +++++++++++++++++++++++++++++++ 5 files changed, 145 insertions(+) diff --git a/arch/m68k/Kconfig.machine b/arch/m68k/Kconfig.machine index 7cdf6b0..10c97dc 100644 --- a/arch/m68k/Kconfig.machine +++ b/arch/m68k/Kconfig.machine &lt; at &gt;&lt; at &gt; -252,6 +252,13 &lt; at &gt;&lt; at &gt; config M5249C3 help Support for the Motorola M5249C3 board. +config M5253DEMO +bool "Freescale M5253DEMO board support" +depends on M525x +select FREESCALE +help + Support for the Freescale M5253DEMO board. + config M5271EVB bool "Freescale (Motorola) M5271EVB board support" depends on M5271 diff --git a/arch/m68k/include/asm/io_no.h b/arch/m68k/include/asm/io_no.h index 353bf75..3d18c94 100644 --- a/arch/m68k/include/asm/io_no.h +++ b/arch/m68k/include/asm/io_no.h &lt; at &gt;&lt; at &gt; -135,6 +135,14 &lt; at &gt;&lt; at &gt; static inline void io_insl(unsigned int addr, void *buf, int len) #define insw(a,b,l) io_insw(a,b,l) #define insl(a,b,l) io_insl(a,b,l) +#define writesb(a, b, l) io_outsb((unsigned int)a, b, l) +#define writesw(a, b, l) io_outsw((unsigned int)a, b, l) +#define writesl(a, b, l) io_outsl((unsigned int)a, b, l) + +#define readsb(a, b, l) io_insb((unsigned int)a, b, l) +#define readsw(a, b, l) io_insw((unsigned int)a, b, l) +#define readsl(a, b, l) io_insl((unsigned int)a, b, l) + #define IO_SPACE_LIMIT 0xffffffff diff --git a/arch/m68k/include/asm/m525xsim.h b/arch/m68k/include/asm/m525xsim.h index 3d62b9d..46fbb34 100644 --- a/arch/m68k/include/asm/m525xsim.h +++ b/arch/m68k/include/asm/m525xsim.h &lt; at &gt;&lt; at &gt; -105,6 +105,10 &lt; at &gt;&lt; at &gt; #define MCFQSPI_CS015 #define MCFQSPI_CS116 #define MCFQSPI_CS224 +#if !IS_ENABLED(CONFIG_DM9000) +/* on the m5253demo the CS1/QSPICS3 is used as CS for the dm9000 */ +#define MCFQSPI_CS328 +#endif /* *I2C module. diff --git a/arch/m68k/platform/coldfire/Makefile b/arch/m68k/platform/coldfire/Makefile index 82f0764..612f8cd 100644 --- a/arch/m68k/platform/coldfire/Makefile +++ b/arch/m68k/platform/coldfire/Makefile &lt; at &gt;&lt; at &gt; -32,6 +32,7 &lt; at &gt;&lt; at &gt; obj-$(CONFIG_M54xx)+= m54xx.o sltimers.o intc-2.o obj-$(CONFIG_NETtel)+= nettel.o obj-$(CONFIG_CLEOPATRA)+= nettel.o obj-$(CONFIG_FIREBEE)+= firebee.o +obj-$(CONFIG_M5253DEMO)+= m5253demo.o obj-y+= pinmux.o gpio.o extra-y := head.o diff --git a/arch/m68k/platform/coldfire/m5253demo.c b/arch/m68k/platform/coldfire/m5253demo.c new file mode 100644 index 0000000..9041e1b --- /dev/null +++ b/arch/m68k/platform/coldfire/m5253demo.c &lt; at &gt;&lt; at &gt; -0,0 +1,125 &lt; at &gt;&lt; at &gt; +/***************************************************************************/ +/* + *m5253demo.c -- board support for the Freescale M5253demo board + * + *Copyright (C) 2012, Steven King &lt;sfking&lt; at &gt;fdwdc.com&gt; + */ + +/***************************************************************************/ + +#include &lt;linux/kernel.h&gt; +#include &lt;linux/param.h&gt; +#include &lt;linux/init.h&gt; +#include &lt;linux/io.h&gt; +#include &lt;linux/platform_device.h&gt; +#include &lt;linux/gpio.h&gt; +#include &lt;linux/dm9000.h&gt; +#include &lt;asm/coldfire.h&gt; +#include &lt;asm/mcfsim.h&gt; + + +/***************************************************************************/ +#if IS_ENABLED(CONFIG_DM9000) + +/* The m5253demo has the DM9000 at 0x0e0000300/0x0e0000304, gpio5/irq 37 */ + +#define DM9000_ADDR0xe0000300 +#define DM9000_DATA0xe0000304 +#define DM9000_IRQMCF_IRQ_GPIO5 + +#define DM9000_GPIO(DM9000_IRQ - MCF_IRQ_GPIO0) + +static struct resource m5253demo_dm9000_resources[] = { +[0] = { +.start= DM9000_ADDR, +.end= DM9000_ADDR + 0x3, +.flags= IORESOURCE_MEM, +}, +[1] = { +.start= DM9000_DATA, +.end= DM9000_DATA + 0x3, +.flags= IORESOURCE_MEM, +}, +[2] = { +.start= DM9000_IRQ, +.end= DM9000_IRQ, +.flags= IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, +}, +}; + +static void m5253demo_dm9000_inblk(void __iomem *reg, void *data, int len) +{ +u16 *buf = data; +int n = (len + 1) &gt;&gt; 1; +while (n-- &gt; 0) +*buf++ = readw(reg); +} + +static void m5253demo_dm9000_outblk(void __iomem *reg, void *data, int len) +{ +u16 *buf = data; +int n = (len + 1) &gt;&gt; 1; +while (n-- &gt; 0) +writew(*buf++, reg); +} + +static void m5253demo_dm9000_dumpblk(void __iomem *reg, int len) +{ +int n = (len + 1) &gt;&gt; 1; +while (n-- &gt; 0) +readw(reg); +} + +static struct dm9000_plat_data m5253demo_dm9000_platdata = { +.flags= DM9000_PLATF_NO_EEPROM, +.inblk= m5253demo_dm9000_inblk, +.outblk= m5253demo_dm9000_outblk, +.dumpblk= m5253demo_dm9000_dumpblk, +}; + +static struct platform_device m5253demo_dm9000 = { +.name= "dm9000", +.id= -1, +.num_resources= ARRAY_SIZE(m5253demo_dm9000_resources), +.resource= m5253demo_dm9000_resources, +.dev.platform_data= &amp;m5253demo_dm9000_platdata, +}; + +static void __init m5253demo_dm9000_init(void) +{ +u32 r; +int status; + +/* set the gpio function for DM9000_GPIO to gpio */ +/* FIXME: replace with pinmux/pinctl support */ +r = readl(MCFSIM2_GPIOFUNC); +r |= 1 &lt;&lt; DM9000_GPIO; +writel(r, MCFSIM2_GPIOFUNC); + +/* reserve the gpio so nothing else can request it */ +/* FIXME: replace with pinmux/pinctl support */ +status = gpio_request(DM9000_GPIO, "DM9000_GPIO"); +if (status) +pr_warn("gpio_request for DM9000_GPIO failed\n"); +/* set the priority level for DM9000 gpio irq */ +r = readl(MCFINTC2_INTPRI_REG(DM9000_IRQ)); +r &amp;= ~MCFINTC2_INTPRI_BITS(0xf, DM9000_IRQ); +r |= MCFINTC2_INTPRI_BITS(0x4, DM9000_IRQ); +writel(r, MCFINTC2_INTPRI_REG(DM9000_IRQ)); +} +#endif /* IS_ENABLED(CONFIG_DM9000) */ + +static struct platform_device *m5253demo_devices[] __initdata = { +&amp;m5253demo_dm9000, +}; + +static int __init m5253demo_init(void) +{ +m5253demo_dm9000_init(); +platform_add_devices(m5253demo_devices, ARRAY_SIZE(m5253demo_devices)); +return 0; +} + +arch_initcall(m5253demo_init); + +/***************************************************************************/ _______________________________________________ uClinux-dev mailing list uClinux-dev&lt; at &gt;uclinux.org http://mailman.uclinux.org/mailman/listinfo/uclinux-dev This message was resent by uclinux-dev&lt; at &gt;uclinux.org To unsubscribe see: http://mailman.uclinux.org/mailman/options/uclinux-dev </pre> Steven King 2012-05-14T00:50:04 http://comments.gmane.org/gmane.linux.uclinux.devel/20396 <pre>The 5251/5253 is quite similar to the 5249, adding basic support for it is fairly trivial. This is a work in progress, not much support for anything beyond the basic Coldfire core is implemented yet, but more patches to come ;) This patch is against the v3.4-rc6 for_next branch of the m68knommu.git Signed-off-by: Steven King &lt;sfking&lt; at &gt;fdwdc.com&gt; --- arch/m68k/Kconfig.cpu | 8 ++ arch/m68k/Makefile | 1 + arch/m68k/include/asm/dma.h | 4 +- arch/m68k/include/asm/gpio.h | 6 +- arch/m68k/include/asm/m525xsim.h | 195 +++++++++++++++++++++++++++++++ arch/m68k/include/asm/mcfsim.h | 3 + arch/m68k/include/asm/mcfuart.h | 4 +- arch/m68k/platform/coldfire/Makefile | 1 + arch/m68k/platform/coldfire/head.S | 6 +- arch/m68k/platform/coldfire/intc-525x.c | 91 +++++++++++++++ arch/m68k/platform/coldfire/m525x.c | 58 +++++++++ drivers/spi/Kconfig | 2 +- 12 files changed, 369 insertions(+), 10 deletions(-) diff --git a/arch/m68k/Kconfig.cpu b/arch/m68k/Kconfig.cpu index 8a9c767..2229ebc 100644 --- a/arch/m68k/Kconfig.cpu +++ b/arch/m68k/Kconfig.cpu &lt; at &gt;&lt; at &gt; -166,6 +166,14 &lt; at &gt;&lt; at &gt; config M5249 help Motorola ColdFire 5249 processor support. +config M525x +bool "MCF525x" +depends on !MMU +select COLDFIRE_SW_A7 +select HAVE_MBAR +help + Freescale (Motorola) Coldfire 5251/5253 processor support. + config M527x bool diff --git a/arch/m68k/Makefile b/arch/m68k/Makefile index 804f139..a1d59b1 100644 --- a/arch/m68k/Makefile +++ b/arch/m68k/Makefile &lt; at &gt;&lt; at &gt; -43,6 +43,7 &lt; at &gt;&lt; at &gt; cpuflags-$(CONFIG_M5275):= $(call cc-option,-mcpu=5275,-m5307) cpuflags-$(CONFIG_M5272):= $(call cc-option,-mcpu=5272,-m5307) cpuflags-$(CONFIG_M5271):= $(call cc-option,-mcpu=5271,-m5307) cpuflags-$(CONFIG_M523x):= $(call cc-option,-mcpu=523x,-m5307) +cpuflags-$(CONFIG_M525x):= $(call cc-option,-mcpu=5253,-m5200) cpuflags-$(CONFIG_M5249):= $(call cc-option,-mcpu=5249,-m5200) cpuflags-$(CONFIG_M520x):= $(call cc-option,-mcpu=5208,-m5200) cpuflags-$(CONFIG_M5206e):= $(call cc-option,-mcpu=5206e,-m5200) diff --git a/arch/m68k/include/asm/dma.h b/arch/m68k/include/asm/dma.h index 6fbdfe8..9470641 100644 --- a/arch/m68k/include/asm/dma.h +++ b/arch/m68k/include/asm/dma.h &lt; at &gt;&lt; at &gt; -33,7 +33,9 &lt; at &gt;&lt; at &gt; * Set number of channels of DMA on ColdFire for different implementations. */ #if defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) || \ -defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) +defined(CONFIG_M523x) || defined(CONFIG_M527x) || \ +defined(CONFIG_M528x) || defined(CONFIG_M525x) + #define MAX_M68K_DMA_CHANNELS 4 #elif defined(CONFIG_M5272) #define MAX_M68K_DMA_CHANNELS 1 diff --git a/arch/m68k/include/asm/gpio.h b/arch/m68k/include/asm/gpio.h index 00d0071..588cfda 100644 --- a/arch/m68k/include/asm/gpio.h +++ b/arch/m68k/include/asm/gpio.h &lt; at &gt;&lt; at &gt; -55,7 +55,7 &lt; at &gt;&lt; at &gt; #define mcfgpio_read(port)__raw_readw(port) #define mcfgpio_write(data, port)__raw_writew(data, port) -#elif defined(CONFIG_M5249) +#elif defined(CONFIG_M5249) || defined(CONFIG_M525x) /* These parts have GPIO organized by 32 bit ports */ &lt; at &gt;&lt; at &gt; -116,7 +116,7 &lt; at &gt;&lt; at &gt; static inline u32 __mcf_gpio_ppdr(unsigned gpio) return MCFSIM_PBDAT; else return MCFSIM_PCDAT; -#elif defined(CONFIG_M5249) +#elif defined(CONFIG_M5249) || defined(CONFIG_M525x) if (gpio &lt; 32) return MCFSIM2_GPIOREAD; else &lt; at &gt;&lt; at &gt; -155,7 +155,7 &lt; at &gt;&lt; at &gt; static inline u32 __mcf_gpio_podr(unsigned gpio) return MCFSIM_PBDAT; else return MCFSIM_PCDAT; -#elif defined(CONFIG_M5249) +#elif defined(CONFIG_M5249) || defined(CONFIG_M525x) if (gpio &lt; 32) return MCFSIM2_GPIOWRITE; else diff --git a/arch/m68k/include/asm/m525xsim.h b/arch/m68k/include/asm/m525xsim.h new file mode 100644 index 0000000..3d62b9d --- /dev/null +++ b/arch/m68k/include/asm/m525xsim.h &lt; at &gt;&lt; at &gt; -0,0 +1,195 &lt; at &gt;&lt; at &gt; +/****************************************************************************/ + +/* + *m525xsim.h -- ColdFire 525x System Integration Module support. + * + *(C) Copyright 2012, Steven King &lt;sfking&lt; at &gt;fdwdc.com&gt; + *(C) Copyright 2002, Greg Ungerer (gerg&lt; at &gt;snapgear.com) + */ + +/****************************************************************************/ +#ifndefm525xsim_h +#define m525xsim_h +/****************************************************************************/ + +#define CPU_NAME"COLDFIRE(m525x)" +#define CPU_INSTR_PER_JIFFY3 +#define MCF_BUSCLK(MCF_CLK / 2) + +#include &lt;asm/m52xxacr.h&gt; + +/* + *The 525x has a second MBAR region, define its address. + */ +#define MCF_MBAR20x80000000 + +/* + *Define the 525x SIM register set addresses. + */ +#define MCFSIM_RSR0x00/* Reset Status reg (r/w) */ +#define MCFSIM_SYPCR0x01/* System Protection reg (r/w)*/ +#define MCFSIM_SWIVR0x02/* SW Watchdog intr reg (r/w) */ +#define MCFSIM_SWSR0x03/* SW Watchdog service (r/w) */ +#define MCFSIM_MPARK0x0C/* BUS Master Control Reg*/ +#define MCFSIM_IPR0x40/* Interrupt Pend reg (r/w) */ +#define MCFSIM_IMR0x44/* Interrupt Mask reg (r/w) */ +#define MCFSIM_ICR00x4c/* Intr Ctrl reg 0 (r/w) */ +#define MCFSIM_ICR10x4d/* Intr Ctrl reg 1 (r/w) */ +#define MCFSIM_ICR20x4e/* Intr Ctrl reg 2 (r/w) */ +#define MCFSIM_ICR30x4f/* Intr Ctrl reg 3 (r/w) */ +#define MCFSIM_ICR40x50/* Intr Ctrl reg 4 (r/w) */ +#define MCFSIM_ICR50x51/* Intr Ctrl reg 5 (r/w) */ +#define MCFSIM_ICR60x52/* Intr Ctrl reg 6 (r/w) */ +#define MCFSIM_ICR70x53/* Intr Ctrl reg 7 (r/w) */ +#define MCFSIM_ICR80x54/* Intr Ctrl reg 8 (r/w) */ +#define MCFSIM_ICR90x55/* Intr Ctrl reg 9 (r/w) */ +#define MCFSIM_ICR100x56/* Intr Ctrl reg 10 (r/w) */ +#define MCFSIM_ICR110x57/* Intr Ctrl reg 11 (r/w) */ + +#define MCFSIM_CSAR00x80/* CS 0 Address 0 reg (r/w) */ +#define MCFSIM_CSMR00x84/* CS 0 Mask 0 reg (r/w) */ +#define MCFSIM_CSCR00x8a/* CS 0 Control reg (r/w) */ +#define MCFSIM_CSAR10x8c/* CS 1 Address reg (r/w) */ +#define MCFSIM_CSMR10x90/* CS 1 Mask reg (r/w) */ +#define MCFSIM_CSCR10x96/* CS 1 Control reg (r/w) */ +#define MCFSIM_CSAR20x98/* CS 2 Address reg (r/w) */ +#define MCFSIM_CSMR20x9c/* CS 2 Mask reg (r/w) */ +#define MCFSIM_CSCR20xa2/* CS 2 Control reg (r/w) */ +#define MCFSIM_CSAR30xa4/* CS 3 Address reg (r/w) */ +#define MCFSIM_CSMR30xa8/* CS 3 Mask reg (r/w) */ +#define MCFSIM_CSCR30xae/* CS 3 Control reg (r/w) */ +#define MCFSIM_CSAR40xb0/* CS 4 Address reg (r/w) */ +#define MCFSIM_CSMR40xb4/* CS 4 Mask reg (r/w) */ +#define MCFSIM_CSCR40xba/* CS 4 Control reg (r/w) */ + +#define MCFSIM_DCR(MCF_MBAR + 0x100)/* DRAM Control */ +#define MCFSIM_DACR0(MCF_MBAR + 0x108)/* DRAM 0 Addr/Ctrl */ +#define MCFSIM_DMR0(MCF_MBAR + 0x10c)/* DRAM 0 Mask */ + +/* + * Secondary Interrupt Controller (in MBAR2) +*/ +#define MCFINTC2_INTBASE(MCF_MBAR2 + 0x168)/* Base Vector Reg */ +#define MCFINTC2_INTPRI1(MCF_MBAR2 + 0x140)/* 0-7 priority */ +#define MCFINTC2_INTPRI2(MCF_MBAR2 + 0x144)/* 8-15 priority */ +#define MCFINTC2_INTPRI3(MCF_MBAR2 + 0x148)/* 16-23 priority */ +#define MCFINTC2_INTPRI4(MCF_MBAR2 + 0x14c)/* 24-31 priority */ +#define MCFINTC2_INTPRI5(MCF_MBAR2 + 0x150)/* 32-39 priority */ +#define MCFINTC2_INTPRI6(MCF_MBAR2 + 0x154)/* 40-47 priority */ +#define MCFINTC2_INTPRI7(MCF_MBAR2 + 0x158)/* 48-55 priority */ +#define MCFINTC2_INTPRI8(MCF_MBAR2 + 0x15c)/* 56-63 priority */ + +#define MCFINTC2_INTPRI_REG(i)(MCFINTC2_INTPRI1 + \ +((((i) - MCFINTC2_VECBASE) / 8) * 4)) +#define MCFINTC2_INTPRI_BITS(b, i)((b) &lt;&lt; (((i) % 8) * 4)) + +/* + *Timer module. + */ +#define MCFTIMER_BASE1(MCF_MBAR + 0x140)/* Base of TIMER1 */ +#define MCFTIMER_BASE2(MCF_MBAR + 0x180)/* Base of TIMER2 */ + +/* + *UART module. + */ +#define MCFUART_BASE0(MCF_MBAR + 0x1c0)/* Base address UART0 */ +#define MCFUART_BASE1(MCF_MBAR + 0x200)/* Base address UART1 */ + +/* + *QSPI module. + */ +#define MCFQSPI_BASE(MCF_MBAR + 0x300)/* Base address QSPI */ +#define MCFQSPI_SIZE0x40/* Register set size */ + + +#define MCFQSPI_CS015 +#define MCFQSPI_CS116 +#define MCFQSPI_CS224 + +/* + *I2C module. + */ +#define MCFI2C_BASE(MCF_MBAR + 280)/* Base addreess I2C0 */ +#define MCFI2C_SIZE0x20/* Register set size */ + +#define MCFI2C_BASE1(MCF_MBAR2 + 440)/* Base addreess I2C1 */ +#define MCFI2C_SIZE10x20/* Register set size */ +/* + *DMA unit base addresses. + */ +#define MCFDMA_BASE0(MCF_MBAR + 0x300)/* Base address DMA 0 */ +#define MCFDMA_BASE1(MCF_MBAR + 0x340)/* Base address DMA 1 */ +#define MCFDMA_BASE2(MCF_MBAR + 0x380)/* Base address DMA 2 */ +#define MCFDMA_BASE3(MCF_MBAR + 0x3C0)/* Base address DMA 3 */ + +/* + *Some symbol defines for the above... + */ +#define MCFSIM_SWDICRMCFSIM_ICR0/* Watchdog timer ICR */ +#define MCFSIM_TIMER1ICRMCFSIM_ICR1/* Timer 1 ICR */ +#define MCFSIM_TIMER2ICRMCFSIM_ICR2/* Timer 2 ICR */ +#define MCFSIM_I2CICRMCFSIM_ICR3/* I2C ICR */ +#define MCFSIM_UART1ICRMCFSIM_ICR4/* UART 1 ICR */ +#define MCFSIM_UART2ICRMCFSIM_ICR5/* UART 2 ICR */ +#define MCFSIM_DMA0ICRMCFSIM_ICR6/* DMA 0 ICR */ +#define MCFSIM_DMA1ICRMCFSIM_ICR7/* DMA 1 ICR */ +#define MCFSIM_DMA2ICRMCFSIM_ICR8/* DMA 2 ICR */ +#define MCFSIM_DMA3ICRMCFSIM_ICR9/* DMA 3 ICR */ +#define MCFSIM_QSPIICRMCFSIM_ICR10/* QSPI ICR */ + +/* + *Define system peripheral IRQ usage. + */ +#define MCF_IRQ_QSPI28/* QSPI, Level 4 */ +#define MCF_IRQ_I2C29 +#define MCF_IRQ_TIMER30/* Timer0, Level 6 */ +#define MCF_IRQ_PROFILER31/* Timer1, Level 7 */ + +#define MCF_IRQ_UART073/* UART0 */ +#define MCF_IRQ_UART174/* UART1 */ + +/* + * Define the base interrupt for the second interrupt controller. + * We set it to 128, out of the way of the base interrupts, and plenty + * of room for its 64 interrupts. + */ +#define MCFINTC2_VECBASE128 + +#define MCF_IRQ_GPIO0(MCFINTC2_VECBASE + 32) +#define MCF_IRQ_GPIO1(MCFINTC2_VECBASE + 33) +#define MCF_IRQ_GPIO2(MCFINTC2_VECBASE + 34) +#define MCF_IRQ_GPIO3(MCFINTC2_VECBASE + 35) +#define MCF_IRQ_GPIO4(MCFINTC2_VECBASE + 36) +#define MCF_IRQ_GPIO5(MCFINTC2_VECBASE + 37) +#define MCF_IRQ_GPIO6(MCFINTC2_VECBASE + 38) + +#define MCF_IRQ_USBWUP(MCFINTC2_VECBASE + 40) +#define MCF_IRQ_I2C1(MCFINTC2_VECBASE + 62) + +/* + *General purpose IO registers (in MBAR2). + */ +#define MCFSIM2_GPIOREAD(MCF_MBAR2 + 0x000)/* GPIO read values */ +#define MCFSIM2_GPIOWRITE(MCF_MBAR2 + 0x004)/* GPIO write values */ +#define MCFSIM2_GPIOENABLE(MCF_MBAR2 + 0x008)/* GPIO enabled */ +#define MCFSIM2_GPIOFUNC(MCF_MBAR2 + 0x00C)/* GPIO function */ +#define MCFSIM2_GPIO1READ(MCF_MBAR2 + 0x0B0)/* GPIO1 read values */ +#define MCFSIM2_GPIO1WRITE(MCF_MBAR2 + 0x0B4)/* GPIO1 write values */ +#define MCFSIM2_GPIO1ENABLE(MCF_MBAR2 + 0x0B8)/* GPIO1 enabled */ +#define MCFSIM2_GPIO1FUNC(MCF_MBAR2 + 0x0BC)/* GPIO1 function */ + +#define MCFSIM2_GPIOINTSTAT(MCF_MBAR2 + 0xc0)/* GPIO intr status */ +#define MCFSIM2_GPIOINTCLEAR(MCF_MBAR2 + 0xc0)/* GPIO intr clear */ +#define MCFSIM2_GPIOINTENABLE(MCF_MBAR2 + 0xc4)/* GPIO intr enable */ + +/* + * Generic GPIO support + */ +#define MCFGPIO_PIN_MAX64 +#define MCFGPIO_IRQ_MAX6 +#define MCFGPIO_IRQ_VECBASEMCF_IRQ_GPIO0 + +/****************************************************************************/ + +#endif/* m525xsim_h */ + diff --git a/arch/m68k/include/asm/mcfsim.h b/arch/m68k/include/asm/mcfsim.h index ebd0304..6871f62 100644 --- a/arch/m68k/include/asm/mcfsim.h +++ b/arch/m68k/include/asm/mcfsim.h &lt; at &gt;&lt; at &gt; -27,6 +27,9 &lt; at &gt;&lt; at &gt; #elif defined(CONFIG_M5249) #include &lt;asm/m5249sim.h&gt; #include &lt;asm/mcfintc.h&gt; +#elif defined(CONFIG_M525x) +#include &lt;asm/m525xsim.h&gt; +#include &lt;asm/mcfintc.h&gt; #elif defined(CONFIG_M527x) #include &lt;asm/m527xsim.h&gt; #elif defined(CONFIG_M5272) diff --git a/arch/m68k/include/asm/mcfuart.h b/arch/m68k/include/asm/mcfuart.h index 2d3bc77..b40c20f 100644 --- a/arch/m68k/include/asm/mcfuart.h +++ b/arch/m68k/include/asm/mcfuart.h &lt; at &gt;&lt; at &gt; -43,8 +43,8 &lt; at &gt;&lt; at &gt; struct mcf_platform_uart { #defineMCFUART_UFPD0x30/* Frac Prec. Divider (r/w) */ #endif #if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \ - defined(CONFIG_M5249) || defined(CONFIG_M5307) || \ - defined(CONFIG_M5407) +defined(CONFIG_M5249) || defined(CONFIG_M525x) || \ +defined(CONFIG_M5307) || defined(CONFIG_M5407) #defineMCFUART_UIVR0x30/* Interrupt Vector (r/w) */ #endif #defineMCFUART_UIPR0x34/* Input Port (r) */ diff --git a/arch/m68k/platform/coldfire/Makefile b/arch/m68k/platform/coldfire/Makefile index 76d389d..82f0764 100644 --- a/arch/m68k/platform/coldfire/Makefile +++ b/arch/m68k/platform/coldfire/Makefile &lt; at &gt;&lt; at &gt; -20,6 +20,7 &lt; at &gt;&lt; at &gt; obj-$(CONFIG_M5206e)+= m5206.o timers.o intc.o reset.o obj-$(CONFIG_M520x)+= m520x.o pit.o intc-simr.o reset.o obj-$(CONFIG_M523x)+= m523x.o pit.o dma_timer.o intc-2.o reset.o obj-$(CONFIG_M5249)+= m5249.o timers.o intc.o intc-5249.o reset.o +obj-$(CONFIG_M525x)+= m525x.o timers.o intc.o intc-525x.o reset.o obj-$(CONFIG_M527x)+= m527x.o pit.o intc-2.o reset.o obj-$(CONFIG_M5272)+= m5272.o intc-5272.o timers.o obj-$(CONFIG_M528x)+= m528x.o pit.o intc-2.o reset.o diff --git a/arch/m68k/platform/coldfire/head.S b/arch/m68k/platform/coldfire/head.S index c3db70e..4e0c9eb 100644 --- a/arch/m68k/platform/coldfire/head.S +++ b/arch/m68k/platform/coldfire/head.S &lt; at &gt;&lt; at &gt; -31,9 +31,9 &lt; at &gt;&lt; at &gt; .endm #elif defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \ - defined(CONFIG_M5249) || defined(CONFIG_M527x) || \ - defined(CONFIG_M528x) || defined(CONFIG_M5307) || \ - defined(CONFIG_M5407) + defined(CONFIG_M5249) || defined(CONFIG_M525x) || \ + defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ + defined(CONFIG_M5307) || defined(CONFIG_M5407) /* *Not all these devices have exactly the same DRAM controller, *but the DCMR register is virtually identical - give or take diff --git a/arch/m68k/platform/coldfire/intc-525x.c b/arch/m68k/platform/coldfire/intc-525x.c new file mode 100644 index 0000000..b23204d --- /dev/null +++ b/arch/m68k/platform/coldfire/intc-525x.c &lt; at &gt;&lt; at &gt; -0,0 +1,91 &lt; at &gt;&lt; at &gt; +/* + * intc2.c -- support for the 2nd INTC controller of the 525x + * + * (C) Copyright 2012, Steven King &lt;sfking&lt; at &gt;fdwdc.com&gt; + * (C) Copyright 2009, Greg Ungerer &lt;gerg&lt; at &gt;snapgear.com&gt; + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +#include &lt;linux/types.h&gt; +#include &lt;linux/init.h&gt; +#include &lt;linux/kernel.h&gt; +#include &lt;linux/interrupt.h&gt; +#include &lt;linux/irq.h&gt; +#include &lt;linux/io.h&gt; +#include &lt;asm/coldfire.h&gt; +#include &lt;asm/mcfsim.h&gt; + +static void intc2_irq_gpio_mask(struct irq_data *d) +{ +u32 imr = readl(MCFSIM2_GPIOINTENABLE); +u32 type = irqd_get_trigger_type(d); +int irq = d-&gt;irq - MCF_IRQ_GPIO0; + +if (type &amp; IRQ_TYPE_EDGE_RISING) +imr &amp;= ~(0x001 &lt;&lt; irq); +if (type &amp; IRQ_TYPE_EDGE_FALLING) +imr &amp;= ~(0x100 &lt;&lt; irq); +writel(imr, MCFSIM2_GPIOINTENABLE); +} + +static void intc2_irq_gpio_unmask(struct irq_data *d) +{ +u32 imr = readl(MCFSIM2_GPIOINTENABLE); +u32 type = irqd_get_trigger_type(d); +int irq = d-&gt;irq - MCF_IRQ_GPIO0; + +if (type &amp; IRQ_TYPE_EDGE_RISING) +imr |= (0x001 &lt;&lt; irq); +if (type &amp; IRQ_TYPE_EDGE_FALLING) +imr |= (0x100 &lt;&lt; irq); +writel(imr, MCFSIM2_GPIOINTENABLE); +} + +static void intc2_irq_gpio_ack(struct irq_data *d) +{ +u32 imr = 0; +u32 type = irqd_get_trigger_type(d); +int irq = d-&gt;irq - MCF_IRQ_GPIO0; + +if (type &amp; IRQ_TYPE_EDGE_RISING) +imr |= (0x001 &lt;&lt; irq); +if (type &amp; IRQ_TYPE_EDGE_FALLING) +imr |= (0x100 &lt;&lt; irq); +writel(imr, MCFSIM2_GPIOINTCLEAR); +} + +static int intc2_irq_gpio_set_type(struct irq_data *d, unsigned int f) +{ +if (f &amp; ~IRQ_TYPE_EDGE_BOTH) +return -EINVAL; +return 0; +} + +static struct irq_chip intc2_irq_gpio_chip = { +.name= "CF-INTC2", +.irq_mask= intc2_irq_gpio_mask, +.irq_unmask= intc2_irq_gpio_unmask, +.irq_ack= intc2_irq_gpio_ack, +.irq_set_type= intc2_irq_gpio_set_type, +}; + +static int __init mcf_intc2_init(void) +{ +int irq; + +/* set the interrupt base for the second interrupt controller */ +writel(MCFINTC2_VECBASE, MCFINTC2_INTBASE); + +/* GPIO interrupt sources */ +for (irq = MCF_IRQ_GPIO0; (irq &lt;= MCF_IRQ_GPIO6); irq++) { +irq_set_chip(irq, &amp;intc2_irq_gpio_chip); +irq_set_handler(irq, handle_edge_irq); +} + +return 0; +} + +arch_initcall(mcf_intc2_init); diff --git a/arch/m68k/platform/coldfire/m525x.c b/arch/m68k/platform/coldfire/m525x.c new file mode 100644 index 0000000..7c56be2 --- /dev/null +++ b/arch/m68k/platform/coldfire/m525x.c &lt; at &gt;&lt; at &gt; -0,0 +1,58 &lt; at &gt;&lt; at &gt; +/***************************************************************************/ + +/* + *525x.c + * + *Copyright (C) 2012, Steven King &lt;sfking&lt; at &gt;fdwdc.com&gt; + */ + +/***************************************************************************/ + +#include &lt;linux/kernel.h&gt; +#include &lt;linux/param.h&gt; +#include &lt;linux/init.h&gt; +#include &lt;linux/io.h&gt; +#include &lt;linux/platform_device.h&gt; +#include &lt;asm/machdep.h&gt; +#include &lt;asm/coldfire.h&gt; +#include &lt;asm/mcfsim.h&gt; +#include &lt;asm/mcfgpio.h&gt; + +/***************************************************************************/ + +struct mcf_gpio_chip mcf_gpio_chips[] = { +MCFGPS(GPIO0, 0, 32, MCFSIM2_GPIOENABLE, MCFSIM2_GPIOWRITE, MCFSIM2_GPIOREAD), +MCFGPS(GPIO1, 32, 32, MCFSIM2_GPIO1ENABLE, MCFSIM2_GPIO1WRITE, MCFSIM2_GPIO1READ), +}; + +unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips); + +/***************************************************************************/ + + +static void __init m525x_qspi_init(void) +{ +#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) +/* set the GPIO function for the qspi cs gpios */ +/* FIXME: replace with pinmux/pinctl support */ +u32 f = readl(MCFSIM2_GPIOFUNC); +f |= (1 &lt;&lt; MCFQSPI_CS2) | (1 &lt;&lt; MCFQSPI_CS1) | (1 &lt;&lt; MCFQSPI_CS0); +writel(f, MCFSIM2_GPIOFUNC); + +/* QSPI irq setup */ +writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0, + MCF_MBAR + MCFSIM_QSPIICR); +mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI); +#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */ +} + +/***************************************************************************/ + +void __init config_BSP(char *commandp, int size) +{ +mach_sched_init = hw_timer_init; + +m525x_qspi_init(); +} + +/***************************************************************************/ diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 00c0240..bfbc33d 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig &lt; at &gt;&lt; at &gt; -125,7 +125,7 &lt; at &gt;&lt; at &gt; config SPI_BUTTERFLY config SPI_COLDFIRE_QSPI tristate "Freescale Coldfire QSPI controller" -depends on (M520x || M523x || M5249 || M527x || M528x || M532x) +depends on (M520x || M523x || M5249 || M525x || M527x || M528x || M532x) help This enables support for the Coldfire QSPI controller in master mode. _______________________________________________ uClinux-dev mailing list uClinux-dev&lt; at &gt;uclinux.org http://mailman.uclinux.org/mailman/listinfo/uclinux-dev This message was resent by uclinux-dev&lt; at &gt;uclinux.org To unsubscribe see: http://mailman.uclinux.org/mailman/options/uclinux-dev </pre> Steven King 2012-05-14T00:44:44 http://comments.gmane.org/gmane.linux.uclinux.devel/20388 <pre>Use the new SPI queue framework; remove use of workqueue, replace mcfqspi_transfer with mcfqspi_transfer_one_message, add mcfqspi_prepare_transfer_hw and mcfqspi_unprepare_transfer_hw, update power management routines. Signed-off-by: Steven King &lt;sfking&lt; at &gt;fdwdc.com&gt; --- drivers/spi/spi-coldfire-qspi.c | 255 +++++++++++++++++--------------------- 1 files changed, 114 insertions(+), 141 deletions(-) diff --git a/drivers/spi/spi-coldfire-qspi.c b/drivers/spi/spi-coldfire-qspi.c index 6eee64a..b2d4b9e 100644 --- a/drivers/spi/spi-coldfire-qspi.c +++ b/drivers/spi/spi-coldfire-qspi.c &lt; at &gt;&lt; at &gt; -25,12 +25,12 &lt; at &gt;&lt; at &gt; #include &lt;linux/errno.h&gt; #include &lt;linux/platform_device.h&gt; #include &lt;linux/sched.h&gt; -#include &lt;linux/workqueue.h&gt; #include &lt;linux/delay.h&gt; #include &lt;linux/io.h&gt; #include &lt;linux/clk.h&gt; #include &lt;linux/err.h&gt; #include &lt;linux/spi/spi.h&gt; +#include &lt;linux/pm_runtime.h&gt; #include &lt;asm/coldfire.h&gt; #include &lt;asm/mcfsim.h&gt; &lt; at &gt;&lt; at &gt; -78,10 +78,7 &lt; at &gt;&lt; at &gt; struct mcfqspi { wait_queue_head_t waitq; -struct work_struct work; -struct workqueue_struct *workq; -spinlock_t lock; -struct list_head msgq; +struct device *dev; }; static void mcfqspi_wr_qmr(struct mcfqspi *mcfqspi, u16 val) &lt; at &gt;&lt; at &gt; -303,120 +300,80 &lt; at &gt;&lt; at &gt; static void mcfqspi_transfer_msg16(struct mcfqspi *mcfqspi, unsigned count, } } -static void mcfqspi_work(struct work_struct *work) +static int mcfqspi_transfer_one_message(struct spi_master *master, + struct spi_message *msg) { -struct mcfqspi *mcfqspi = container_of(work, struct mcfqspi, work); -unsigned long flags; - -spin_lock_irqsave(&amp;mcfqspi-&gt;lock, flags); -while (!list_empty(&amp;mcfqspi-&gt;msgq)) { -struct spi_message *msg; -struct spi_device *spi; -struct spi_transfer *xfer; -int status = 0; - -msg = container_of(mcfqspi-&gt;msgq.next, struct spi_message, - queue); - -list_del_init(&amp;msg-&gt;queue); -spin_unlock_irqrestore(&amp;mcfqspi-&gt;lock, flags); - -spi = msg-&gt;spi; - -list_for_each_entry(xfer, &amp;msg-&gt;transfers, transfer_list) { -bool cs_high = spi-&gt;mode &amp; SPI_CS_HIGH; -u16 qmr = MCFQSPI_QMR_MSTR; - -if (xfer-&gt;bits_per_word) -qmr |= xfer-&gt;bits_per_word &lt;&lt; 10; -else -qmr |= spi-&gt;bits_per_word &lt;&lt; 10; -if (spi-&gt;mode &amp; SPI_CPHA) -qmr |= MCFQSPI_QMR_CPHA; -if (spi-&gt;mode &amp; SPI_CPOL) -qmr |= MCFQSPI_QMR_CPOL; -if (xfer-&gt;speed_hz) -qmr |= mcfqspi_qmr_baud(xfer-&gt;speed_hz); -else -qmr |= mcfqspi_qmr_baud(spi-&gt;max_speed_hz); -mcfqspi_wr_qmr(mcfqspi, qmr); - -mcfqspi_cs_select(mcfqspi, spi-&gt;chip_select, cs_high); - -mcfqspi_wr_qir(mcfqspi, MCFQSPI_QIR_SPIFE); -if ((xfer-&gt;bits_per_word ? xfer-&gt;bits_per_word : -spi-&gt;bits_per_word) == 8) -mcfqspi_transfer_msg8(mcfqspi, xfer-&gt;len, - xfer-&gt;tx_buf, - xfer-&gt;rx_buf); -else -mcfqspi_transfer_msg16(mcfqspi, xfer-&gt;len / 2, - xfer-&gt;tx_buf, - xfer-&gt;rx_buf); -mcfqspi_wr_qir(mcfqspi, 0); - -if (xfer-&gt;delay_usecs) -udelay(xfer-&gt;delay_usecs); -if (xfer-&gt;cs_change) { -if (!list_is_last(&amp;xfer-&gt;transfer_list, - &amp;msg-&gt;transfers)) -mcfqspi_cs_deselect(mcfqspi, - spi-&gt;chip_select, - cs_high); -} else { -if (list_is_last(&amp;xfer-&gt;transfer_list, - &amp;msg-&gt;transfers)) -mcfqspi_cs_deselect(mcfqspi, - spi-&gt;chip_select, - cs_high); -} -msg-&gt;actual_length += xfer-&gt;len; +struct mcfqspi *mcfqspi = spi_master_get_devdata(master); +struct spi_device *spi = msg-&gt;spi; +struct spi_transfer *t; +int status = 0; + +list_for_each_entry(t, &amp;msg-&gt;transfers, transfer_list) { +bool cs_high = spi-&gt;mode &amp; SPI_CS_HIGH; +u16 qmr = MCFQSPI_QMR_MSTR; + +if (t-&gt;bits_per_word) +qmr |= t-&gt;bits_per_word &lt;&lt; 10; +else +qmr |= spi-&gt;bits_per_word &lt;&lt; 10; +if (spi-&gt;mode &amp; SPI_CPHA) +qmr |= MCFQSPI_QMR_CPHA; +if (spi-&gt;mode &amp; SPI_CPOL) +qmr |= MCFQSPI_QMR_CPOL; +if (t-&gt;speed_hz) +qmr |= mcfqspi_qmr_baud(t-&gt;speed_hz); +else +qmr |= mcfqspi_qmr_baud(spi-&gt;max_speed_hz); +mcfqspi_wr_qmr(mcfqspi, qmr); + +mcfqspi_cs_select(mcfqspi, spi-&gt;chip_select, cs_high); + +mcfqspi_wr_qir(mcfqspi, MCFQSPI_QIR_SPIFE); +if ((t-&gt;bits_per_word ? t-&gt;bits_per_word : +spi-&gt;bits_per_word) == 8) +mcfqspi_transfer_msg8(mcfqspi, t-&gt;len, t-&gt;tx_buf, +t-&gt;rx_buf); +else +mcfqspi_transfer_msg16(mcfqspi, t-&gt;len / 2, t-&gt;tx_buf, +t-&gt;rx_buf); +mcfqspi_wr_qir(mcfqspi, 0); + +if (t-&gt;delay_usecs) +udelay(t-&gt;delay_usecs); +if (t-&gt;cs_change) { +if (!list_is_last(&amp;t-&gt;transfer_list, &amp;msg-&gt;transfers)) +mcfqspi_cs_deselect(mcfqspi, spi-&gt;chip_select, +cs_high); +} else { +if (list_is_last(&amp;t-&gt;transfer_list, &amp;msg-&gt;transfers)) +mcfqspi_cs_deselect(mcfqspi, spi-&gt;chip_select, +cs_high); } -msg-&gt;status = status; -msg-&gt;complete(msg-&gt;context); - -spin_lock_irqsave(&amp;mcfqspi-&gt;lock, flags); +msg-&gt;actual_length += t-&gt;len; } -spin_unlock_irqrestore(&amp;mcfqspi-&gt;lock, flags); +msg-&gt;status = status; +spi_finalize_current_message(master); + +return status; + } -static int mcfqspi_transfer(struct spi_device *spi, struct spi_message *msg) +static int mcfqspi_prepare_transfer_hw(struct spi_master *master) { -struct mcfqspi *mcfqspi; -struct spi_transfer *xfer; -unsigned long flags; - -mcfqspi = spi_master_get_devdata(spi-&gt;master); - -list_for_each_entry(xfer, &amp;msg-&gt;transfers, transfer_list) { -if (xfer-&gt;bits_per_word &amp;&amp; ((xfer-&gt;bits_per_word &lt; 8) -|| (xfer-&gt;bits_per_word &gt; 16))) { -dev_dbg(&amp;spi-&gt;dev, -"%d bits per word is not supported\n", -xfer-&gt;bits_per_word); -goto fail; -} -if (xfer-&gt;speed_hz) { -u32 real_speed = MCFQSPI_BUSCLK / -mcfqspi_qmr_baud(xfer-&gt;speed_hz); -if (real_speed != xfer-&gt;speed_hz) -dev_dbg(&amp;spi-&gt;dev, -"using speed %d instead of %d\n", -real_speed, xfer-&gt;speed_hz); -} -} -msg-&gt;status = -EINPROGRESS; -msg-&gt;actual_length = 0; +struct mcfqspi *mcfqspi = spi_master_get_devdata(master); -spin_lock_irqsave(&amp;mcfqspi-&gt;lock, flags); -list_add_tail(&amp;msg-&gt;queue, &amp;mcfqspi-&gt;msgq); -queue_work(mcfqspi-&gt;workq, &amp;mcfqspi-&gt;work); -spin_unlock_irqrestore(&amp;mcfqspi-&gt;lock, flags); +pm_runtime_get_sync(mcfqspi-&gt;dev); + +return 0; +} + +static int mcfqspi_unprepare_transfer_hw(struct spi_master *master) +{ +struct mcfqspi *mcfqspi = spi_master_get_devdata(master); + +pm_runtime_put_sync(mcfqspi-&gt;dev); return 0; -fail: -msg-&gt;status = -EINVAL; -return -EINVAL; } static int mcfqspi_setup(struct spi_device *spi) &lt; at &gt;&lt; at &gt; -502,21 +459,10 &lt; at &gt;&lt; at &gt; static int __devinit mcfqspi_probe(struct platform_device *pdev) } clk_enable(mcfqspi-&gt;clk); -mcfqspi-&gt;workq = create_singlethread_workqueue(dev_name(master-&gt;dev.parent)); -if (!mcfqspi-&gt;workq) { -dev_dbg(&amp;pdev-&gt;dev, "create_workqueue failed\n"); -status = -ENOMEM; -goto fail4; -} -INIT_WORK(&amp;mcfqspi-&gt;work, mcfqspi_work); -spin_lock_init(&amp;mcfqspi-&gt;lock); -INIT_LIST_HEAD(&amp;mcfqspi-&gt;msgq); -init_waitqueue_head(&amp;mcfqspi-&gt;waitq); - pdata = pdev-&gt;dev.platform_data; if (!pdata) { dev_dbg(&amp;pdev-&gt;dev, "platform data is missing\n"); -goto fail5; +goto fail4; } master-&gt;bus_num = pdata-&gt;bus_num; master-&gt;num_chipselect = pdata-&gt;num_chipselect; &lt; at &gt;&lt; at &gt; -525,28 +471,33 &lt; at &gt;&lt; at &gt; static int __devinit mcfqspi_probe(struct platform_device *pdev) status = mcfqspi_cs_setup(mcfqspi); if (status) { dev_dbg(&amp;pdev-&gt;dev, "error initializing cs_control\n"); -goto fail5; +goto fail4; } +init_waitqueue_head(&amp;mcfqspi-&gt;waitq); +mcfqspi-&gt;dev = &amp;pdev-&gt;dev; + master-&gt;mode_bits = SPI_CS_HIGH | SPI_CPOL | SPI_CPHA; master-&gt;setup = mcfqspi_setup; -master-&gt;transfer = mcfqspi_transfer; +master-&gt;transfer_one_message = mcfqspi_transfer_one_message; +master-&gt;prepare_transfer_hardware = mcfqspi_prepare_transfer_hw; +master-&gt;unprepare_transfer_hardware = mcfqspi_unprepare_transfer_hw; platform_set_drvdata(pdev, master); status = spi_register_master(master); if (status) { dev_dbg(&amp;pdev-&gt;dev, "spi_register_master failed\n"); -goto fail6; +goto fail5; } +pm_runtime_enable(mcfqspi-&gt;dev); + dev_info(&amp;pdev-&gt;dev, "Coldfire QSPI bus driver\n"); return 0; -fail6: -mcfqspi_cs_teardown(mcfqspi); fail5: -destroy_workqueue(mcfqspi-&gt;workq); +mcfqspi_cs_teardown(mcfqspi); fail4: clk_disable(mcfqspi-&gt;clk); clk_put(mcfqspi-&gt;clk); &lt; at &gt;&lt; at &gt; -570,12 +521,12 &lt; at &gt;&lt; at &gt; static int __devexit mcfqspi_remove(struct platform_device *pdev) struct mcfqspi *mcfqspi = spi_master_get_devdata(master); struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); +pm_runtime_disable(mcfqspi-&gt;dev); /* disable the hardware (set the baud rate to 0) */ mcfqspi_wr_qmr(mcfqspi, MCFQSPI_QMR_MSTR); platform_set_drvdata(pdev, NULL); mcfqspi_cs_teardown(mcfqspi); -destroy_workqueue(mcfqspi-&gt;workq); clk_disable(mcfqspi-&gt;clk); clk_put(mcfqspi-&gt;clk); free_irq(mcfqspi-&gt;irq, mcfqspi); &lt; at &gt;&lt; at &gt; -587,11 +538,13 &lt; at &gt;&lt; at &gt; static int __devexit mcfqspi_remove(struct platform_device *pdev) return 0; } -#ifdef CONFIG_PM - +#ifdef CONFIG_PM_SLEEP static int mcfqspi_suspend(struct device *dev) { -struct mcfqspi *mcfqspi = platform_get_drvdata(to_platform_device(dev)); +struct spi_master *master = spi_master_get(dev_get_drvdata(dev)); +struct mcfqspi *mcfqspi = spi_master_get_devdata(master); + +spi_master_suspend(master); clk_disable(mcfqspi-&gt;clk); &lt; at &gt;&lt; at &gt; -600,27 +553,47 &lt; at &gt;&lt; at &gt; static int mcfqspi_suspend(struct device *dev) static int mcfqspi_resume(struct device *dev) { -struct mcfqspi *mcfqspi = platform_get_drvdata(to_platform_device(dev)); +struct spi_master *master = spi_master_get(dev_get_drvdata(dev)); +struct mcfqspi *mcfqspi = spi_master_get_devdata(master); + +spi_master_resume(master); clk_enable(mcfqspi-&gt;clk); return 0; } +#endif -static struct dev_pm_ops mcfqspi_dev_pm_ops = { -.suspend= mcfqspi_suspend, -.resume= mcfqspi_resume, -}; +#ifdef CONFIG_PM_RUNTIME +static int mcfqspi_runtime_suspend(struct device *dev) +{ +struct mcfqspi *mcfqspi = platform_get_drvdata(to_platform_device(dev)); -#defineMCFQSPI_DEV_PM_OPS(&amp;mcfqspi_dev_pm_ops) -#else -#defineMCFQSPI_DEV_PM_OPSNULL +clk_disable(mcfqspi-&gt;clk); + +return 0; +} + +static int mcfqspi_runtime_resume(struct device *dev) +{ +struct mcfqspi *mcfqspi = platform_get_drvdata(to_platform_device(dev)); + +clk_enable(mcfqspi-&gt;clk); + +return 0; +} #endif +static const struct dev_pm_ops mcfqspi_pm = { +SET_SYSTEM_SLEEP_PM_OPS(mcfqspi_suspend, mcfqspi_resume) +SET_RUNTIME_PM_OPS(mcfqspi_runtime_suspend, mcfqspi_runtime_resume, +NULL) +}; + static struct platform_driver mcfqspi_driver = { .driver.name= DRIVER_NAME, .driver.owner= THIS_MODULE, -.driver.pm= MCFQSPI_DEV_PM_OPS, +.driver.pm= &amp;mcfqspi_pm, .probe= mcfqspi_probe, .remove= __devexit_p(mcfqspi_remove), }; _______________________________________________ uClinux-dev mailing list uClinux-dev&lt; at &gt;uclinux.org http://mailman.uclinux.org/mailman/listinfo/uclinux-dev This message was resent by uclinux-dev&lt; at &gt;uclinux.org To unsubscribe see: http://mailman.uclinux.org/mailman/options/uclinux-dev </pre> Steven King 2012-05-10T16:26:55 http://comments.gmane.org/gmane.linux.uclinux.devel/20387 <pre>From: Greg Ungerer &lt;gerg&lt; at &gt;uclinux.org&gt; The uclinux.c mapping driver uses ioremap_nocache() to map its physical mapping address to a system virtual address. Problem is that the region it is mapping is not device memory. It is ordinary system RAM. On most non-MMU systems this doesn't matter, and the mapping is always a 1:1 translation of the address. But if we want to use the uclinux.c mapping driver on real MMU enabled systems we should be using phys_to_virt() for the translation, since that is really what we are doing. So change it to do that. Signed-off-by: Greg Ungerer &lt;gerg&lt; at &gt;uclinux.org&gt; --- drivers/mtd/maps/uclinux.c | 9 +++------ 1 files changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/mtd/maps/uclinux.c b/drivers/mtd/maps/uclinux.c index cfff454..6d43c75 100644 --- a/drivers/mtd/maps/uclinux.c +++ b/drivers/mtd/maps/uclinux.c &lt; at &gt;&lt; at &gt; -68,10 +68,10 &lt; at &gt;&lt; at &gt; static int __init uclinux_mtd_init(void) printk("uclinux[mtd]: RAM probe address=0x%x size=0x%x\n", (int) mapp-&gt;phys, (int) mapp-&gt;size); -mapp-&gt;virt = ioremap_nocache(mapp-&gt;phys, mapp-&gt;size); +mapp-&gt;virt = phys_to_virt(mapp-&gt;phys); if (mapp-&gt;virt == 0) { -printk("uclinux[mtd]: ioremap_nocache() failed\n"); +printk("uclinux[mtd]: no virtual mapping?\n"); return(-EIO); } &lt; at &gt;&lt; at &gt; -80,7 +80,6 &lt; at &gt;&lt; at &gt; static int __init uclinux_mtd_init(void) mtd = do_map_probe("map_ram", mapp); if (!mtd) { printk("uclinux[mtd]: failed to find a mapping?\n"); -iounmap(mapp-&gt;virt); return(-ENXIO); } &lt; at &gt;&lt; at &gt; -103,10 +102,8 &lt; at &gt;&lt; at &gt; static void __exit uclinux_mtd_cleanup(void) map_destroy(uclinux_ram_mtdinfo); uclinux_ram_mtdinfo = NULL; } -if (uclinux_ram_map.virt) { -iounmap((void *) uclinux_ram_map.virt); +if (uclinux_ram_map.virt) uclinux_ram_map.virt = 0; -} } /****************************************************************************/ </pre> gerg< at >snapgear.com 2012-05-10T06:55:28 http://comments.gmane.org/gmane.linux.uclinux.devel/20376 <pre>Enable Coldfire QSPI support when SPI_COLDFIRE_QSPI is built as a module. This version of the patch combines changes to the config files and device.c and uses IF_ENABLED (thanks to Sam Ravnborg for the suggestion). Signed-off-by: Steven King &lt;sfking&lt; at &gt;fdwdc.com&gt; --- arch/m68k/platform/520x/config.c | 6 +++--- arch/m68k/platform/523x/config.c | 6 +++--- arch/m68k/platform/5249/config.c | 6 +++--- arch/m68k/platform/527x/config.c | 6 +++--- arch/m68k/platform/528x/config.c | 6 +++--- arch/m68k/platform/532x/config.c | 6 +++--- arch/m68k/platform/coldfire/device.c | 6 +++--- 7 files changed, 21 insertions(+), 21 deletions(-) diff --git a/arch/m68k/platform/520x/config.c b/arch/m68k/platform/520x/config.c index 2359478..09df4b8 100644 --- a/arch/m68k/platform/520x/config.c +++ b/arch/m68k/platform/520x/config.c &lt; at &gt;&lt; at &gt; -22,7 +22,7 &lt; at &gt;&lt; at &gt; /***************************************************************************/ -#ifdef CONFIG_SPI_COLDFIRE_QSPI +#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) static void __init m520x_qspi_init(void) { &lt; at &gt;&lt; at &gt; -35,7 +35,7 &lt; at &gt;&lt; at &gt; static void __init m520x_qspi_init(void) writew(par, MCF_GPIO_PAR_UART); } -#endif /* CONFIG_SPI_COLDFIRE_QSPI */ +#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */ /***************************************************************************/ &lt; at &gt;&lt; at &gt; -79,7 +79,7 &lt; at &gt;&lt; at &gt; void __init config_BSP(char *commandp, int size) mach_sched_init = hw_timer_init; m520x_uarts_init(); m520x_fec_init(); -#ifdef CONFIG_SPI_COLDFIRE_QSPI +#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) m520x_qspi_init(); #endif } diff --git a/arch/m68k/platform/523x/config.c b/arch/m68k/platform/523x/config.c index c8b405d..d47dfd8 100644 --- a/arch/m68k/platform/523x/config.c +++ b/arch/m68k/platform/523x/config.c &lt; at &gt;&lt; at &gt; -22,7 +22,7 &lt; at &gt;&lt; at &gt; /***************************************************************************/ -#ifdef CONFIG_SPI_COLDFIRE_QSPI +#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) static void __init m523x_qspi_init(void) { &lt; at &gt;&lt; at &gt; -36,7 +36,7 &lt; at &gt;&lt; at &gt; static void __init m523x_qspi_init(void) writew(par, MCFGPIO_PAR_TIMER); } -#endif /* CONFIG_SPI_COLDFIRE_QSPI */ +#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */ /***************************************************************************/ &lt; at &gt;&lt; at &gt; -58,7 +58,7 &lt; at &gt;&lt; at &gt; void __init config_BSP(char *commandp, int size) { mach_sched_init = hw_timer_init; m523x_fec_init(); -#ifdef CONFIG_SPI_COLDFIRE_QSPI +#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) m523x_qspi_init(); #endif } diff --git a/arch/m68k/platform/5249/config.c b/arch/m68k/platform/5249/config.c index bbf0513..300e729 100644 --- a/arch/m68k/platform/5249/config.c +++ b/arch/m68k/platform/5249/config.c &lt; at &gt;&lt; at &gt; -51,7 +51,7 &lt; at &gt;&lt; at &gt; static struct platform_device *m5249_devices[] __initdata = { /***************************************************************************/ -#ifdef CONFIG_SPI_COLDFIRE_QSPI +#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) static void __init m5249_qspi_init(void) { &lt; at &gt;&lt; at &gt; -61,7 +61,7 &lt; at &gt;&lt; at &gt; static void __init m5249_qspi_init(void) mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI); } -#endif /* CONFIG_SPI_COLDFIRE_QSPI */ +#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */ /***************************************************************************/ &lt; at &gt;&lt; at &gt; -90,7 +90,7 &lt; at &gt;&lt; at &gt; void __init config_BSP(char *commandp, int size) #ifdef CONFIG_M5249C3 m5249_smc91x_init(); #endif -#ifdef CONFIG_SPI_COLDFIRE_QSPI +#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) m5249_qspi_init(); #endif } diff --git a/arch/m68k/platform/527x/config.c b/arch/m68k/platform/527x/config.c index f91a532..b3cb378 100644 --- a/arch/m68k/platform/527x/config.c +++ b/arch/m68k/platform/527x/config.c &lt; at &gt;&lt; at &gt; -23,7 +23,7 &lt; at &gt;&lt; at &gt; /***************************************************************************/ -#ifdef CONFIG_SPI_COLDFIRE_QSPI +#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) static void __init m527x_qspi_init(void) { &lt; at &gt;&lt; at &gt; -42,7 +42,7 &lt; at &gt;&lt; at &gt; static void __init m527x_qspi_init(void) #endif } -#endif /* CONFIG_SPI_COLDFIRE_QSPI */ +#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */ /***************************************************************************/ &lt; at &gt;&lt; at &gt; -90,7 +90,7 &lt; at &gt;&lt; at &gt; void __init config_BSP(char *commandp, int size) mach_sched_init = hw_timer_init; m527x_uarts_init(); m527x_fec_init(); -#ifdef CONFIG_SPI_COLDFIRE_QSPI +#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) m527x_qspi_init(); #endif } diff --git a/arch/m68k/platform/528x/config.c b/arch/m68k/platform/528x/config.c index d449292..c5f11ba 100644 --- a/arch/m68k/platform/528x/config.c +++ b/arch/m68k/platform/528x/config.c &lt; at &gt;&lt; at &gt; -24,7 +24,7 &lt; at &gt;&lt; at &gt; /***************************************************************************/ -#ifdef CONFIG_SPI_COLDFIRE_QSPI +#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) static void __init m528x_qspi_init(void) { &lt; at &gt;&lt; at &gt; -32,7 +32,7 &lt; at &gt;&lt; at &gt; static void __init m528x_qspi_init(void) __raw_writeb(0x07, MCFGPIO_PQSPAR); } -#endif /* CONFIG_SPI_COLDFIRE_QSPI */ +#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */ /***************************************************************************/ &lt; at &gt;&lt; at &gt; -98,7 +98,7 &lt; at &gt;&lt; at &gt; void __init config_BSP(char *commandp, int size) mach_sched_init = hw_timer_init; m528x_uarts_init(); m528x_fec_init(); -#ifdef CONFIG_SPI_COLDFIRE_QSPI +#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) m528x_qspi_init(); #endif } diff --git a/arch/m68k/platform/532x/config.c b/arch/m68k/platform/532x/config.c index 2bec347..37082d0 100644 --- a/arch/m68k/platform/532x/config.c +++ b/arch/m68k/platform/532x/config.c &lt; at &gt;&lt; at &gt; -30,7 +30,7 &lt; at &gt;&lt; at &gt; /***************************************************************************/ -#ifdef CONFIG_SPI_COLDFIRE_QSPI +#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) static void __init m532x_qspi_init(void) { &lt; at &gt;&lt; at &gt; -38,7 +38,7 &lt; at &gt;&lt; at &gt; static void __init m532x_qspi_init(void) writew(0x01f0, MCF_GPIO_PAR_QSPI); } -#endif /* CONFIG_SPI_COLDFIRE_QSPI */ +#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */ /***************************************************************************/ &lt; at &gt;&lt; at &gt; -77,7 +77,7 &lt; at &gt;&lt; at &gt; void __init config_BSP(char *commandp, int size) mach_sched_init = hw_timer_init; m532x_uarts_init(); m532x_fec_init(); -#ifdef CONFIG_SPI_COLDFIRE_QSPI +#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) m532x_qspi_init(); #endif diff --git a/arch/m68k/platform/coldfire/device.c b/arch/m68k/platform/coldfire/device.c index 7af9736..3aa77dd 100644 --- a/arch/m68k/platform/coldfire/device.c +++ b/arch/m68k/platform/coldfire/device.c &lt; at &gt;&lt; at &gt; -121,7 +121,7 &lt; at &gt;&lt; at &gt; static struct platform_device mcf_fec1 = { #endif /* MCFFEC_BASE1 */ #endif /* CONFIG_FEC */ -#ifdef CONFIG_SPI_COLDFIRE_QSPI +#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) /* *The ColdFire QSPI module is an SPI protocol hardware block used *on a number of different ColdFire CPUs. &lt; at &gt;&lt; at &gt; -274,7 +274,7 &lt; at &gt;&lt; at &gt; static struct platform_device mcf_qspi = { .resource= mcf_qspi_resources, .dev.platform_data= &amp;mcf_qspi_data, }; -#endif /* CONFIG_SPI_COLDFIRE_QSPI */ +#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */ static struct platform_device *mcf_devices[] __initdata = { &amp;mcf_uart, &lt; at &gt;&lt; at &gt; -284,7 +284,7 &lt; at &gt;&lt; at &gt; static struct platform_device *mcf_devices[] __initdata = { &amp;mcf_fec1, #endif #endif -#ifdef CONFIG_SPI_COLDFIRE_QSPI +#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) &amp;mcf_qspi, #endif }; _______________________________________________ uClinux-dev mailing list uClinux-dev&lt; at &gt;uclinux.org http://mailman.uclinux.org/mailman/listinfo/uclinux-dev This message was resent by uclinux-dev&lt; at &gt;uclinux.org To unsubscribe see: http://mailman.uclinux.org/mailman/options/uclinux-dev </pre> Steven King 2012-05-06T19:22:53 http://comments.gmane.org/gmane.linux.uclinux.devel/20373 <pre>Hi Greg, The qspi consolidation omitted support for device initialization when the qspi is built as a module. Signed-off-by: Steven King &lt;sfking&lt; at &gt;fdwdc.com&gt; --- arch/m68k/platform/520x/config.c | 6 +++--- arch/m68k/platform/523x/config.c | 6 +++--- arch/m68k/platform/5249/config.c | 6 +++--- arch/m68k/platform/527x/config.c | 6 +++--- arch/m68k/platform/528x/config.c | 6 +++--- arch/m68k/platform/532x/config.c | 6 +++--- 6 files changed, 18 insertions(+), 18 deletions(-) diff --git a/arch/m68k/platform/520x/config.c b/arch/m68k/platform/520x/config.c index 2359478..621fe15 100644 --- a/arch/m68k/platform/520x/config.c +++ b/arch/m68k/platform/520x/config.c &lt; at &gt;&lt; at &gt; -22,7 +22,7 &lt; at &gt;&lt; at &gt; /***************************************************************************/ -#ifdef CONFIG_SPI_COLDFIRE_QSPI +#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) static void __init m520x_qspi_init(void) { &lt; at &gt;&lt; at &gt; -35,7 +35,7 &lt; at &gt;&lt; at &gt; static void __init m520x_qspi_init(void) writew(par, MCF_GPIO_PAR_UART); } -#endif /* CONFIG_SPI_COLDFIRE_QSPI */ +#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */ /***************************************************************************/ &lt; at &gt;&lt; at &gt; -79,7 +79,7 &lt; at &gt;&lt; at &gt; void __init config_BSP(char *commandp, int size) mach_sched_init = hw_timer_init; m520x_uarts_init(); m520x_fec_init(); -#ifdef CONFIG_SPI_COLDFIRE_QSPI +#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) m520x_qspi_init(); #endif } diff --git a/arch/m68k/platform/523x/config.c b/arch/m68k/platform/523x/config.c index c8b405d..bb4cbd5 100644 --- a/arch/m68k/platform/523x/config.c +++ b/arch/m68k/platform/523x/config.c &lt; at &gt;&lt; at &gt; -22,7 +22,7 &lt; at &gt;&lt; at &gt; /***************************************************************************/ -#ifdef CONFIG_SPI_COLDFIRE_QSPI +#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) static void __init m523x_qspi_init(void) { &lt; at &gt;&lt; at &gt; -36,7 +36,7 &lt; at &gt;&lt; at &gt; static void __init m523x_qspi_init(void) writew(par, MCFGPIO_PAR_TIMER); } -#endif /* CONFIG_SPI_COLDFIRE_QSPI */ +#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */ /***************************************************************************/ &lt; at &gt;&lt; at &gt; -58,7 +58,7 &lt; at &gt;&lt; at &gt; void __init config_BSP(char *commandp, int size) { mach_sched_init = hw_timer_init; m523x_fec_init(); -#ifdef CONFIG_SPI_COLDFIRE_QSPI +#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) m523x_qspi_init(); #endif } diff --git a/arch/m68k/platform/5249/config.c b/arch/m68k/platform/5249/config.c index bbf0513..76a69c8 100644 --- a/arch/m68k/platform/5249/config.c +++ b/arch/m68k/platform/5249/config.c &lt; at &gt;&lt; at &gt; -51,7 +51,7 &lt; at &gt;&lt; at &gt; static struct platform_device *m5249_devices[] __initdata = { /***************************************************************************/ -#ifdef CONFIG_SPI_COLDFIRE_QSPI +#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) static void __init m5249_qspi_init(void) { &lt; at &gt;&lt; at &gt; -61,7 +61,7 &lt; at &gt;&lt; at &gt; static void __init m5249_qspi_init(void) mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI); } -#endif /* CONFIG_SPI_COLDFIRE_QSPI */ +#if /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */ /***************************************************************************/ &lt; at &gt;&lt; at &gt; -90,7 +90,7 &lt; at &gt;&lt; at &gt; void __init config_BSP(char *commandp, int size) #ifdef CONFIG_M5249C3 m5249_smc91x_init(); #endif -#ifdef CONFIG_SPI_COLDFIRE_QSPI +#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) m5249_qspi_init(); #endif } diff --git a/arch/m68k/platform/527x/config.c b/arch/m68k/platform/527x/config.c index f91a532..fcb2735 100644 --- a/arch/m68k/platform/527x/config.c +++ b/arch/m68k/platform/527x/config.c &lt; at &gt;&lt; at &gt; -23,7 +23,7 &lt; at &gt;&lt; at &gt; /***************************************************************************/ -#ifdef CONFIG_SPI_COLDFIRE_QSPI +#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) static void __init m527x_qspi_init(void) { &lt; at &gt;&lt; at &gt; -42,7 +42,7 &lt; at &gt;&lt; at &gt; static void __init m527x_qspi_init(void) #endif } -#endif /* CONFIG_SPI_COLDFIRE_QSPI */ +#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */ /***************************************************************************/ &lt; at &gt;&lt; at &gt; -90,7 +90,7 &lt; at &gt;&lt; at &gt; void __init config_BSP(char *commandp, int size) mach_sched_init = hw_timer_init; m527x_uarts_init(); m527x_fec_init(); -#ifdef CONFIG_SPI_COLDFIRE_QSPI +#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) m527x_qspi_init(); #endif } diff --git a/arch/m68k/platform/528x/config.c b/arch/m68k/platform/528x/config.c index d449292..5f82434 100644 --- a/arch/m68k/platform/528x/config.c +++ b/arch/m68k/platform/528x/config.c &lt; at &gt;&lt; at &gt; -24,7 +24,7 &lt; at &gt;&lt; at &gt; /***************************************************************************/ -#ifdef CONFIG_SPI_COLDFIRE_QSPI +#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) static void __init m528x_qspi_init(void) { &lt; at &gt;&lt; at &gt; -32,7 +32,7 &lt; at &gt;&lt; at &gt; static void __init m528x_qspi_init(void) __raw_writeb(0x07, MCFGPIO_PQSPAR); } -#endif /* CONFIG_SPI_COLDFIRE_QSPI */ +#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */ /***************************************************************************/ &lt; at &gt;&lt; at &gt; -98,7 +98,7 &lt; at &gt;&lt; at &gt; void __init config_BSP(char *commandp, int size) mach_sched_init = hw_timer_init; m528x_uarts_init(); m528x_fec_init(); -#ifdef CONFIG_SPI_COLDFIRE_QSPI +#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) m528x_qspi_init(); #endif } diff --git a/arch/m68k/platform/532x/config.c b/arch/m68k/platform/532x/config.c index 2bec347..a4fb70c 100644 --- a/arch/m68k/platform/532x/config.c +++ b/arch/m68k/platform/532x/config.c &lt; at &gt;&lt; at &gt; -30,7 +30,7 &lt; at &gt;&lt; at &gt; /***************************************************************************/ -#ifdef CONFIG_SPI_COLDFIRE_QSPI +#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) static void __init m532x_qspi_init(void) { &lt; at &gt;&lt; at &gt; -38,7 +38,7 &lt; at &gt;&lt; at &gt; static void __init m532x_qspi_init(void) writew(0x01f0, MCF_GPIO_PAR_QSPI); } -#endif /* CONFIG_SPI_COLDFIRE_QSPI */ +#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */ /***************************************************************************/ &lt; at &gt;&lt; at &gt; -77,7 +77,7 &lt; at &gt;&lt; at &gt; void __init config_BSP(char *commandp, int size) mach_sched_init = hw_timer_init; m532x_uarts_init(); m532x_fec_init(); -#ifdef CONFIG_SPI_COLDFIRE_QSPI +#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) m532x_qspi_init(); #endif _______________________________________________ uClinux-dev mailing list uClinux-dev&lt; at &gt;uclinux.org http://mailman.uclinux.org/mailman/listinfo/uclinux-dev This message was resent by uclinux-dev&lt; at &gt;uclinux.org To unsubscribe see: http://mailman.uclinux.org/mailman/options/uclinux-dev </pre> Steven King 2012-05-06T00:34:42 http://comments.gmane.org/gmane.linux.uclinux.devel/20372 <pre>Hi Greg, The qspi consolidation omitted support for device initialization when the qspi is built as a module. Signed-off-by: Steven King &lt;sfking&lt; at &gt;fdwdc.com&gt; --- arch/m68k/platform/coldfire/device.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/m68k/platform/coldfire/device.c b/arch/m68k/platform/coldfire/device.c index 7af9736..a8c50b0 100644 --- a/arch/m68k/platform/coldfire/device.c +++ b/arch/m68k/platform/coldfire/device.c &lt; at &gt;&lt; at &gt; -121,7 +121,7 &lt; at &gt;&lt; at &gt; static struct platform_device mcf_fec1 = { #endif /* MCFFEC_BASE1 */ #endif /* CONFIG_FEC */ -#ifdef CONFIG_SPI_COLDFIRE_QSPI +#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) /* *The ColdFire QSPI module is an SPI protocol hardware block used *on a number of different ColdFire CPUs. &lt; at &gt;&lt; at &gt; -284,7 +284,7 &lt; at &gt;&lt; at &gt; static struct platform_device *mcf_devices[] __initdata = { &amp;mcf_fec1, #endif #endif -#ifdef CONFIG_SPI_COLDFIRE_QSPI +#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) &amp;mcf_qspi, #endif }; _______________________________________________ uClinux-dev mailing list uClinux-dev&lt; at &gt;uclinux.org http://mailman.uclinux.org/mailman/listinfo/uclinux-dev This message was resent by uclinux-dev&lt; at &gt;uclinux.org To unsubscribe see: http://mailman.uclinux.org/mailman/options/uclinux-dev </pre> Steven King 2012-05-05T21:00:24 http://comments.gmane.org/gmane.linux.uclinux.devel/20371 <pre>Hi Greg, The consolidation of the qspi code missed a definition for 528x. Signed-off-by: Steven King &lt;sfking&lt; at &gt;fdwdc.com&gt; --- arch/m68k/include/asm/m528xsim.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h index 569476f..7c92dc4 100644 --- a/arch/m68k/include/asm/m528xsim.h +++ b/arch/m68k/include/asm/m528xsim.h &lt; at &gt;&lt; at &gt; -86,7 +86,7 &lt; at &gt;&lt; at &gt; /* *QSPI module. */ -#defineMCFQSPI_IOBASE(MCF_IPSBAR + 0x340) +#defineMCFQSPI_BASE(MCF_IPSBAR + 0x340) #defineMCFQSPI_SIZE0x40 #defineMCFQSPI_CS0147 _______________________________________________ uClinux-dev mailing list uClinux-dev&lt; at &gt;uclinux.org http://mailman.uclinux.org/mailman/listinfo/uclinux-dev This message was resent by uclinux-dev&lt; at &gt;uclinux.org To unsubscribe see: http://mailman.uclinux.org/mailman/options/uclinux-dev </pre> Steven King 2012-05-05T20:40:44 http://comments.gmane.org/gmane.linux.uclinux.devel/20366 <pre>Hi, I've tried the 'rrdtool' included in the latest uClinux dist (20120401). Creating the database, inserting and fetching values work fine, but when I try to create a .png chart it do one of these two things: 1) Crash the kernel (I'm almost sure it writes in bad memory locations) 2) Give an 'Address Error' trap. Before I start to dig the code to find the issue (if I ever get time to do it), has anyone used this tool in a m68k target? If yes, does it work good? What about in other nommu targets? Thanks, Luis _______________________________________________ uClinux-dev mailing list uClinux-dev&lt; at &gt;uclinux.org http://mailman.uclinux.org/mailman/listinfo/uclinux-dev This message was resent by uclinux-dev&lt; at &gt;uclinux.org To unsubscribe see: http://mailman.uclinux.org/mailman/options/uclinux-dev </pre> Luis Alves 2012-05-04T09:58:03 http://comments.gmane.org/gmane.linux.uclinux.devel/20344 <pre>Hello. I'm writing firmware for a BF526 based device that has to operate in very low power mode for extended periods of time. Prototypes typically sleep for ~30s, keeping code in SDRAM in self-refresh mode, wake for a few seconds to do the necessary processing, then return to sleep. With existing code we can restore operations in 60-100ms. Is anyone aware of any techniques (hacks?) that would allow uClinux to be restored in similar time-frames? Or what reasonable time frames might be for uClinux? Any help greatly appreciated. Jerry. _______________________________________________ uClinux-dev mailing list uClinux-dev&lt; at &gt;uclinux.org http://mailman.uclinux.org/mailman/listinfo/uclinux-dev This message was resent by uclinux-dev&lt; at &gt;uclinux.org To unsubscribe see: http://mailman.uclinux.org/mailman/options/uclinux-dev </pre> Jerry Evans 2012-05-01T13:32:54 http://comments.gmane.org/gmane.linux.uclinux.devel/20343 <pre>Hi. I'd like to try linux on an AT91SAM9G20 (i have a linuxstamp board), with MMU disabled (the Hyok-Sung Choi &amp; Hee-Chul Yun paper demonstrate that it could be possible). All the code seems to be present in the kernel... So i would like to share my experience. (1) I had to make two little changes in the kernel code : - I'm not able to change the REMAP_VECTOR_TO_DRAM. I have submitted the problem to the kbuild mailing list (http://www.spinics.net/lists/linux-kbuild/msg06153.html). - The soc_detect code that init the at91_soc_initdata structure is never called. Later this structure is used unitialized. I'm currently using the joined patch as a workaround. Someone can review it please ? (2) I used to run the module with a "classic system" based on linux + eglibc, and i needed only one toolchain (arm-xxx-linux-gnueabi) for the kernel and the userspace apps. I found that for the nommu case i wasn't able to build the kernel with the userspace toolchain. So I had to build 2 toolchain, based on binutils 2.22, gcc 4.7, uclibc 0.9.33.1 and linux 3.2.14 : - an arm-xxx-eabi toolchain for the kernel - an arm-xxx-uclinux-uclibceabi for the userspace apps Do you confirm that it is not possible to compile the kernel with arm-xxx-uclinux-uclibceabi ? Or, may i have misconfigured the toolchain (i join the toolchain build procedure) ? (3) The arm-xxx-uclinux-uclibceabi with elf2flt seems to produce running bins only if it is build with the uClibc DOPIC not set. Is it required to disable DOPIC ? Moreover, i can't run bins produced with a arm-xxx-linux-uclibceabi toolchain and -Wl,-elf2flt (not uclinux one). Is it the expected behavior ? (4) The elf2flt needs to be updated to be aware of the exidx section, and some reloc types. I join the patch i currently use. Given these observations, i've been able to run a linux with an hello world as the /init process. My next tests will be to run threaded programs, c++ programs, then busybox. Thanks for your attention. Paul. diff -abBruN linux-3.2.14.orig/arch/arm/Kconfig-nommu linux-3.2.14.mod/arch/arm/Kconfig-nommu --- linux-3.2.14.orig/arch/arm/Kconfig-nommu2012-04-02 18:53:31.000000000 +0200 +++ linux-3.2.14.mod/arch/arm/Kconfig-nommu2012-04-15 12:52:05.000000000 +0200 &lt; at &gt;&lt; at &gt; -34,8 +34,7 &lt; at &gt;&lt; at &gt; used instead of the auto-probing which utilizes the register. config REMAP_VECTORS_TO_RAM -bool 'Install vectors to the beginning of RAM' if DRAM_BASE -depends on DRAM_BASE +bool 'Install vectors to the beginning of RAM' help The kernel needs to change the hardware exception vectors. In nommu mode, the hardware exception vectors are normally diff -abBruN linux-3.2.14.orig/arch/arm/mm/nommu.c linux-3.2.14.mod/arch/arm/mm/nommu.c --- linux-3.2.14.orig/arch/arm/mm/nommu.c2012-04-02 18:53:31.000000000 +0200 +++ linux-3.2.14.mod/arch/arm/mm/nommu.c2012-04-16 15:50:47.000000000 +0200 &lt; at &gt;&lt; at &gt; -31,12 +31,23 &lt; at &gt;&lt; at &gt; { } +static void __init devicemaps_init(struct machine_desc *mdesc) +{ +/* + * Ask the machine support to map in the statically mapped devices. + */ +if (mdesc-&gt;map_io) +mdesc-&gt;map_io(); +} + /* * paging_init() sets up the page tables, initialises the zone memory * maps, and sets up the zero page, bad page and bad page tables. */ void __init paging_init(struct machine_desc *mdesc) { +devicemaps_init(mdesc); + bootmem_init(); } From bd2014eb59dea812e396a5f299f53ed03629bdad Mon Sep 17 00:00:00 2001 From: Paul Chavent &lt;pchavent&lt; at &gt;wdcsd911h.onecert.fr&gt; Date: Fri, 27 Apr 2012 10:09:20 +0200 Subject: [PATCH] Update arm support. --- .gitignore | 1 + Makefile.in | 2 +- arm-elf2flt.ld | 221 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ elf2flt.c | 27 +++++++ 4 files changed, 250 insertions(+), 1 deletions(-) create mode 100644 arm-elf2flt.ld diff --git a/.gitignore b/.gitignore index 92ff5f6..e0e0bd5 100644 --- a/.gitignore +++ b/.gitignore &lt; at &gt;&lt; at &gt; -22,3 +22,4 &lt; at &gt;&lt; at &gt; elf2flt elf2flt.ld flthdr ld-elf2flt +ld-elf2flt.sh \ No newline at end of file diff --git a/Makefile.in b/Makefile.in index 81e1afc..f98421e 100644 --- a/Makefile.in +++ b/Makefile.in &lt; at &gt;&lt; at &gt; -42,7 +42,7 &lt; at &gt;&lt; at &gt; ifneq ($(strip $(shell gcc -v 2&gt;&amp;1 | grep "cygwin")),) endif LDFILE= elf2flt.ld -ifeq ($(strip $(CPU)),e1) +ifeq ($(filter-out e1 arm,$(CPU)),) SRC_LDFILE= $(srcdir)/$(CPU)-elf2flt.ld else SRC_LDFILE= elf2flt.ld diff --git a/arm-elf2flt.ld b/arm-elf2flt.ld new file mode 100644 index 0000000..b57999c --- /dev/null +++ b/arm-elf2flt.ld &lt; at &gt;&lt; at &gt; -0,0 +1,221 &lt; at &gt;&lt; at &gt; + +ENTRY (_start) + +MEMORY { +flatmem : ORIGIN = 0x0, LENGTH = 0x1000000 +} + +PHDRS { +text PT_LOAD ; +data PT_LOAD ; +} + +SECTIONS { + +.text 0x0 : { +. = ALIGN(0x4) ; +_stext = . ; +*(.text) +*(.text.*) +*(.gnu.warning) +*(.stub) +*(.gnu.linkonce.t*) +*(.glue_7t) +*(.glue_7) +*(.vfp11_veneer) +*(.jcr) +KEEP (*(.init)) +KEEP (*(.fini)) + +W_RODAT*(.rodata) +W_RODAT*(.rodata1) +W_RODAT*(.rodata.*) +W_RODAT*(.gnu.linkonce.r*) + + /* .ARM.extab name sections containing exception unwinding information */ +*(.ARM.extab* .gnu.linkonce.armextab.*) +/* This is special code area at the end of the normal + text section. It contains a small lookup table at + the start followed by the code pointed to by entries + in the lookup table. */ +. = ALIGN (4) ; +PROVIDE(__ctbp = .); +*(.call_table_data) +*(.call_table_text) +} &gt; flatmem :text + + /* .ARM.exidx name sections containing index entries for section unwinding */ +/* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; +.ARM.exidx : +{ +*(.ARM.exidx* .gnu.linkonce.armexidx.*) +} &gt; flatmem +__exidx_end = .; + +. = ALIGN(0x20) ; +_etext = . ; + +.data : { + . = ALIGN(0x4) ; +_sdata = . ; +__data_start = . ; +data_start = . ; +*(.got.plt) +*(.got) +FILL(0) ; +. = ALIGN(0x20) ; +LONG(-1) +. = ALIGN(0x20) ; +R_RODAT*(.rodata) +R_RODAT*(.rodata1) +R_RODAT*(.rodata.*) +R_RODAT*(.gnu.linkonce.r*) +*(.data) +*(.data1) +*(.data.*) +*(.gnu.linkonce.d*) + +/* Microblaze has .sdata and .sbss (small bss). They must + be contiguous, so please don't move any of this. JW */ +_ssrw = . ; +*(.sdata) +*(.sdata.*) +*(.sbss)/* Don't move this! */ +*(.gnu.linkonce.sb*) +_essrw = . ; + +_ssrw_size = _essrw - _ssrw; +PROVIDE(_SDA_BASE_ = _ssrw + (_ssrw_size / 2)); + +*(.gnu.linkonce.s.*) +*(__libc_atexit) +*(__libc_subinit) +*(__libc_subfreeres) + +/* microblaze-specific read-only small data area + and associated locating symbols */ +_ssro = . ; +*(.sdata2) +_essro = . ; +_ssro_size = _essro - _ssro; +PROVIDE(_SDA2_BASE_ = _ssro + (_ssro_size / 2)); + +. = ALIGN(4) ; +TOR:__CTOR_LIST__ = .; +TOR:LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2) +SINGLE_LINK:/* gcc uses crtbegin.o to find the start of +SINGLE_LINK: the constructors, so we make sure it is +SINGLE_LINK: first. Because this is a wildcard, it +SINGLE_LINK: doesn't matter if the user does not +SINGLE_LINK: actually link against crtbegin.o; the +SINGLE_LINK: linker won't look for a file to match a +SINGLE_LINK: wildcard. The wildcard also means that it +SINGLE_LINK: doesn't matter which directory crtbegin.o +SINGLE_LINK: is in. */ +SINGLE_LINK:KEEP (*crtbegin*.o(.ctors)) +SINGLE_LINK:/* We don't want to include the .ctor section from +SINGLE_LINK: from the crtend.o file until after the sorted ctors. +SINGLE_LINK: The .ctor section from the crtend file contains the +SINGLE_LINK: end of ctors marker and it must be last */ +SINGLE_LINK:KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors)) +SINGLE_LINK:KEEP (*(SORT(.ctors.*))) +KEEP (*(.ctors)) +TOR:LONG(0) +TOR:__CTOR_END__ = .; +TOR:__DTOR_LIST__ = .; +TOR:LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2) +SINGLE_LINK:KEEP (*crtbegin*.o(.dtors)) +SINGLE_LINK:KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors)) +SINGLE_LINK:KEEP (*(SORT(.dtors.*))) +KEEP (*(.dtors)) +TOR:LONG(0) +TOR:__DTOR_END__ = .; + +PROVIDE (__preinit_array_start = .); +KEEP (*(.preinit_array)) +PROVIDE (__preinit_array_end = .); + +PROVIDE (__init_array_start = .); +KEEP (*(SORT(.init_array.*))) +KEEP (*(.init_array)) +PROVIDE (__init_array_end = .); + +PROVIDE (__fini_array_start = .); +KEEP (*(.fini_array)) +KEEP (*(SORT(.fini_array.*))) +PROVIDE (__fini_array_end = .); +} &gt; flatmem :data + +.note.ABI-tag : { *(.note.ABI-tag) } &gt; flatmem +.eh_frame_hdr : { *(.eh_frame_hdr) } &gt; flatmem +.eh_frame : { KEEP(*(.eh_frame)) } &gt; flatmem +.gcc_except_table : { +KEEP(*(.gcc_except_table)) +KEEP(*(.gcc_except_table.*)) +} &gt;flatmem + +. = ALIGN(0x10) ; +_edata = . ; + +.bss : { +. = ALIGN(0x4) ; +_sbss = ALIGN(0x4) ; +__bss_start = . ; +*(.dynsbss) +*(.sbss) +*(.sbss.*) +*(.scommon) +*(.dynbss) +*(.bss) +*(.bss.*) +*(.bss*) +*(.gnu.linkonce.b*) +*(COMMON) +. = ALIGN(0x10) ; +_ebss = . ; +_end = . ; +end = . ; +} &gt; flatmem + +.stack : { +. = ALIGN(0x4); +_stack_start = .; +} + +.junk 0 : { *(.rel*) *(.rela*) } +/DISCARD/ : { *(.note.GNU-stack) } +/* Stabs debugging sections. */ +.stab 0 : { *(.stab) } +.stabstr 0 : { *(.stabstr) } +.stab.excl 0 : { *(.stab.excl) } +.stab.exclstr 0 : { *(.stab.exclstr) } +.stab.index 0 : { *(.stab.index) } +.stab.indexstr 0 : { *(.stab.indexstr) } +.comment 0 : { *(.comment) } +/* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ +/* DWARF 1 */ +.debug 0 : { *(.debug) } +.line 0 : { *(.line) } +/* GNU DWARF 1 extensions */ +.debug_srcinfo 0 : { *(.debug_srcinfo) } +.debug_sfnames 0 : { *(.debug_sfnames) } +/* DWARF 1.1 and DWARF 2 */ +.debug_aranges 0 : { *(.debug_aranges) } +.debug_pubnames 0 : { *(.debug_pubnames) } +/* DWARF 2 */ +.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } +.debug_abbrev 0 : { *(.debug_abbrev) } +.debug_line 0 : { *(.debug_line) } +.debug_frame 0 : { *(.debug_frame) } +.debug_str 0 : { *(.debug_str) } +.debug_loc 0 : { *(.debug_loc) } +.debug_macinfo 0 : { *(.debug_macinfo) } +/* SGI/MIPS DWARF 2 extensions */ +.debug_weaknames 0 : { *(.debug_weaknames) } +.debug_funcnames 0 : { *(.debug_funcnames) } +.debug_typenames 0 : { *(.debug_typenames) } +.debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/elf2flt.c b/elf2flt.c index 2fea9b5..1a7ef88 100644 --- a/elf2flt.c +++ b/elf2flt.c &lt; at &gt;&lt; at &gt; -54,6 +54,8 &lt; at &gt;&lt; at &gt; const char *elf2flt_progname; #if defined(TARGET_h8300) #include &lt;elf/h8.h&gt; /* TARGET_* ELF support for the BFD library */ +#elif defined(TARGET_arm) +#include "elf/arm.h" #elif defined(__CYGWIN__) || defined(__MINGW32__) || defined(TARGET_nios) || defined(TARGET_nios2) #include "cygwin-elf.h"/* Cygwin uses a local copy */ #elif defined(TARGET_microblaze) &lt; at &gt;&lt; at &gt; -639,12 +641,16 &lt; at &gt;&lt; at &gt; dump_symbols(symbols, number_of_symbols); relocation_needed = 1; break; case R_ARM_REL32: +case R_ARM_JUMP24: +case R_ARM_CALL: case R_ARM_THM_PC11: case R_ARM_THM_PC22: case R_ARM_PC24: case R_ARM_PLT32: case R_ARM_GOTPC: case R_ARM_GOT32: +case R_ARM_PREL31: +case R_ARM_NONE: relocation_needed = 0; break; default: &lt; at &gt;&lt; at &gt; -1702,6 +1708,27 &lt; at &gt;&lt; at &gt; int main(int argc, char *argv[]) } } + if (verbose) { + printf(" verbose = %d\n" + " load_to_ram = %d\n" + " ktrace = %d\n" + " docompress = %d\n" + " pfile = \"%s\"\n" + " ofile = \"%s\"\n" + " use_resolved = %d\n" + " stack = %d\n" + " rel_file = \"%s\\n", + verbose , + load_to_ram , + ktrace , + docompress , + pfile , + ofile , + use_resolved, + stack , + rel_file ); + } + /* * if neither the -r or -p options was given, default to * a RAM load as that is the only option that makes sense. </pre> Paul Chavent 2012-05-01T15:24:48 http://comments.gmane.org/gmane.linux.uclinux.devel/20342 <pre>I'm writing firmware for a BF526 based device that has to operate in very low power mode for extended periods of time. Prototypes typically sleep for ~30s, keeping code in SDRAM in self-refresh mode, wake for a few seconds to do the necessary processing, then return to sleep. With existing code we can restore operations in 60-100ms. Is anyone aware of any techniques (hacks?) that would allow uClinux to be restored in similar time-frames? Or what reasonable time frames might be for uClinux? Any help greatly appreciated. Jerry. _______________________________________________ uClinux-dev mailing list uClinux-dev&lt; at &gt;uclinux.org http://mailman.uclinux.org/mailman/listinfo/uclinux-dev This message was resent by uclinux-dev&lt; at &gt;uclinux.org To unsubscribe see: http://mailman.uclinux.org/mailman/options/uclinux-dev </pre> g4< at >novadsp.com 2012-05-01T14:12:53 http://comments.gmane.org/gmane.linux.uclinux.devel/20322 <pre>Hi, something seems to be wrong with this list. I am subscribed for months now an didn't get anything except a monthly (?) password reminder. I guess I set this behaviour in my profile. But now I seem to get everything. Did you change something lately? Martin _______________________________________________ uClinux-dev mailing list uClinux-dev&lt; at &gt;uclinux.org http://mailman.uclinux.org/mailman/listinfo/uclinux-dev This message was resent by uclinux-dev&lt; at &gt;uclinux.org To unsubscribe see: http://mailman.uclinux.org/mailman/options/uclinux-dev</pre> Martin Mensch 2012-04-26T18:59:26 http://comments.gmane.org/gmane.linux.uclinux.devel/20317 <pre>From: Greg Ungerer &lt;gerg&lt; at &gt;uclinux.org&gt; We have very large tables in the ColdFire CPU GPIO setup code that essentially boil down to 2 distinct types of GPIO pin initiaization. Using 2 macros we can reduce these large tables to at most a dozen lines of setup code, and in quite a few cases a single table entry. Introduce these 2 macros into the existing mcfgpio.h header. Signed-off-by: Greg Ungerer &lt;gerg&lt; at &gt;uclinux.org&gt; Acked-by: Steven King &lt;sfking&lt; at &gt;fdwdc.com&gt; --- arch/m68k/include/asm/mcfgpio.h | 54 +++++++++++++++++++++++++++++++++++++++ 1 files changed, 54 insertions(+), 0 deletions(-) diff --git a/arch/m68k/include/asm/mcfgpio.h b/arch/m68k/include/asm/mcfgpio.h index ee5e4cc..cd28830 100644 --- a/arch/m68k/include/asm/mcfgpio.h +++ b/arch/m68k/include/asm/mcfgpio.h &lt; at &gt;&lt; at &gt; -37,4 +37,58 &lt; at &gt;&lt; at &gt; void mcf_gpio_set_value_fast(struct gpio_chip *, unsigned, int); int mcf_gpio_request(struct gpio_chip *, unsigned); void mcf_gpio_free(struct gpio_chip *, unsigned); +/* + *Define macros to ease the pain of setting up the GPIO tables. There + *is two cases we need to deal with here, they cover all currently + *available ColdFire GPIO hardware. There is of course minor differences + *in the layout and number of bits in each ColdFire part, but the macros + *take all that in. + * + *Firstly is the conventional GPIO registers where we toggle individual + *bits in a register, preserving the other bits in the register. For + *lack of a better term I have called this the slow method. + */ +#defineMCFGPS(mlabel, mbase, mngpio, mpddr, mpodr, mppdr) \ +{ \ +.gpio_chip= { \ +.label= #mlabel, \ +.request= mcf_gpio_request, \ +.free= mcf_gpio_free, \ +.direction_input= mcf_gpio_direction_input, \ +.direction_output= mcf_gpio_direction_output,\ +.get= mcf_gpio_get_value, \ +.set= mcf_gpio_set_value, \ +.base= mbase, \ +.ngpio= mngpio, \ +}, \ +.pddr= (void __iomem *) mpddr, \ +.podr= (void __iomem *) mpodr, \ +.ppdr= (void __iomem *) mppdr, \ +} + +/* + *Secondly is the faster case, where we have set and clear registers + *that allow us to set or clear a bit with a single write, not having + *to worry about preserving other bits. + */ +#defineMCFGPF(mlabel, mbase, mngpio) \ +{ \ +.gpio_chip= { \ +.label= #mlabel, \ +.request= mcf_gpio_request, \ +.free= mcf_gpio_free, \ +.direction_input= mcf_gpio_direction_input, \ +.direction_output= mcf_gpio_direction_output,\ +.get= mcf_gpio_get_value, \ +.set= mcf_gpio_set_value_fast, \ +.base= mbase, \ +.ngpio= mngpio, \ +}, \ +.pddr= (void __iomem *) MCFGPIO_PDDR_##mlabel, \ +.podr= (void __iomem *) MCFGPIO_PODR_##mlabel, \ +.ppdr= (void __iomem *) MCFGPIO_PPDSDR_##mlabel, \ +.setr= (void __iomem *) MCFGPIO_PPDSDR_##mlabel, \ +.clrr= (void __iomem *) MCFGPIO_PCLRR_##mlabel, \ +} + #endif </pre> gerg< at >snapgear.com 2012-04-26T13:14:51 Search the mailing list at Gmane query http://search.gmane.org/?group=$group=gmane.linux.uclinux.devel