gmane.linux.serial

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[PATCH 0/2] serial: sh-sci: HSCIF support

Simon Horman — 2013-06-17T02:42:12

Hi Greg, Hi All,

this short series adds HSCIF support to the sh-sci driver
and enhances the r8a7790 SoC to not use external clocks for SCIF.

I have included these two patches in a single series as the second
patch has a build-time dependency on the first.

Greg, would it be possible for you to review at least the first patch and
if it is ok either:
* Ack the first patch so I can merge it through the renesas tree or;
* Take both patches, I have supplied Acks.

In the case of the latter I can supply a pull request if you like.

Ulrich Hecht (2):
  serial: sh-sci: HSCIF support
  ARM: shmobile: r8a7790: don't use external clock for SCIFs

 arch/arm/mach-shmobile/setup-r8a7790.c |   16 ++++-
 drivers/tty/serial/sh-sci.c            |  102 +++++++++++++++++++++++++++++---
 include/linux/serial_sci.h             |   12 +++-
 include/uapi/linux/serial_core.h       |    3 +
 4 files changed, 120 insertions(+), 13 deletions(-)

[PATCH] serial: mfd: Add sysrq support

Feng Tang — 2013-06-14T10:11:17

When using MFD HSU based console, sometime we need the sysrq function
to help debugging kernel. The sysrq code is basically there, this
patch just simply enable it.

Signed-off-by: Feng Tang <feng.tang< at >intel.com>
---
 drivers/tty/serial/mfd.c |    4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/tty/serial/mfd.c b/drivers/tty/serial/mfd.c
index 5f4765a..e266eca 100644
--- a/drivers/tty/serial/mfd.c
+++ b/drivers/tty/serial/mfd.c
< at >< at > -21,6 +21,10 < at >< at >
  *    be triggered
  */
 
+#if defined(CONFIG_SERIAL_MFD_HSU_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
+#define SUPPORT_SYSRQ
+#endif
+
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/console.h>

API to flush rx fifo?

Grant Edwards — 2013-06-12T20:03:50

I see the uart_ops.flush_buffer method which is used to flush the
UART's tx fifo (presumably when the user calls tcflush(TCOFLUSH)).

How does the rx fifo get flushed when the user calls tcflush(TCIFLUSH)?

[GIT PATCH] TTY/Serial fixes for 3.10-rc5

Greg KH — 2013-06-06T17:58:05

The following changes since commit e4aa937ec75df0eea0bee03bffa3303ad36c986b:

  Linux 3.10-rc3 (2013-05-26 16:00:47 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty.git/ tags/tty-3.10-rc4

for you to fetch changes up to 317a68427d4b0a302ecff252fd83a00557947db8:

  Revert "serial: 8250: Make SERIAL_8250_RUNTIME_UARTS work correctly" (2013-06-03 10:08:28 -0700)

----------------------------------------------------------------
TTY/Serial driver fixes for 3.10-rc4

Here are some small bugfixes, and one revert, of serial driver issues
that have been reported.

Signed-off-by: Greg Kroah-Hartman <gregkh< at >linuxfoundation.org>

----------------------------------------------------------------
Chander Kashyap (1):
      serial: samsung: enable clock before clearing pending interrupts during init

Kyle McMartin (1):
      Revert "serial: 8250: Make SERIAL_8250_RUNTIME_UARTS work correctly"

Lucas Stach (1):
      serial/imx: disable hardware flow control at startup

 drivers/tty/serial/8250/8250_core.c | 14 +++++++-------
 drivers/tty/serial/imx.c            |  2 ++
 drivers/tty/serial/samsung.c        | 13 +++++++++++++
 3 files changed, 22 insertions(+), 7 deletions(-)
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[PATCH 01/13] ARM: Exynos: initialize l2x0 cache controller only for cortex-a9 based SoCs

Chander Kashyap — 2013-06-06T11:01:15

Only cortex-a9 based Exynos SoCs have l2x0 cache controller. Hence instead of
checking for every SoC with soc_is_xxx, just check for cpu part number and
initialize the cache controller for cortex-a9 based SoCs.

Signed-off-by: Chander Kashyap <chander.kashyap< at >linaro.org>
---
 arch/arm/mach-exynos/common.c |    3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 8ce2db4..bad000e 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
< at >< at > -35,6 +35,7 < at >< at >
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 #include <asm/cacheflush.h>
+#include <asm/cputype.h>
 
 #include <mach/regs-irq.h>
 #include <mach/regs-pmu.h>
< at >< at > -520,7 +521,7 < at >< at > static int __init exynos4_l2x0_cache_init(void)
 {
 int ret;
 
-if (soc_is_exynos5250() || soc_is_exynos5440())
+if (read_cpuid_part_number() != ARM_CPU_PART_CORTEX_A9)
 return 0;
 
 ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);

[PATCH] tty/serial/sirf: fix error propagation in sirfsoc_uart_probe()

Alexey Khoroshilov — 2013-06-05T21:28:12

If pinctrl_get_select_default() fails, sirfsoc_uart_probe()
returns IS_ERR(result) instead of PTR_ERR(result).

Found by Linux Driver Verification project (linuxtesting.org).

Signed-off-by: Alexey Khoroshilov <khoroshilov< at >ispras.ru>
---
 drivers/tty/serial/sirfsoc_uart.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/tty/serial/sirfsoc_uart.c b/drivers/tty/serial/sirfsoc_uart.c
index 03465b6..1fd564b 100644
--- a/drivers/tty/serial/sirfsoc_uart.c
+++ b/drivers/tty/serial/sirfsoc_uart.c
< at >< at > -687,9 +687,10 < at >< at > int sirfsoc_uart_probe(struct platform_device *pdev)
 
 if (sirfport->hw_flow_ctrl) {
 sirfport->p = pinctrl_get_select_default(&pdev->dev);
-ret = IS_ERR(sirfport->p);
-if (ret)
+if (IS_ERR(sirfport->p)) {
+ret = PTR_ERR(sirfport->p);
 goto err;
+}
 }
 
 sirfport->clk = clk_get(&pdev->dev, NULL);

[PATCH v3 1/3] serial: imx: Fix warning when !CONFIG_SERIAL_IMX_CONSOLE

Fabio Estevam — 2013-06-05T03:58:46

From: Fabio Estevam <fabio.estevam< at >freescale.com>

When CONFIG_SERIAL_IMX_CONSOLE is not selected the following build warnings
appear:

drivers/tty/serial/imx.c:274:13: warning: 'imx_port_ucrs_save' defined but not used [-Wunused-function]
drivers/tty/serial/imx.c:283:13: warning: 'imx_port_ucrs_restore' defined but not used [-Wunused-function]

imx_port_ucrs_save() and imx_port_ucrs_restore() are only used when 
CONFIG_CONSOLE_POLL or CONFIG_SERIAL_IMX_CONSOLE are selected, so protect these
functions declaration with a proper ifdef.

Signed-off-by: Fabio Estevam <fabio.estevam< at >freescale.com>
---
Changes since v2:
- Do the same as in v1
 drivers/tty/serial/imx.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
index a07e94f..981749f 100644
--- a/drivers/tty/serial/imx.c
+++ b/drivers/tty/serial/imx.c
< at >< at > -272,6 +272,7 < at >< at > static inline int is_imx21_uart(struct imx_port *sport)
 /*
  * Save and restore functions for UCR1, UCR2 and UCR3 registers
  */
+#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_IMX_CONSOLE)
 static void imx_port_ucrs_save(struct uart_port *port,
        struct imx_port_ucrs *ucr)
 {
< at >< at > -289,6 +290,7 < at >< at > static void imx_port_ucrs_restore(struct uart_port *port,
 writel(ucr->ucr2, port->membase + UCR2);
 writel(ucr->ucr3, port->membase + UCR3);
 }
+#endif
 
 /*
  * Handle any change of modem status signal since we were last called.

[PATCH -next] serial: omap: fix potential NULL pointer dereference in serial_omap_runtime_suspend()

Wei Yongjun — 2013-06-05T02:04:49

From: Wei Yongjun <yongjun_wei< at >trendmicro.com.cn>

The dereference to 'up' should be moved below the NULL test.
Introduced by commit ddd85e225c8885b5e4419b0499ab27100e7c366a
(serial: omap: prevent runtime PM for "no_console_suspend")

Signed-off-by: Wei Yongjun <yongjun_wei< at >trendmicro.com.cn>
---
 drivers/tty/serial/omap-serial.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index 1aaeca8..156b5aa 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
< at >< at > -1613,6 +1613,9 < at >< at > static int serial_omap_runtime_suspend(struct device *dev)
 struct uart_omap_port *up = dev_get_drvdata(dev);
 struct omap_uart_port_info *pdata = dev->platform_data;
 
+if (!up)
+return -EINVAL;
+
 /*
 * When using 'no_console_suspend', the console UART must not be
 * suspended. Since driver suspend is managed by runtime suspend,
< at >< at > -1623,9 +1626,6 < at >< at > static int serial_omap_runtime_suspend(struct device *dev)
     uart_console(&up->port))
 return -EBUSY;
 
-if (!up)
-return -EINVAL;
-
 if (!pdata)
 return 0;
 

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[PATCH v2 1/2] serial: imx: Remove SERIAL_IMX_CONSOLE

Fabio Estevam — 2013-06-04T17:08:37

When CONFIG_SERIAL_IMX_CONSOLE is not selected the following build warnings
appear:

drivers/tty/serial/imx.c:274:13: warning: 'imx_port_ucrs_save' defined but not used [-Wunused-function]
drivers/tty/serial/imx.c:283:13: warning: 'imx_port_ucrs_restore' defined but not used [-Wunused-function]

Instead of fixing the warning by protecting mx_port_ucrs_save() and 
imx_port_ucrs_restore() with an "ifdef", let's get rid of the SERIAL_IMX_CONSOLE
option and make the console support always present.

While at it, change the CPU vendor name to Freescale. 

Suggested-by: Sascha Hauer <s.hauer< at >pengutronix.de>
Signed-off-by: Fabio Estevam <fabio.estevam< at >freescale.com>
---
Changes since v1:
- Fix the warning by removing SERIAL_IMX_CONSOLE

 drivers/tty/serial/Kconfig | 18 ++----------------
 drivers/tty/serial/imx.c   | 10 ++--------
 2 files changed, 4 insertions(+), 24 deletions(-)

diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 7e7006f..a9ae1cd 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
< at >< at > -554,26 +554,12 < at >< at > config SERIAL_IMX
 bool "IMX serial port support"
 depends on ARCH_MXC
 select SERIAL_CORE
+select SERIAL_CORE_CONSOLE
 select RATIONAL
 help
-  If you have a machine based on a Motorola IMX CPU you
+  If you have a machine based on a Freescale IMX CPU you
   can enable its onboard serial port by enabling this option.
 
-config SERIAL_IMX_CONSOLE
-bool "Console on IMX serial port"
-depends on SERIAL_IMX
-select SERIAL_CORE_CONSOLE
-help
-  If you have enabled the serial port on the Motorola IMX
-  CPU you can make it the console by answering Y to this option.
-
-  Even if you say Y here, the currently visible virtual console
-  (/dev/tty0) will still be used as the system console by default, but
-  you can alter that using a kernel command line option such as
-  "console=ttySA0". (Try "man bootparam" or see the documentation of
-  your boot loader (lilo or loadlin) about how to pass options to the
-  kernel at boot time.)
-
 config SERIAL_UARTLITE
 tristate "Xilinx uartlite serial port support"
 depends on PPC32 || MICROBLAZE || MFD_TIMBERDALE
diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
index a07e94f..d0fcd5e 100644
--- a/drivers/tty/serial/imx.c
+++ b/drivers/tty/serial/imx.c
< at >< at > -27,7 +27,7 < at >< at >
  * Added hardware handshake
  */
 
-#if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
+#if defined(CONFIG_MAGIC_SYSRQ)
 #define SUPPORT_SYSRQ
 #endif
 
< at >< at > -1211,7 +1211,6 < at >< at > static struct uart_ops imx_pops = {
 
 static struct imx_port *imx_ports[UART_NR];
 
-#ifdef CONFIG_SERIAL_IMX_CONSOLE
 static void imx_console_putchar(struct uart_port *port, int ch)
 {
 struct imx_port *sport = (struct imx_port *)port;
< at >< at > -1374,11 +1373,6 < at >< at > static struct console imx_console = {
 .data= &imx_reg,
 };
 
-#define IMX_CONSOLE&imx_console
-#else
-#define IMX_CONSOLENULL
-#endif
-
 static struct uart_driver imx_reg = {
 .owner          = THIS_MODULE,
 .driver_name    = DRIVER_NAME,
< at >< at > -1386,7 +1380,7 < at >< at > static struct uart_driver imx_reg = {
 .major          = SERIAL_IMX_MAJOR,
 .minor          = MINOR_START,
 .nr             = ARRAY_SIZE(imx_ports),
-.cons           = IMX_CONSOLE,
+.cons           = &imx_console,
 };
 
 static int serial_imx_suspend(struct platform_device *dev, pm_message_t state)

[PATCH] tty: serial: Enable uartlite for ARM zynq

Michal Simek — 2013-06-04T12:20:43

Enable it in Kconfig.

Signed-off-by: Michal Simek <michal.simek< at >xilinx.com>
---
 drivers/tty/serial/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 7e7006f..64250b1 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
< at >< at > -576,7 +576,7 < at >< at > config SERIAL_IMX_CONSOLE

 config SERIAL_UARTLITE
 tristate "Xilinx uartlite serial port support"
-depends on PPC32 || MICROBLAZE || MFD_TIMBERDALE
+depends on PPC32 || MICROBLAZE || MFD_TIMBERDALE || ARCH_ZYNQ
 select SERIAL_CORE
 help
   Say Y here if you want to use the Xilinx uartlite serial controller.
--
1.8.2.3

[PATCH 1/3] serial: imx: Fix warning when !CONFIG_SERIAL_IMX_CONSOLE

Fabio Estevam — 2013-06-04T02:51:46

From: Fabio Estevam <fabio.estevam< at >freescale.com>

When CONFIG_SERIAL_IMX_CONSOLE is not selected the following build warnings
appear:

drivers/tty/serial/imx.c:274:13: warning: 'imx_port_ucrs_save' defined but not used [-Wunused-function]
drivers/tty/serial/imx.c:283:13: warning: 'imx_port_ucrs_restore' defined but not used [-Wunused-function]

imx_port_ucrs_save() and imx_port_ucrs_restore() are only used when 
CONFIG_CONSOLE_POLL or CONFIG_SERIAL_IMX_CONSOLE are selected, so protect these
functions declaration with a proper ifdef.

Signed-off-by: Fabio Estevam <fabio.estevam< at >freescale.com>
---
 drivers/tty/serial/imx.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
index 72bc1db..90eba78 100644
--- a/drivers/tty/serial/imx.c
+++ b/drivers/tty/serial/imx.c
< at >< at > -271,6 +271,7 < at >< at > static inline int is_imx21_uart(struct imx_port *sport)
 /*
  * Save and restore functions for UCR1, UCR2 and UCR3 registers
  */
+#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_IMX_CONSOLE)
 static void imx_port_ucrs_save(struct uart_port *port,
        struct imx_port_ucrs *ucr)
 {
< at >< at > -288,6 +289,7 < at >< at > static void imx_port_ucrs_restore(struct uart_port *port,
 writel(ucr->ucr2, port->membase + UCR2);
 writel(ucr->ucr3, port->membase + UCR3);
 }
+#endif
 
 /*
  * Handle any change of modem status signal since we were last called.

[PATCH V2] serial: imx: enable the clocks only when the uart is used

Huang Shijie — 2013-06-04T01:59:33

Current code opens the clocks when the uart driver is probed.
This will wastes some power if several uarts are enabled, but not really
used.

So close these clocks for uart, and enable the clocks only when
the uart is used.

Signed-off-by: Huang Shijie <b32955< at >freescale.com>
---
v1 --> v2:
check the return value of clk_prepare_enable().
---
 drivers/tty/serial/imx.c |   17 ++++++++++++++---
 1 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
index 72bc1db..7cc4810 100644
--- a/drivers/tty/serial/imx.c
+++ b/drivers/tty/serial/imx.c
< at >< at > -699,6 +699,14 < at >< at > static int imx_startup(struct uart_port *port)
 int retval;
 unsigned long flags, temp;
 
+retval = clk_prepare_enable(sport->clk_per);
+if (retval)
+goto error_out1;
+
+retval = clk_prepare_enable(sport->clk_ipg);
+if (retval)
+goto error_out1;
+
 imx_setup_ufcr(sport, 0);
 
 /* disable the DREN bit (Data Ready interrupt enable) before
< at >< at > -884,6 +892,9 < at >< at > static void imx_shutdown(struct uart_port *port)
 
 writel(temp, sport->port.membase + UCR1);
 spin_unlock_irqrestore(&sport->port.lock, flags);
+
+clk_disable_unprepare(sport->clk_per);
+clk_disable_unprepare(sport->clk_ipg);
 }
 
 static void
< at >< at > -1557,6 +1568,9 < at >< at > static int serial_imx_probe(struct platform_device *pdev)
 goto deinit;
 platform_set_drvdata(pdev, sport);
 
+clk_disable_unprepare(sport->clk_per);
+clk_disable_unprepare(sport->clk_ipg);
+
 return 0;
 deinit:
 if (pdata && pdata->exit)
< at >< at > -1578,9 +1592,6 < at >< at > static int serial_imx_remove(struct platform_device *pdev)
 
 uart_remove_one_port(&imx_reg, &sport->port);
 
-clk_disable_unprepare(sport->clk_per);
-clk_disable_unprepare(sport->clk_ipg);
-
 if (pdata && pdata->exit)
 pdata->exit(pdev);

[PATCH v6] tty: serial: add Freescale lpuart driver support

Jingchang Lu — 2013-06-04T01:27:50

Add Freescale lpuart driver support. The lpuart device
can be found on Vybrid VF610 and Layerscape LS-1 SoCs.

Signed-off-by: Jingchang Lu <b35083< at >freescale.com>
---
changes in v6:
  Enable being built as a module support.

changes in v5:
 Coding style fix, remove redundant code.
 Checking clk_prepare_enable return value.
 Using devm_ioremap_resource instead of devm_request_and_ioremap.

changes in v4:
 Change Vybrid VF610 SoC compatible string to "fsl,vf610-lpuart"

changes in v3:
 Use general driver name lpuart instead of mvf for further share between SoCs.
 Add bind doc in Documentation/devicetree/bindings/tty/serial.
 Remove unused #include header lines and clean up code.

changes in v2:
 Remove unused variables and clean up the code.

 .../devicetree/bindings/tty/serial/fsl-lpuart.txt  |  14 +
 drivers/tty/serial/Kconfig                         |  14 +
 drivers/tty/serial/Makefile                        |   1 +
 drivers/tty/serial/fsl_lpuart.c                    | 873 +++++++++++++++++++++
 include/uapi/linux/serial_core.h                   |   3 +
 5 files changed, 905 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/tty/serial/fsl-lpuart.txt
 create mode 100644 drivers/tty/serial/fsl_lpuart.c

diff --git a/Documentation/devicetree/bindings/tty/serial/fsl-lpuart.txt b/Documentation/devicetree/bindings/tty/serial/fsl-lpuart.txt
new file mode 100644
index 0000000..6fd1dd1
--- /dev/null
+++ b/Documentation/devicetree/bindings/tty/serial/fsl-lpuart.txt
< at >< at > -0,0 +1,14 < at >< at >
+* Freescale low power universal asynchronous receiver/transmitter (lpuart)
+
+Required properties:
+- compatible : Should be "fsl,<soc>-lpuart"
+- reg : Address and length of the register set for the device
+- interrupts : Should contain uart interrupt
+
+Example:
+
+uart0: serial< at >40027000 {
+       compatible = "fsl,vf610-lpuart";
+       reg = <0x40027000 0x1000>;
+       interrupts = <0 61 0x00>;
+       };
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 7e7006f..8b756a8 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
< at >< at > -1484,6 +1484,20 < at >< at > config SERIAL_RP2_NR_UARTS
   If multiple cards are present, the default limit of 32 ports may
   need to be increased.
 
+config SERIAL_FSL_LPUART
+tristate "Freescale lpuart serial port support"
+select SERIAL_CORE
+help
+  Support for the on-chip lpuart on some Freescale SOCs.
+
+config SERIAL_FSL_LPUART_CONSOLE
+bool "Console on Freescale lpuart serial port"
+depends on SERIAL_FSL_LPUART=y
+select SERIAL_CORE_CONSOLE
+help
+  If you have enabled the lpuart serial port on the Freescale SoCs,
+  you can make it the console by answering Y to this option.
+
 endmenu
 
 endif # TTY
diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile
index eedfec4..cf650f0 100644
--- a/drivers/tty/serial/Makefile
+++ b/drivers/tty/serial/Makefile
< at >< at > -85,3 +85,4 < at >< at > obj-$(CONFIG_SERIAL_AR933X)   += ar933x_uart.o
 obj-$(CONFIG_SERIAL_EFM32_UART) += efm32-uart.o
 obj-$(CONFIG_SERIAL_ARC)+= arc_uart.o
 obj-$(CONFIG_SERIAL_RP2)+= rp2.o
+obj-$(CONFIG_SERIAL_FSL_LPUART)+= fsl_lpuart.o
diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuart.c
new file mode 100644
index 0000000..267718c
--- /dev/null
+++ b/drivers/tty/serial/fsl_lpuart.c
< at >< at > -0,0 +1,873 < at >< at >
+/*
+ *  Freescale lpuart serial port driver
+ *
+ *  Copyright 2012-2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#if defined(CONFIG_SERIAL_FSL_LPUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
+#define SUPPORT_SYSRQ
+#endif
+
+#include <linux/module.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/clk.h>
+#include <linux/of_device.h>
+#include <linux/console.h>
+#include <linux/serial_core.h>
+#include <linux/tty_flip.h>
+
+/* All registers are 8-bit width */
+#define UARTBDH0x00
+#define UARTBDL0x01
+#define UARTCR10x02
+#define UARTCR20x03
+#define UARTSR10x04
+#define UARTCR30x06
+#define UARTDR0x07
+#define UARTCR40x0a
+#define UARTCR50x0b
+#define UARTMODEM0x0d
+#define UARTPFIFO0x10
+#define UARTCFIFO0x11
+#define UARTSFIFO0x12
+#define UARTTWFIFO0x13
+#define UARTTCFIFO0x14
+#define UARTRWFIFO0x15
+
+#define UARTBDH_LBKDIE0x80
+#define UARTBDH_RXEDGIE0x40
+#define UARTBDH_SBR_MASK0x1f
+
+#define UARTCR1_LOOPS0x80
+#define UARTCR1_RSRC0x20
+#define UARTCR1_M0x10
+#define UARTCR1_WAKE0x08
+#define UARTCR1_ILT0x04
+#define UARTCR1_PE0x02
+#define UARTCR1_PT0x01
+
+#define UARTCR2_TIE0x80
+#define UARTCR2_TCIE0x40
+#define UARTCR2_RIE0x20
+#define UARTCR2_ILIE0x10
+#define UARTCR2_TE0x08
+#define UARTCR2_RE0x04
+#define UARTCR2_RWU0x02
+#define UARTCR2_SBK0x01
+
+#define UARTSR1_TDRE0x80
+#define UARTSR1_TC0x40
+#define UARTSR1_RDRF0x20
+#define UARTSR1_IDLE0x10
+#define UARTSR1_OR0x08
+#define UARTSR1_NF0x04
+#define UARTSR1_FE0x02
+#define UARTSR1_PE0x01
+
+#define UARTCR3_R80x80
+#define UARTCR3_T80x40
+#define UARTCR3_TXDIR0x20
+#define UARTCR3_TXINV0x10
+#define UARTCR3_ORIE0x08
+#define UARTCR3_NEIE0x04
+#define UARTCR3_FEIE0x02
+#define UARTCR3_PEIE0x01
+
+#define UARTCR4_MAEN10x80
+#define UARTCR4_MAEN20x40
+#define UARTCR4_M100x20
+#define UARTCR4_BRFA_MASK0x1f
+#define UARTCR4_BRFA_OFF0
+
+#define UARTCR5_TDMAS0x80
+#define UARTCR5_RDMAS0x20
+
+#define UARTMODEM_RXRTSE0x08
+#define UARTMODEM_TXRTSPOL0x04
+#define UARTMODEM_TXRTSE0x02
+#define UARTMODEM_TXCTSE0x01
+
+#define UARTPFIFO_TXFE0x80
+#define UARTPFIFO_FIFOSIZE_MASK0x7
+#define UARTPFIFO_TXSIZE_OFF4
+#define UARTPFIFO_RXFE0x08
+#define UARTPFIFO_RXSIZE_OFF0
+
+#define UARTCFIFO_TXFLUSH0x80
+#define UARTCFIFO_RXFLUSH0x40
+#define UARTCFIFO_RXOFE0x04
+#define UARTCFIFO_TXOFE0x02
+#define UARTCFIFO_RXUFE0x01
+
+#define UARTSFIFO_TXEMPT0x80
+#define UARTSFIFO_RXEMPT0x40
+#define UARTSFIFO_RXOF0x04
+#define UARTSFIFO_TXOF0x02
+#define UARTSFIFO_RXUF0x01
+
+#define DRIVER_NAME"fsl-lpuart"
+#define DEV_NAME"ttyLP"
+#define UART_NR6
+
+struct lpuart_port {
+struct uart_portport;
+struct clk*clk;
+unsigned inttxfifo_size;
+unsigned intrxfifo_size;
+};
+
+static struct of_device_id lpuart_dt_ids[] = {
+{
+.compatible = "fsl,vf610-lpuart",
+},
+{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, lpuart_dt_ids);
+
+static void lpuart_stop_tx(struct uart_port *port)
+{
+unsigned char temp;
+
+temp = readb(port->membase + UARTCR2);
+temp &= ~(UARTCR2_TIE | UARTCR2_TCIE);
+writeb(temp, port->membase + UARTCR2);
+}
+
+static void lpuart_stop_rx(struct uart_port *port)
+{
+unsigned char temp;
+
+temp = readb(port->membase + UARTCR2);
+writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2);
+}
+
+static void lpuart_enable_ms(struct uart_port *port)
+{
+}
+
+static inline void lpuart_transmit_buffer(struct lpuart_port *sport)
+{
+struct circ_buf *xmit = &sport->port.state->xmit;
+
+while (!uart_circ_empty(xmit) &&
+(readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) {
+writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR);
+xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
+sport->port.icount.tx++;
+}
+
+if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+uart_write_wakeup(&sport->port);
+
+if (uart_circ_empty(xmit))
+lpuart_stop_tx(&sport->port);
+}
+
+static void lpuart_start_tx(struct uart_port *port)
+{
+struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
+unsigned char temp;
+
+temp = readb(port->membase + UARTCR2);
+writeb(temp | UARTCR2_TIE, port->membase + UARTCR2);
+
+if (readb(port->membase + UARTSR1) & UARTSR1_TDRE)
+lpuart_transmit_buffer(sport);
+}
+
+static irqreturn_t lpuart_txint(int irq, void *dev_id)
+{
+struct lpuart_port *sport = dev_id;
+struct circ_buf *xmit = &sport->port.state->xmit;
+unsigned long flags;
+
+spin_lock_irqsave(&sport->port.lock, flags);
+if (sport->port.x_char) {
+writeb(sport->port.x_char, sport->port.membase + UARTDR);
+goto out;
+}
+
+if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
+lpuart_stop_tx(&sport->port);
+goto out;
+}
+
+lpuart_transmit_buffer(sport);
+
+if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+uart_write_wakeup(&sport->port);
+
+out:
+spin_unlock_irqrestore(&sport->port.lock, flags);
+return IRQ_HANDLED;
+}
+
+static irqreturn_t lpuart_rxint(int irq, void *dev_id)
+{
+struct lpuart_port *sport = dev_id;
+unsigned int flg, ignored = 0;
+struct tty_port *port = &sport->port.state->port;
+unsigned long flags;
+unsigned char rx, sr;
+
+spin_lock_irqsave(&sport->port.lock, flags);
+
+while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) {
+flg = TTY_NORMAL;
+sport->port.icount.rx++;
+/*
+ * to clear the FE, OR, NF, FE, PE flags,
+ * read SR1 then read DR
+ */
+sr = readb(sport->port.membase + UARTSR1);
+rx = readb(sport->port.membase + UARTDR);
+
+if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
+continue;
+
+if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) {
+if (sr & UARTSR1_PE)
+sport->port.icount.parity++;
+else if (sr & UARTSR1_FE)
+sport->port.icount.frame++;
+
+if (sr & UARTSR1_OR)
+sport->port.icount.overrun++;
+
+if (sr & sport->port.ignore_status_mask) {
+if (++ignored > 100)
+goto out;
+continue;
+}
+
+sr &= sport->port.read_status_mask;
+
+if (sr & UARTSR1_PE)
+flg = TTY_PARITY;
+else if (sr & UARTSR1_FE)
+flg = TTY_FRAME;
+
+if (sr & UARTSR1_OR)
+flg = TTY_OVERRUN;
+
+#ifdef SUPPORT_SYSRQ
+sport->port.sysrq = 0;
+#endif
+}
+
+tty_insert_flip_char(port, rx, flg);
+}
+
+out:
+spin_unlock_irqrestore(&sport->port.lock, flags);
+
+tty_flip_buffer_push(port);
+return IRQ_HANDLED;
+}
+
+static irqreturn_t lpuart_int(int irq, void *dev_id)
+{
+struct lpuart_port *sport = dev_id;
+unsigned char sts;
+
+sts = readb(sport->port.membase + UARTSR1);
+
+if (sts & UARTSR1_RDRF)
+lpuart_rxint(irq, dev_id);
+
+if (sts & UARTSR1_TDRE &&
+!(readb(sport->port.membase + UARTCR5) & UARTCR5_TDMAS))
+lpuart_txint(irq, dev_id);
+
+return IRQ_HANDLED;
+}
+
+/* return TIOCSER_TEMT when transmitter is not busy */
+static unsigned int lpuart_tx_empty(struct uart_port *port)
+{
+return (readb(port->membase + UARTSR1) & UARTSR1_TC) ?
+TIOCSER_TEMT : 0;
+}
+
+static unsigned int lpuart_get_mctrl(struct uart_port *port)
+{
+unsigned int temp = 0;
+unsigned char reg;
+
+reg = readb(port->membase + UARTMODEM);
+if (reg & UARTMODEM_TXCTSE)
+temp |= TIOCM_CTS;
+
+if (reg & UARTMODEM_RXRTSE)
+temp |= TIOCM_RTS;
+
+return temp;
+}
+
+static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl)
+{
+unsigned char temp;
+
+temp = readb(port->membase + UARTMODEM) &
+~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
+
+if (mctrl & TIOCM_RTS)
+temp |= UARTMODEM_RXRTSE;
+
+if (mctrl & TIOCM_CTS)
+temp |= UARTMODEM_TXCTSE;
+
+writeb(temp, port->membase + UARTMODEM);
+}
+
+static void lpuart_break_ctl(struct uart_port *port, int break_state)
+{
+unsigned char temp;
+
+temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK;
+
+if (break_state != 0)
+temp |= UARTCR2_SBK;
+
+writeb(temp, port->membase + UARTCR2);
+}
+
+static void lpuart_setup_watermark(struct lpuart_port *sport)
+{
+unsigned char val, cr2;
+
+cr2 = readb(sport->port.membase + UARTCR2);
+cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE |
+UARTCR2_RIE | UARTCR2_RE);
+writeb(cr2, sport->port.membase + UARTCR2);
+
+/* determine FIFO size and enable FIFO mode */
+val = readb(sport->port.membase + UARTPFIFO);
+
+sport->txfifo_size = 0x1 << (((val >> UARTPFIFO_TXSIZE_OFF) &
+UARTPFIFO_FIFOSIZE_MASK) + 1);
+
+sport->rxfifo_size = 0x1 << (((val >> UARTPFIFO_RXSIZE_OFF) &
+UARTPFIFO_FIFOSIZE_MASK) + 1);
+
+writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE,
+sport->port.membase + UARTPFIFO);
+
+/* flush Tx and Rx FIFO */
+writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
+sport->port.membase + UARTCFIFO);
+
+writeb(2, sport->port.membase + UARTTWFIFO);
+writeb(1, sport->port.membase + UARTRWFIFO);
+}
+
+static int lpuart_startup(struct uart_port *port)
+{
+struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
+int ret;
+unsigned long flags;
+unsigned char temp;
+
+ret = devm_request_irq(port->dev, port->irq, lpuart_int, 0,
+DRIVER_NAME, sport);
+if (ret)
+return ret;
+
+spin_lock_irqsave(&sport->port.lock, flags);
+
+lpuart_setup_watermark(sport);
+
+temp = readb(sport->port.membase + UARTCR2);
+temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE);
+writeb(temp, sport->port.membase + UARTCR2);
+
+spin_unlock_irqrestore(&sport->port.lock, flags);
+return 0;
+}
+
+static void lpuart_shutdown(struct uart_port *port)
+{
+struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
+unsigned char temp;
+unsigned long flags;
+
+spin_lock_irqsave(&port->lock, flags);
+
+/* disable Rx/Tx and interrupts */
+temp = readb(port->membase + UARTCR2);
+temp &= ~(UARTCR2_TE | UARTCR2_RE |
+UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
+writeb(temp, port->membase + UARTCR2);
+
+spin_unlock_irqrestore(&port->lock, flags);
+
+devm_free_irq(port->dev, port->irq, sport);
+}
+
+static void
+lpuart_set_termios(struct uart_port *port, struct ktermios *termios,
+   struct ktermios *old)
+{
+struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
+unsigned long flags;
+unsigned char cr1, old_cr1, old_cr2, cr4, bdh, modem;
+unsigned int  baud;
+unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
+unsigned int sbr, brfa;
+
+cr1 = old_cr1 = readb(sport->port.membase + UARTCR1);
+old_cr2 = readb(sport->port.membase + UARTCR2);
+cr4 = readb(sport->port.membase + UARTCR4);
+bdh = readb(sport->port.membase + UARTBDH);
+modem = readb(sport->port.membase + UARTMODEM);
+/*
+ * only support CS8 and CS7, and for CS7 must enable PE.
+ * supported mode:
+ *  - (7,e/o,1)
+ *  - (8,n,1)
+ *  - (8,m/s,1)
+ *  - (8,e/o,1)
+ */
+while ((termios->c_cflag & CSIZE) != CS8 &&
+(termios->c_cflag & CSIZE) != CS7) {
+termios->c_cflag &= ~CSIZE;
+termios->c_cflag |= old_csize;
+old_csize = CS8;
+}
+
+if ((termios->c_cflag & CSIZE) == CS8 ||
+(termios->c_cflag & CSIZE) == CS7)
+cr1 = old_cr1 & ~UARTCR1_M;
+
+if (termios->c_cflag & CMSPAR) {
+if ((termios->c_cflag & CSIZE) != CS8) {
+termios->c_cflag &= ~CSIZE;
+termios->c_cflag |= CS8;
+}
+cr1 |= UARTCR1_M;
+}
+
+if (termios->c_cflag & CRTSCTS) {
+modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
+} else {
+termios->c_cflag &= ~CRTSCTS;
+modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
+}
+
+if (termios->c_cflag & CSTOPB)
+termios->c_cflag &= ~CSTOPB;
+
+/* parity must be enabled when CS7 to match 8-bits format */
+if ((termios->c_cflag & CSIZE) == CS7)
+termios->c_cflag |= PARENB;
+
+if ((termios->c_cflag & PARENB)) {
+if (termios->c_cflag & CMSPAR) {
+cr1 &= ~UARTCR1_PE;
+cr1 |= UARTCR1_M;
+} else {
+cr1 |= UARTCR1_PE;
+if ((termios->c_cflag & CSIZE) == CS8)
+cr1 |= UARTCR1_M;
+if (termios->c_cflag & PARODD)
+cr1 |= UARTCR1_PT;
+else
+cr1 &= ~UARTCR1_PT;
+}
+}
+
+/* ask the core to calculate the divisor */
+baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
+
+spin_lock_irqsave(&sport->port.lock, flags);
+
+sport->port.read_status_mask = 0;
+if (termios->c_iflag & INPCK)
+sport->port.read_status_mask |=(UARTSR1_FE | UARTSR1_PE);
+if (termios->c_iflag & (BRKINT | PARMRK))
+sport->port.read_status_mask |= UARTSR1_FE;
+
+/* characters to ignore */
+sport->port.ignore_status_mask = 0;
+if (termios->c_iflag & IGNPAR)
+sport->port.ignore_status_mask |= UARTSR1_PE;
+if (termios->c_iflag & IGNBRK) {
+sport->port.ignore_status_mask |= UARTSR1_FE;
+/*
+ * if we're ignoring parity and break indicators,
+ * ignore overruns too (for real raw support).
+ */
+if (termios->c_iflag & IGNPAR)
+sport->port.ignore_status_mask |= UARTSR1_OR;
+}
+
+/* update the per-port timeout */
+uart_update_timeout(port, termios->c_cflag, baud);
+
+/* wait transmit engin complete */
+while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
+barrier();
+
+/* disable transmit and receive */
+writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE),
+sport->port.membase + UARTCR2);
+
+sbr = sport->port.uartclk / (16 * baud);
+brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud;
+bdh &= ~UARTBDH_SBR_MASK;
+bdh |= (sbr >> 8) & 0x1F;
+cr4 &= ~UARTCR4_BRFA_MASK;
+brfa &= UARTCR4_BRFA_MASK;
+writeb(cr4 | brfa, sport->port.membase + UARTCR4);
+writeb(bdh, sport->port.membase + UARTBDH);
+writeb(sbr & 0xFF, sport->port.membase + UARTBDL);
+writeb(cr1, sport->port.membase + UARTCR1);
+writeb(modem, sport->port.membase + UARTMODEM);
+
+/* restore control register */
+writeb(old_cr2, sport->port.membase + UARTCR2);
+
+spin_unlock_irqrestore(&sport->port.lock, flags);
+}
+
+static const char *lpuart_type(struct uart_port *port)
+{
+return "FSL_LPUART";
+}
+
+static void lpuart_release_port(struct uart_port *port)
+{
+/* nothing to do */
+}
+
+static int lpuart_request_port(struct uart_port *port)
+{
+return  0;
+}
+
+/* configure/autoconfigure the port */
+static void lpuart_config_port(struct uart_port *port, int flags)
+{
+if (flags & UART_CONFIG_TYPE)
+port->type = PORT_LPUART;
+}
+
+static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser)
+{
+int ret = 0;
+
+if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART)
+ret = -EINVAL;
+if (port->irq != ser->irq)
+ret = -EINVAL;
+if (ser->io_type != UPIO_MEM)
+ret = -EINVAL;
+if (port->uartclk / 16 != ser->baud_base)
+ret = -EINVAL;
+if (port->iobase != ser->port)
+ret = -EINVAL;
+if (ser->hub6 != 0)
+ret = -EINVAL;
+return ret;
+}
+
+static struct uart_ops lpuart_pops = {
+.tx_empty= lpuart_tx_empty,
+.set_mctrl= lpuart_set_mctrl,
+.get_mctrl= lpuart_get_mctrl,
+.stop_tx= lpuart_stop_tx,
+.start_tx= lpuart_start_tx,
+.stop_rx= lpuart_stop_rx,
+.enable_ms= lpuart_enable_ms,
+.break_ctl= lpuart_break_ctl,
+.startup= lpuart_startup,
+.shutdown= lpuart_shutdown,
+.set_termios= lpuart_set_termios,
+.type= lpuart_type,
+.request_port= lpuart_request_port,
+.release_port= lpuart_release_port,
+.config_port= lpuart_config_port,
+.verify_port= lpuart_verify_port,
+};
+
+static struct lpuart_port *lpuart_ports[UART_NR];
+
+#ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE
+static void lpuart_console_putchar(struct uart_port *port, int ch)
+{
+while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE))
+barrier();
+
+writeb(ch, port->membase + UARTDR);
+}
+
+static void
+lpuart_console_write(struct console *co, const char *s, unsigned int count)
+{
+struct lpuart_port *sport = lpuart_ports[co->index];
+unsigned char  old_cr2, cr2;
+
+/* first save CR2 and then disable interrupts */
+cr2 = old_cr2 = readb(sport->port.membase + UARTCR2);
+cr2 |= (UARTCR2_TE |  UARTCR2_RE);
+cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
+writeb(cr2, sport->port.membase + UARTCR2);
+
+uart_console_write(&sport->port, s, count, lpuart_console_putchar);
+
+/* wait for transmitter finish complete and restore CR2 */
+while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
+barrier();
+
+writeb(old_cr2, sport->port.membase + UARTCR2);
+}
+
+/*
+ * if the port was already initialised (eg, by a boot loader),
+ * try to determine the current setup.
+ */
+static void __init
+lpuart_console_get_options(struct lpuart_port *sport, int *baud,
+   int *parity, int *bits)
+{
+unsigned char cr, bdh, bdl, brfa;
+unsigned int sbr, uartclk, baud_raw;
+
+cr = readb(sport->port.membase + UARTCR2);
+cr &= UARTCR2_TE | UARTCR2_RE;
+if (!cr)
+return;
+
+/* ok, the port was enabled */
+
+cr = readb(sport->port.membase + UARTCR1);
+
+*parity = 'n';
+if (cr & UARTCR1_PE) {
+if (cr & UARTCR1_PT)
+*parity = 'o';
+else
+*parity = 'e';
+}
+
+if (cr & UARTCR1_M)
+*bits = 9;
+else
+*bits = 8;
+
+bdh = readb(sport->port.membase + UARTBDH);
+bdh &= UARTBDH_SBR_MASK;
+bdl = readb(sport->port.membase + UARTBDL);
+sbr = bdh;
+sbr <<= 8;
+sbr |= bdl;
+brfa = readb(sport->port.membase + UARTCR4);
+brfa &= UARTCR4_BRFA_MASK;
+
+uartclk = clk_get_rate(sport->clk);
+/*
+ * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
+ */
+baud_raw = uartclk / (16 * (sbr + brfa / 32));
+
+if (*baud != baud_raw)
+printk(KERN_INFO "Serial: Console lpuart rounded baud rate"
+"from %d to %d\n", baud_raw, *baud);
+}
+
+static int __init lpuart_console_setup(struct console *co, char *options)
+{
+struct lpuart_port *sport;
+int baud = 115200;
+int bits = 8;
+int parity = 'n';
+int flow = 'n';
+
+/*
+ * check whether an invalid uart number has been specified, and
+ * if so, search for the first available port that does have
+ * console support.
+ */
+if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports))
+co->index = 0;
+
+sport = lpuart_ports[co->index];
+if (sport == NULL)
+return -ENODEV;
+
+if (options)
+uart_parse_options(options, &baud, &parity, &bits, &flow);
+else
+lpuart_console_get_options(sport, &baud, &parity, &bits);
+
+lpuart_setup_watermark(sport);
+
+return uart_set_options(&sport->port, co, baud, parity, bits, flow);
+}
+
+static struct uart_driver lpuart_reg;
+static struct console lpuart_console = {
+.name= DEV_NAME,
+.write= lpuart_console_write,
+.device= uart_console_device,
+.setup= lpuart_console_setup,
+.flags= CON_PRINTBUFFER,
+.index= -1,
+.data= &lpuart_reg,
+};
+
+#define LPUART_CONSOLE(&lpuart_console)
+#else
+#define LPUART_CONSOLENULL
+#endif
+
+static struct uart_driver lpuart_reg = {
+.owner= THIS_MODULE,
+.driver_name= DRIVER_NAME,
+.dev_name= DEV_NAME,
+.nr= ARRAY_SIZE(lpuart_ports),
+.cons= LPUART_CONSOLE,
+};
+
+static int lpuart_probe(struct platform_device *pdev)
+{
+struct device_node *np = pdev->dev.of_node;
+struct lpuart_port *sport;
+struct resource *res;
+int ret;
+
+sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
+if (!sport)
+return -ENOMEM;
+
+pdev->dev.coherent_dma_mask = 0;
+
+ret = of_alias_get_id(np, "serial");
+if (ret < 0) {
+dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
+return ret;
+}
+sport->port.line = ret;
+
+res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+if (!res)
+return -ENODEV;
+
+sport->port.mapbase = res->start;
+sport->port.membase = devm_ioremap_resource(&pdev->dev, res);
+if (IS_ERR(sport->port.membase))
+return PTR_ERR(sport->port.membase);
+
+sport->port.dev = &pdev->dev;
+sport->port.type = PORT_LPUART;
+sport->port.iotype = UPIO_MEM;
+sport->port.irq = platform_get_irq(pdev, 0);
+sport->port.ops = &lpuart_pops;
+sport->port.flags = UPF_BOOT_AUTOCONF;
+
+sport->clk = devm_clk_get(&pdev->dev, "ipg");
+if (IS_ERR(sport->clk)) {
+ret = PTR_ERR(sport->clk);
+dev_err(&pdev->dev, "failed to get uart clk: %d\n", ret);
+return ret;
+}
+
+ret = clk_prepare_enable(sport->clk);
+if (ret) {
+dev_err(&pdev->dev, "failed to enable uart clk: %d\n", ret);
+return ret;
+}
+
+sport->port.uartclk = clk_get_rate(sport->clk);
+
+lpuart_ports[sport->port.line] = sport;
+
+platform_set_drvdata(pdev, &sport->port);
+
+ret = uart_add_one_port(&lpuart_reg, &sport->port);
+if (ret) {
+clk_disable_unprepare(sport->clk);
+return ret;
+}
+
+return 0;
+}
+
+static int lpuart_remove(struct platform_device *pdev)
+{
+struct lpuart_port *sport = platform_get_drvdata(pdev);
+
+uart_remove_one_port(&lpuart_reg, &sport->port);
+
+clk_disable_unprepare(sport->clk);
+
+return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int lpuart_suspend(struct device *dev)
+{
+struct lpuart_port *sport = dev_get_drvdata(dev);
+
+uart_suspend_port(&lpuart_reg, &sport->port);
+
+return 0;
+}
+
+static int lpuart_resume(struct device *dev)
+{
+struct lpuart_port *sport = dev_get_drvdata(dev);
+
+uart_resume_port(&lpuart_reg, &sport->port);
+
+return 0;
+}
+#endif
+
+static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume);
+
+static struct platform_driver lpuart_driver = {
+.probe= lpuart_probe,
+.remove= lpuart_remove,
+.driver= {
+.name= "fsl-lpuart",
+.owner= THIS_MODULE,
+.of_match_table = lpuart_dt_ids,
+.pm= &lpuart_pm_ops,
+},
+};
+
+static int __init lpuart_serial_init(void)
+{
+int ret;
+
+pr_info("serial: Freescale lpuart driver\n");
+
+ret = uart_register_driver(&lpuart_reg);
+if (ret)
+return ret;
+
+ret = platform_driver_register(&lpuart_driver);
+if (ret)
+uart_unregister_driver(&lpuart_reg);
+
+return 0;
+}
+
+static void __exit lpuart_serial_exit(void)
+{
+platform_driver_unregister(&lpuart_driver);
+uart_unregister_driver(&lpuart_reg);
+}
+
+module_init(lpuart_serial_init);
+module_exit(lpuart_serial_exit);
+
+MODULE_DESCRIPTION("Freescale lpuart serial port driver");
+MODULE_LICENSE("GPL v2");
diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h
index 74c2bf7..c8eaeb5 100644
--- a/include/uapi/linux/serial_core.h
+++ b/include/uapi/linux/serial_core.h
< at >< at > -226,4 +226,7 < at >< at >
 /* Rocketport EXPRESS/INFINITY */
 #define PORT_RP2102
 
+/* Freescale lpuart */
+#define PORT_LPUART103
+
 #endif /* _UAPILINUX_SERIAL_CORE_H */

MAX14830 serial driver

Alexander Shiyan — 2013-06-01T18:37:01

Hello All.

For all who ask me about MAX14830 support in the max310x driver,
support is completed, preliminary version I can send to test.
Once driver is being tested, patch for this chip will be posted
for apply in the kernel. So if you want to test initial version,
please mail me.
Thanks.

[PATCH] serial/imx: disable hardware flow control at startup

Markus Pargmann — 2013-05-30T13:47:04

From: Lucas Stach <l.stach< at >pengutronix.de>

We only want to enable hardware flow control if RTS/CTS pins
are connected.

Signed-off-by: Lucas Stach <l.stach< at >pengutronix.de>
Signed-off-by: Markus Pargmann <mpa< at >pengutronix.de>
---

 drivers/tty/serial/imx.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
index 147c9e1..8cdfbd3 100644
--- a/drivers/tty/serial/imx.c
+++ b/drivers/tty/serial/imx.c
< at >< at > -761,6 +761,8 < at >< at > static int imx_startup(struct uart_port *port)
 
 temp = readl(sport->port.membase + UCR2);
 temp |= (UCR2_RXEN | UCR2_TXEN);
+if (!sport->have_rtscts)
+temp |= UCR2_IRTS;
 writel(temp, sport->port.membase + UCR2);
 
 if (USE_IRDA(sport)) {

Connection to a 3G USB Module using USB-Serial

Fabio Fumi — 2013-05-30T12:54:40

I'm struggling with this issue since a while and as the author of the
USB-Serial module I thought experts here might provide some help... As
it's a USB-serail issue, I've posted on both USB and Serial lists.
thanks in advance!

The problem is about connecting with a 3G USB modem, a ZTE MF-210
mini-pci board; plugged as a daughter board inside an Android tablet.
I have posted already on a couple forums, but got no useful feedback
yet.

As soon as I power up the module I get the expected /dev/ttyUSB0-3 and
that's fine, so far:

<6>usb 1-1.1: new high speed USB device using emxx-ehci-driver and address 3
<6>option 1-1.1:1.0: GSM modem (1-port) converter detected
<6>usb 1-1.1: GSM modem (1-port) converter now attached to ttyUSB0
<6>option 1-1.1:1.1: GSM modem (1-port) converter detected
<6>usb 1-1.1: GSM modem (1-port) converter now attached to ttyUSB1
<6>option 1-1.1:1.2: GSM modem (1-port) converter detected
<6>usb 1-1.1: GSM modem (1-port) converter now attached to ttyUSB2
<6>option 1-1.1:1.3: GSM modem (1-port) converter detected
<6>usb 1-1.1: GSM modem (1-port) converter now attached to ttyUSB3

Issue is when I try to communicate with any of these ports. I can
connect using picocom to all but can't receive any feedback from AT
commands sent over to them. I made some partial progress only after
using the "-i" option (i.e. "no port init"), but below you can find
what I get if I simply type A + T + Z + <enter>, for example.

As you can see, characters and commands are repeated several times.
That's what I can't understand.

Without the -i option, I don't even get any feedback from the modem
and the same happens using other connection programs, e.g. busybox
microcom. I'm using picocom as it's very small and I succesfully used
it already in a similar case, though on a different Android platform
and kernel.

This Kernel is built including standard usb-serial options below:

CONFIG_USB_SERIAL=y
CONFIG_USB_SERIAL_WWAN=y
CONFIG_USB_SERIAL_OPTION=y

Is the kernel missing anything, or requiring some special ZTE-specific
customizations in your opinion?

What are the best connection options I could try?

 thanks
--
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[PATCH v5] tty: serial: add Freescale lpuart driver support

Jingchang Lu — 2013-05-30T05:53:37

Add Freescale lpuart driver support. The lpuart device
can be found on Vybrid VF610 and Layerscape LS-1 SoCs.

Signed-off-by: Jingchang Lu <b35083< at >freescale.com>
---
changes in v5:
 Coding style fix, remove redundant code.
 Checking clk_prepare_enable return value.
 Using devm_ioremap_resource instead of devm_request_and_ioremap.

changes in v4:
 Change Vybrid VF610 SoC compatible string to "fsl,vf610-lpuart"

changes in v3:
 Use general driver name lpuart instead of mvf for further share between SoCs.
 Add bind doc in Documentation/devicetree/bindings/tty/serial.
 Remove unused #include header lines and clean up code.

changes in v2:
 Remove unused variables and clean up the code.

 .../devicetree/bindings/tty/serial/fsl-lpuart.txt  |  14 +
 drivers/tty/serial/Kconfig                         |  14 +
 drivers/tty/serial/Makefile                        |   1 +
 drivers/tty/serial/fsl_lpuart.c                    | 873 +++++++++++++++++++++
 include/uapi/linux/serial_core.h                   |   3 +
 5 files changed, 905 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/tty/serial/fsl-lpuart.txt
 create mode 100644 drivers/tty/serial/fsl_lpuart.c

diff --git a/Documentation/devicetree/bindings/tty/serial/fsl-lpuart.txt b/Documentation/devicetree/bindings/tty/serial/fsl-lpuart.txt
new file mode 100644
index 0000000..6fd1dd1
--- /dev/null
+++ b/Documentation/devicetree/bindings/tty/serial/fsl-lpuart.txt
< at >< at > -0,0 +1,14 < at >< at >
+* Freescale low power universal asynchronous receiver/transmitter (lpuart)
+
+Required properties:
+- compatible : Should be "fsl,<soc>-lpuart"
+- reg : Address and length of the register set for the device
+- interrupts : Should contain uart interrupt
+
+Example:
+
+uart0: serial< at >40027000 {
+       compatible = "fsl,vf610-lpuart";
+       reg = <0x40027000 0x1000>;
+       interrupts = <0 61 0x00>;
+       };
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 7e7006f..aee7030 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
< at >< at > -1484,6 +1484,20 < at >< at > config SERIAL_RP2_NR_UARTS
   If multiple cards are present, the default limit of 32 ports may
   need to be increased.
 
+config SERIAL_FSL_LPUART
+bool "Freescale lpuart serial port support"
+select SERIAL_CORE
+help
+  Support for the on-chip lpuart on some Freescale SOCs.
+
+config SERIAL_FSL_LPUART_CONSOLE
+bool "Console on Freescale lpuart serial port"
+depends on SERIAL_FSL_LPUART
+select SERIAL_CORE_CONSOLE
+help
+  If you have enabled the lpuart serial port on the Freescale SoCs,
+  you can make it the console by answering Y to this option.
+
 endmenu
 
 endif # TTY
diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile
index eedfec4..cf650f0 100644
--- a/drivers/tty/serial/Makefile
+++ b/drivers/tty/serial/Makefile
< at >< at > -85,3 +85,4 < at >< at > obj-$(CONFIG_SERIAL_AR933X)   += ar933x_uart.o
 obj-$(CONFIG_SERIAL_EFM32_UART) += efm32-uart.o
 obj-$(CONFIG_SERIAL_ARC)+= arc_uart.o
 obj-$(CONFIG_SERIAL_RP2)+= rp2.o
+obj-$(CONFIG_SERIAL_FSL_LPUART)+= fsl_lpuart.o
diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuart.c
new file mode 100644
index 0000000..7fb1681
--- /dev/null
+++ b/drivers/tty/serial/fsl_lpuart.c
< at >< at > -0,0 +1,873 < at >< at >
+/*
+ *  Freescale lpuart serial port driver
+ *
+ *  Copyright 2012-2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#if defined(CONFIG_SERIAL_FSL_LPUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
+#define SUPPORT_SYSRQ
+#endif
+
+#include <linux/module.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/clk.h>
+#include <linux/of_device.h>
+#include <linux/console.h>
+#include <linux/serial_core.h>
+#include <linux/tty_flip.h>
+
+/* All registers are 8-bit width */
+#define UARTBDH0x00
+#define UARTBDL0x01
+#define UARTCR10x02
+#define UARTCR20x03
+#define UARTSR10x04
+#define UARTCR30x06
+#define UARTDR0x07
+#define UARTCR40x0a
+#define UARTCR50x0b
+#define UARTMODEM0x0d
+#define UARTPFIFO0x10
+#define UARTCFIFO0x11
+#define UARTSFIFO0x12
+#define UARTTWFIFO0x13
+#define UARTTCFIFO0x14
+#define UARTRWFIFO0x15
+
+#define UARTBDH_LBKDIE0x80
+#define UARTBDH_RXEDGIE0x40
+#define UARTBDH_SBR_MASK0x1f
+
+#define UARTCR1_LOOPS0x80
+#define UARTCR1_RSRC0x20
+#define UARTCR1_M0x10
+#define UARTCR1_WAKE0x08
+#define UARTCR1_ILT0x04
+#define UARTCR1_PE0x02
+#define UARTCR1_PT0x01
+
+#define UARTCR2_TIE0x80
+#define UARTCR2_TCIE0x40
+#define UARTCR2_RIE0x20
+#define UARTCR2_ILIE0x10
+#define UARTCR2_TE0x08
+#define UARTCR2_RE0x04
+#define UARTCR2_RWU0x02
+#define UARTCR2_SBK0x01
+
+#define UARTSR1_TDRE0x80
+#define UARTSR1_TC0x40
+#define UARTSR1_RDRF0x20
+#define UARTSR1_IDLE0x10
+#define UARTSR1_OR0x08
+#define UARTSR1_NF0x04
+#define UARTSR1_FE0x02
+#define UARTSR1_PE0x01
+
+#define UARTCR3_R80x80
+#define UARTCR3_T80x40
+#define UARTCR3_TXDIR0x20
+#define UARTCR3_TXINV0x10
+#define UARTCR3_ORIE0x08
+#define UARTCR3_NEIE0x04
+#define UARTCR3_FEIE0x02
+#define UARTCR3_PEIE0x01
+
+#define UARTCR4_MAEN10x80
+#define UARTCR4_MAEN20x40
+#define UARTCR4_M100x20
+#define UARTCR4_BRFA_MASK0x1f
+#define UARTCR4_BRFA_OFF0
+
+#define UARTCR5_TDMAS0x80
+#define UARTCR5_RDMAS0x20
+
+#define UARTMODEM_RXRTSE0x08
+#define UARTMODEM_TXRTSPOL0x04
+#define UARTMODEM_TXRTSE0x02
+#define UARTMODEM_TXCTSE0x01
+
+#define UARTPFIFO_TXFE0x80
+#define UARTPFIFO_FIFOSIZE_MASK0x7
+#define UARTPFIFO_TXSIZE_OFF4
+#define UARTPFIFO_RXFE0x08
+#define UARTPFIFO_RXSIZE_OFF0
+
+#define UARTCFIFO_TXFLUSH0x80
+#define UARTCFIFO_RXFLUSH0x40
+#define UARTCFIFO_RXOFE0x04
+#define UARTCFIFO_TXOFE0x02
+#define UARTCFIFO_RXUFE0x01
+
+#define UARTSFIFO_TXEMPT0x80
+#define UARTSFIFO_RXEMPT0x40
+#define UARTSFIFO_RXOF0x04
+#define UARTSFIFO_TXOF0x02
+#define UARTSFIFO_RXUF0x01
+
+#define DRIVER_NAME"fsl-lpuart"
+#define DEV_NAME"ttyLP"
+#define UART_NR6
+
+struct lpuart_port {
+struct uart_portport;
+struct clk*clk;
+unsigned inttxfifo_size;
+unsigned intrxfifo_size;
+};
+
+static struct of_device_id lpuart_dt_ids[] = {
+{
+.compatible = "fsl,vf610-lpuart",
+},
+{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, lpuart_dt_ids);
+
+static void lpuart_stop_tx(struct uart_port *port)
+{
+unsigned char temp;
+
+temp = readb(port->membase + UARTCR2);
+temp &= ~(UARTCR2_TIE | UARTCR2_TCIE);
+writeb(temp, port->membase + UARTCR2);
+}
+
+static void lpuart_stop_rx(struct uart_port *port)
+{
+unsigned char temp;
+
+temp = readb(port->membase + UARTCR2);
+writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2);
+}
+
+static void lpuart_enable_ms(struct uart_port *port)
+{
+}
+
+static inline void lpuart_transmit_buffer(struct lpuart_port *sport)
+{
+struct circ_buf *xmit = &sport->port.state->xmit;
+
+while (!uart_circ_empty(xmit) &&
+(readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) {
+writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR);
+xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
+sport->port.icount.tx++;
+}
+
+if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+uart_write_wakeup(&sport->port);
+
+if (uart_circ_empty(xmit))
+lpuart_stop_tx(&sport->port);
+}
+
+static void lpuart_start_tx(struct uart_port *port)
+{
+struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
+unsigned char temp;
+
+temp = readb(port->membase + UARTCR2);
+writeb(temp | UARTCR2_TIE, port->membase + UARTCR2);
+
+if (readb(port->membase + UARTSR1) & UARTSR1_TDRE)
+lpuart_transmit_buffer(sport);
+}
+
+static irqreturn_t lpuart_txint(int irq, void *dev_id)
+{
+struct lpuart_port *sport = dev_id;
+struct circ_buf *xmit = &sport->port.state->xmit;
+unsigned long flags;
+
+spin_lock_irqsave(&sport->port.lock, flags);
+if (sport->port.x_char) {
+writeb(sport->port.x_char, sport->port.membase + UARTDR);
+goto out;
+}
+
+if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
+lpuart_stop_tx(&sport->port);
+goto out;
+}
+
+lpuart_transmit_buffer(sport);
+
+if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+uart_write_wakeup(&sport->port);
+
+out:
+spin_unlock_irqrestore(&sport->port.lock, flags);
+return IRQ_HANDLED;
+}
+
+static irqreturn_t lpuart_rxint(int irq, void *dev_id)
+{
+struct lpuart_port *sport = dev_id;
+unsigned int flg, ignored = 0;
+struct tty_port *port = &sport->port.state->port;
+unsigned long flags;
+unsigned char rx, sr;
+
+spin_lock_irqsave(&sport->port.lock, flags);
+
+while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) {
+flg = TTY_NORMAL;
+sport->port.icount.rx++;
+/*
+ * to clear the FE, OR, NF, FE, PE flags,
+ * read SR1 then read DR
+ */
+sr = readb(sport->port.membase + UARTSR1);
+rx = readb(sport->port.membase + UARTDR);
+
+if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
+continue;
+
+if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) {
+if (sr & UARTSR1_PE)
+sport->port.icount.parity++;
+else if (sr & UARTSR1_FE)
+sport->port.icount.frame++;
+
+if (sr & UARTSR1_OR)
+sport->port.icount.overrun++;
+
+if (sr & sport->port.ignore_status_mask) {
+if (++ignored > 100)
+goto out;
+continue;
+}
+
+sr &= sport->port.read_status_mask;
+
+if (sr & UARTSR1_PE)
+flg = TTY_PARITY;
+else if (sr & UARTSR1_FE)
+flg = TTY_FRAME;
+
+if (sr & UARTSR1_OR)
+flg = TTY_OVERRUN;
+
+#ifdef SUPPORT_SYSRQ
+sport->port.sysrq = 0;
+#endif
+}
+
+tty_insert_flip_char(port, rx, flg);
+}
+
+out:
+spin_unlock_irqrestore(&sport->port.lock, flags);
+
+tty_flip_buffer_push(port);
+return IRQ_HANDLED;
+}
+
+static irqreturn_t lpuart_int(int irq, void *dev_id)
+{
+struct lpuart_port *sport = dev_id;
+unsigned char sts;
+
+sts = readb(sport->port.membase + UARTSR1);
+
+if (sts & UARTSR1_RDRF)
+lpuart_rxint(irq, dev_id);
+
+if (sts & UARTSR1_TDRE &&
+!(readb(sport->port.membase + UARTCR5) & UARTCR5_TDMAS))
+lpuart_txint(irq, dev_id);
+
+return IRQ_HANDLED;
+}
+
+/* return TIOCSER_TEMT when transmitter is not busy */
+static unsigned int lpuart_tx_empty(struct uart_port *port)
+{
+return (readb(port->membase + UARTSR1) & UARTSR1_TC) ?
+TIOCSER_TEMT : 0;
+}
+
+static unsigned int lpuart_get_mctrl(struct uart_port *port)
+{
+unsigned int temp = 0;
+unsigned char reg;
+
+reg = readb(port->membase + UARTMODEM);
+if (reg & UARTMODEM_TXCTSE)
+temp |= TIOCM_CTS;
+
+if (reg & UARTMODEM_RXRTSE)
+temp |= TIOCM_RTS;
+
+return temp;
+}
+
+static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl)
+{
+unsigned char temp;
+
+temp = readb(port->membase + UARTMODEM) &
+~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
+
+if (mctrl & TIOCM_RTS)
+temp |= UARTMODEM_RXRTSE;
+
+if (mctrl & TIOCM_CTS)
+temp |= UARTMODEM_TXCTSE;
+
+writeb(temp, port->membase + UARTMODEM);
+}
+
+static void lpuart_break_ctl(struct uart_port *port, int break_state)
+{
+unsigned char temp;
+
+temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK;
+
+if (break_state != 0)
+temp |= UARTCR2_SBK;
+
+writeb(temp, port->membase + UARTCR2);
+}
+
+static void lpuart_setup_watermark(struct lpuart_port *sport)
+{
+unsigned char val, cr2;
+
+cr2 = readb(sport->port.membase + UARTCR2);
+cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE |
+UARTCR2_RIE | UARTCR2_RE);
+writeb(cr2, sport->port.membase + UARTCR2);
+
+/* determine FIFO size and enable FIFO mode */
+val = readb(sport->port.membase + UARTPFIFO);
+
+sport->txfifo_size = 0x1 << (((val >> UARTPFIFO_TXSIZE_OFF) &
+UARTPFIFO_FIFOSIZE_MASK) + 1);
+
+sport->rxfifo_size = 0x1 << (((val >> UARTPFIFO_RXSIZE_OFF) &
+UARTPFIFO_FIFOSIZE_MASK) + 1);
+
+writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE,
+sport->port.membase + UARTPFIFO);
+
+/* flush Tx and Rx FIFO */
+writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
+sport->port.membase + UARTCFIFO);
+
+writeb(2, sport->port.membase + UARTTWFIFO);
+writeb(1, sport->port.membase + UARTRWFIFO);
+}
+
+static int lpuart_startup(struct uart_port *port)
+{
+struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
+int ret;
+unsigned long flags;
+unsigned char temp;
+
+ret = devm_request_irq(port->dev, port->irq, lpuart_int, 0,
+DRIVER_NAME, sport);
+if (ret)
+return ret;
+
+spin_lock_irqsave(&sport->port.lock, flags);
+
+lpuart_setup_watermark(sport);
+
+temp = readb(sport->port.membase + UARTCR2);
+temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE);
+writeb(temp, sport->port.membase + UARTCR2);
+
+spin_unlock_irqrestore(&sport->port.lock, flags);
+return 0;
+}
+
+static void lpuart_shutdown(struct uart_port *port)
+{
+struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
+unsigned char temp;
+unsigned long flags;
+
+spin_lock_irqsave(&port->lock, flags);
+
+/* disable Rx/Tx and interrupts */
+temp = readb(port->membase + UARTCR2);
+temp &= ~(UARTCR2_TE | UARTCR2_RE |
+UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
+writeb(temp, port->membase + UARTCR2);
+
+spin_unlock_irqrestore(&port->lock, flags);
+
+devm_free_irq(port->dev, port->irq, sport);
+}
+
+static void
+lpuart_set_termios(struct uart_port *port, struct ktermios *termios,
+   struct ktermios *old)
+{
+struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
+unsigned long flags;
+unsigned char cr1, old_cr1, old_cr2, cr4, bdh, modem;
+unsigned int  baud;
+unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
+unsigned int sbr, brfa;
+
+cr1 = old_cr1 = readb(sport->port.membase + UARTCR1);
+old_cr2 = readb(sport->port.membase + UARTCR2);
+cr4 = readb(sport->port.membase + UARTCR4);
+bdh = readb(sport->port.membase + UARTBDH);
+modem = readb(sport->port.membase + UARTMODEM);
+/*
+ * only support CS8 and CS7, and for CS7 must enable PE.
+ * supported mode:
+ *  - (7,e/o,1)
+ *  - (8,n,1)
+ *  - (8,m/s,1)
+ *  - (8,e/o,1)
+ */
+while ((termios->c_cflag & CSIZE) != CS8 &&
+(termios->c_cflag & CSIZE) != CS7) {
+termios->c_cflag &= ~CSIZE;
+termios->c_cflag |= old_csize;
+old_csize = CS8;
+}
+
+if ((termios->c_cflag & CSIZE) == CS8 ||
+(termios->c_cflag & CSIZE) == CS7)
+cr1 = old_cr1 & ~UARTCR1_M;
+
+if (termios->c_cflag & CMSPAR) {
+if ((termios->c_cflag & CSIZE) != CS8) {
+termios->c_cflag &= ~CSIZE;
+termios->c_cflag |= CS8;
+}
+cr1 |= UARTCR1_M;
+}
+
+if (termios->c_cflag & CRTSCTS) {
+modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
+} else {
+termios->c_cflag &= ~CRTSCTS;
+modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
+}
+
+if (termios->c_cflag & CSTOPB)
+termios->c_cflag &= ~CSTOPB;
+
+/* parity must be enabled when CS7 to match 8-bits format */
+if ((termios->c_cflag & CSIZE) == CS7)
+termios->c_cflag |= PARENB;
+
+if ((termios->c_cflag & PARENB)) {
+if (termios->c_cflag & CMSPAR) {
+cr1 &= ~UARTCR1_PE;
+cr1 |= UARTCR1_M;
+} else {
+cr1 |= UARTCR1_PE;
+if ((termios->c_cflag & CSIZE) == CS8)
+cr1 |= UARTCR1_M;
+if (termios->c_cflag & PARODD)
+cr1 |= UARTCR1_PT;
+else
+cr1 &= ~UARTCR1_PT;
+}
+}
+
+/* ask the core to calculate the divisor */
+baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
+
+spin_lock_irqsave(&sport->port.lock, flags);
+
+sport->port.read_status_mask = 0;
+if (termios->c_iflag & INPCK)
+sport->port.read_status_mask |=(UARTSR1_FE | UARTSR1_PE);
+if (termios->c_iflag & (BRKINT | PARMRK))
+sport->port.read_status_mask |= UARTSR1_FE;
+
+/* characters to ignore */
+sport->port.ignore_status_mask = 0;
+if (termios->c_iflag & IGNPAR)
+sport->port.ignore_status_mask |= UARTSR1_PE;
+if (termios->c_iflag & IGNBRK) {
+sport->port.ignore_status_mask |= UARTSR1_FE;
+/*
+ * if we're ignoring parity and break indicators,
+ * ignore overruns too (for real raw support).
+ */
+if (termios->c_iflag & IGNPAR)
+sport->port.ignore_status_mask |= UARTSR1_OR;
+}
+
+/* update the per-port timeout */
+uart_update_timeout(port, termios->c_cflag, baud);
+
+/* wait transmit engin complete */
+while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
+barrier();
+
+/* disable transmit and receive */
+writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE),
+sport->port.membase + UARTCR2);
+
+sbr = sport->port.uartclk / (16 * baud);
+brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud;
+bdh &= ~UARTBDH_SBR_MASK;
+bdh |= (sbr >> 8) & 0x1F;
+cr4 &= ~UARTCR4_BRFA_MASK;
+brfa &= UARTCR4_BRFA_MASK;
+writeb(cr4 | brfa, sport->port.membase + UARTCR4);
+writeb(bdh, sport->port.membase + UARTBDH);
+writeb(sbr & 0xFF, sport->port.membase + UARTBDL);
+writeb(cr1, sport->port.membase + UARTCR1);
+writeb(modem, sport->port.membase + UARTMODEM);
+
+/* restore control register */
+writeb(old_cr2, sport->port.membase + UARTCR2);
+
+spin_unlock_irqrestore(&sport->port.lock, flags);
+}
+
+static const char *lpuart_type(struct uart_port *port)
+{
+return "FSL_LPUART";
+}
+
+static void lpuart_release_port(struct uart_port *port)
+{
+/* nothing to do */
+}
+
+static int lpuart_request_port(struct uart_port *port)
+{
+return  0;
+}
+
+/* configure/autoconfigure the port */
+static void lpuart_config_port(struct uart_port *port, int flags)
+{
+if (flags & UART_CONFIG_TYPE)
+port->type = PORT_LPUART;
+}
+
+static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser)
+{
+int ret = 0;
+
+if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART)
+ret = -EINVAL;
+if (port->irq != ser->irq)
+ret = -EINVAL;
+if (ser->io_type != UPIO_MEM)
+ret = -EINVAL;
+if (port->uartclk / 16 != ser->baud_base)
+ret = -EINVAL;
+if (port->iobase != ser->port)
+ret = -EINVAL;
+if (ser->hub6 != 0)
+ret = -EINVAL;
+return ret;
+}
+
+static struct uart_ops lpuart_pops = {
+.tx_empty= lpuart_tx_empty,
+.set_mctrl= lpuart_set_mctrl,
+.get_mctrl= lpuart_get_mctrl,
+.stop_tx= lpuart_stop_tx,
+.start_tx= lpuart_start_tx,
+.stop_rx= lpuart_stop_rx,
+.enable_ms= lpuart_enable_ms,
+.break_ctl= lpuart_break_ctl,
+.startup= lpuart_startup,
+.shutdown= lpuart_shutdown,
+.set_termios= lpuart_set_termios,
+.type= lpuart_type,
+.request_port= lpuart_request_port,
+.release_port= lpuart_release_port,
+.config_port= lpuart_config_port,
+.verify_port= lpuart_verify_port,
+};
+
+static struct lpuart_port *lpuart_ports[UART_NR];
+
+#ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE
+static void lpuart_console_putchar(struct uart_port *port, int ch)
+{
+while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE))
+barrier();
+
+writeb(ch, port->membase + UARTDR);
+}
+
+static void
+lpuart_console_write(struct console *co, const char *s, unsigned int count)
+{
+struct lpuart_port *sport = lpuart_ports[co->index];
+unsigned char  old_cr2, cr2;
+
+/* first save CR2 and then disable interrupts */
+cr2 = old_cr2 = readb(sport->port.membase + UARTCR2);
+cr2 |= (UARTCR2_TE |  UARTCR2_RE);
+cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
+writeb(cr2, sport->port.membase + UARTCR2);
+
+uart_console_write(&sport->port, s, count, lpuart_console_putchar);
+
+/* wait for transmitter finish complete and restore CR2 */
+while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
+barrier();
+
+writeb(old_cr2, sport->port.membase + UARTCR2);
+}
+
+/*
+ * if the port was already initialised (eg, by a boot loader),
+ * try to determine the current setup.
+ */
+static void __init
+lpuart_console_get_options(struct lpuart_port *sport, int *baud,
+   int *parity, int *bits)
+{
+unsigned char cr, bdh, bdl, brfa;
+unsigned int sbr, uartclk, baud_raw;
+
+cr = readb(sport->port.membase + UARTCR2);
+cr &= UARTCR2_TE | UARTCR2_RE;
+if (!cr)
+return;
+
+/* ok, the port was enabled */
+
+cr = readb(sport->port.membase + UARTCR1);
+
+*parity = 'n';
+if (cr & UARTCR1_PE) {
+if (cr & UARTCR1_PT)
+*parity = 'o';
+else
+*parity = 'e';
+}
+
+if (cr & UARTCR1_M)
+*bits = 9;
+else
+*bits = 8;
+
+bdh = readb(sport->port.membase + UARTBDH);
+bdh &= UARTBDH_SBR_MASK;
+bdl = readb(sport->port.membase + UARTBDL);
+sbr = bdh;
+sbr <<= 8;
+sbr |= bdl;
+brfa = readb(sport->port.membase + UARTCR4);
+brfa &= UARTCR4_BRFA_MASK;
+
+uartclk = clk_get_rate(sport->clk);
+/*
+ * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
+ */
+baud_raw = uartclk / (16 * (sbr + brfa / 32));
+
+if (*baud != baud_raw)
+printk(KERN_INFO "Serial: Console lpuart rounded baud rate"
+"from %d to %d\n", baud_raw, *baud);
+}
+
+static int __init lpuart_console_setup(struct console *co, char *options)
+{
+struct lpuart_port *sport;
+int baud = 115200;
+int bits = 8;
+int parity = 'n';
+int flow = 'n';
+
+/*
+ * check whether an invalid uart number has been specified, and
+ * if so, search for the first available port that does have
+ * console support.
+ */
+if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports))
+co->index = 0;
+
+sport = lpuart_ports[co->index];
+if (sport == NULL)
+return -ENODEV;
+
+if (options)
+uart_parse_options(options, &baud, &parity, &bits, &flow);
+else
+lpuart_console_get_options(sport, &baud, &parity, &bits);
+
+lpuart_setup_watermark(sport);
+
+return uart_set_options(&sport->port, co, baud, parity, bits, flow);
+}
+
+static struct uart_driver lpuart_reg;
+static struct console lpuart_console = {
+.name= DEV_NAME,
+.write= lpuart_console_write,
+.device= uart_console_device,
+.setup= lpuart_console_setup,
+.flags= CON_PRINTBUFFER,
+.index= -1,
+.data= &lpuart_reg,
+};
+
+#define LPUART_CONSOLE(&lpuart_console)
+#else
+#define LPUART_CONSOLENULL
+#endif
+
+static struct uart_driver lpuart_reg = {
+.owner= THIS_MODULE,
+.driver_name= DRIVER_NAME,
+.dev_name= DEV_NAME,
+.nr= ARRAY_SIZE(lpuart_ports),
+.cons= LPUART_CONSOLE,
+};
+
+static int lpuart_probe(struct platform_device *pdev)
+{
+struct device_node *np = pdev->dev.of_node;
+struct lpuart_port *sport;
+struct resource *res;
+int ret;
+
+sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
+if (!sport)
+return -ENOMEM;
+
+pdev->dev.coherent_dma_mask = 0;
+
+ret = of_alias_get_id(np, "serial");
+if (ret < 0) {
+dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
+return ret;
+}
+sport->port.line = ret;
+
+res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+if (!res)
+return -ENODEV;
+
+sport->port.mapbase = res->start;
+sport->port.membase = devm_ioremap_resource(&pdev->dev, res);
+if (IS_ERR(sport->port.membase))
+return PTR_ERR(sport->port.membase);
+
+sport->port.dev = &pdev->dev;
+sport->port.type = PORT_LPUART;
+sport->port.iotype = UPIO_MEM;
+sport->port.irq = platform_get_irq(pdev, 0);
+sport->port.ops = &lpuart_pops;
+sport->port.flags = UPF_BOOT_AUTOCONF;
+
+sport->clk = devm_clk_get(&pdev->dev, "ipg");
+if (IS_ERR(sport->clk)) {
+ret = PTR_ERR(sport->clk);
+dev_err(&pdev->dev, "failed to get uart clk: %d\n", ret);
+return ret;
+}
+
+ret = clk_prepare_enable(sport->clk);
+if (ret) {
+dev_err(&pdev->dev, "failed to enable uart clk: %d\n", ret);
+return ret;
+}
+
+sport->port.uartclk = clk_get_rate(sport->clk);
+
+lpuart_ports[sport->port.line] = sport;
+
+platform_set_drvdata(pdev, &sport->port);
+
+ret = uart_add_one_port(&lpuart_reg, &sport->port);
+if (ret) {
+clk_disable_unprepare(sport->clk);
+return ret;
+}
+
+return 0;
+}
+
+static int lpuart_remove(struct platform_device *pdev)
+{
+struct lpuart_port *sport = platform_get_drvdata(pdev);
+
+uart_remove_one_port(&lpuart_reg, &sport->port);
+
+clk_disable_unprepare(sport->clk);
+
+return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int lpuart_suspend(struct device *dev)
+{
+struct lpuart_port *sport = dev_get_drvdata(dev);
+
+uart_suspend_port(&lpuart_reg, &sport->port);
+
+return 0;
+}
+
+static int lpuart_resume(struct device *dev)
+{
+struct lpuart_port *sport = dev_get_drvdata(dev);
+
+uart_resume_port(&lpuart_reg, &sport->port);
+
+return 0;
+}
+#endif
+
+static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume);
+
+static struct platform_driver lpuart_driver = {
+.probe= lpuart_probe,
+.remove= lpuart_remove,
+.driver= {
+.name= "fsl-lpuart",
+.owner= THIS_MODULE,
+.of_match_table = lpuart_dt_ids,
+.pm= &lpuart_pm_ops,
+},
+};
+
+static int __init lpuart_serial_init(void)
+{
+int ret;
+
+pr_info("serial: Freescale lpuart driver\n");
+
+ret = uart_register_driver(&lpuart_reg);
+if (ret)
+return ret;
+
+ret = platform_driver_register(&lpuart_driver);
+if (ret)
+uart_unregister_driver(&lpuart_reg);
+
+return 0;
+}
+
+static void __exit lpuart_serial_exit(void)
+{
+platform_driver_unregister(&lpuart_driver);
+uart_unregister_driver(&lpuart_reg);
+}
+
+module_init(lpuart_serial_init);
+module_exit(lpuart_serial_exit);
+
+MODULE_DESCRIPTION("Freescale lpuart serial port driver");
+MODULE_LICENSE("GPL v2");
diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h
index 74c2bf7..c8eaeb5 100644
--- a/include/uapi/linux/serial_core.h
+++ b/include/uapi/linux/serial_core.h
< at >< at > -226,4 +226,7 < at >< at >
 /* Rocketport EXPRESS/INFINITY */
 #define PORT_RP2102
 
+/* Freescale lpuart */
+#define PORT_LPUART103
+
 #endif /* _UAPILINUX_SERIAL_CORE_H */

[PATCH] serail: imx: add support for DTE mode

Huang Shijie — 2013-05-30T06:07:12

The uart works in the DCE mode by default, but sometime we need it
works at the DTE mode.

This patch adds the support for the DTE mode.

Signed-off-by: Huang Shijie <b32955< at >freescale.com>
---
 .../bindings/tty/serial/fsl-imx-uart.txt           |    3 +++
 drivers/tty/serial/imx.c                           |    6 ++++++
 2 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/Documentation/devicetree/bindings/tty/serial/fsl-imx-uart.txt b/Documentation/devicetree/bindings/tty/serial/fsl-imx-uart.txt
index b462d0c..c662eb3 100644
--- a/Documentation/devicetree/bindings/tty/serial/fsl-imx-uart.txt
+++ b/Documentation/devicetree/bindings/tty/serial/fsl-imx-uart.txt
< at >< at > -8,6 +8,8 < at >< at > Required properties:
 Optional properties:
 - fsl,uart-has-rtscts : Indicate the uart has rts and cts
 - fsl,irda-mode : Indicate the uart supports irda mode
+- fsl,dte-mode : Indicate the uart works in DTE mode. The uart works
+                  is DCE mode by default.
 
 Example:
 
< at >< at > -16,4 +18,5 < at >< at > serial< at >73fbc000 {
 reg = <0x73fbc000 0x4000>;
 interrupts = <31>;
 fsl,uart-has-rtscts;
+fsl,dte-mode;
 };
diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
index 72bc1db..381a2d7 100644
--- a/drivers/tty/serial/imx.c
+++ b/drivers/tty/serial/imx.c
< at >< at > -201,6 +201,7 < at >< at > struct imx_port {
 unsigned intold_status;
 inttxirq, rxirq, rtsirq;
 unsigned inthave_rtscts:1;
+unsigned intdte_mode:1;
 unsigned intuse_irda:1;
 unsigned intirda_inv_rx:1;
 unsigned intirda_inv_tx:1;
< at >< at > -1020,6 +1021,8 < at >< at > imx_set_termios(struct uart_port *port, struct ktermios *termios,
 
 ufcr = readl(sport->port.membase + UFCR);
 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
+if (sport->dte_mode)
+ufcr |= UFCR_DCEDTE;
 writel(ufcr, sport->port.membase + UFCR);
 
 writel(num, sport->port.membase + UBIR);
< at >< at > -1444,6 +1447,9 < at >< at > static int serial_imx_probe_dt(struct imx_port *sport,
 if (of_get_property(np, "fsl,irda-mode", NULL))
 sport->use_irda = 1;
 
+if (of_get_property(np, "fsl,dte-mode", NULL))
+sport->dte_mode = 1;
+
 sport->devdata = of_id->data;
 
 return 0;

[PATCH] serial: samsung: missing uart_unregister_driver() on error in s3c24xx_serial_modinit()

Wei Yongjun — 2013-05-29T05:47:09

From: Wei Yongjun <yongjun_wei< at >trendmicro.com.cn>

Add the missing uart_unregister_driver() before return from
s3c24xx_serial_modinit() in the error handling case.

Signed-off-by: Wei Yongjun <yongjun_wei< at >trendmicro.com.cn>
---
 drivers/tty/serial/samsung.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/tty/serial/samsung.c b/drivers/tty/serial/samsung.c
index 8942941..1c2b8c3 100644
--- a/drivers/tty/serial/samsung.c
+++ b/drivers/tty/serial/samsung.c
< at >< at > -1798,7 +1798,13 < at >< at > static int __init s3c24xx_serial_modinit(void)
 return ret;
 }
 
-return platform_driver_register(&samsung_serial_driver);
+ret = platform_driver_register(&samsung_serial_driver);
+if (ret < 0) {
+pr_err("Failed to register platform driver\n");
+uart_unregister_driver(&s3c24xx_uart_drv);
+}
+
+return ret;
 }
 
 static void __exit s3c24xx_serial_modexit(void)

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[PATCH] driver: tty: add missing unregister in err case

Libo Chen — 2013-05-29T02:33:16

when platform_driver_register broken, we should unregister ucc_uart_driver

Signed-off-by: Libo chen <libo.chen< at >huawei.com>
---
 drivers/tty/serial/ucc_uart.c |    4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/drivers/tty/serial/ucc_uart.c b/drivers/tty/serial/ucc_uart.c
index 7355303..f86f447 100644
--- a/drivers/tty/serial/ucc_uart.c
+++ b/drivers/tty/serial/ucc_uart.c
< at >< at > -1518,9 +1518,11 < at >< at > static int __init ucc_uart_init(void)
 }

 ret = platform_driver_register(&ucc_uart_of_driver);
-if (ret)
+if (ret) {
 printk(KERN_ERR
        "ucc-uart: could not register platform driver\n");
+uart_unregister_driver(&ucc_uart_driver);
+}

 return ret;
 }