gmane.linux.ports.sh.devel

(unknown)

robothroli company — 2012-05-25T13:45:54

 i am robothroli, Purchase manager from roli Merchant Ltd. We are
Import/export Company based in taiwan. We are interested in purchasing
your product and I would like to make an inquiry. Please inform me on:

Sample availability and price
Minimum order quantity
FOB Prices

Sincerely
Purchase Manager
robothroli



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[PATCH] sh: fix sh7724 compilation

Guennadi Liakhovetski — 2012-05-25T14:24:53

Fix compile breakage:

arch/sh/kernel/process.c: In function 'arch_dup_task_struct':
arch/sh/kernel/process.c:23: error: implicit declaration of function 'unlazy_fpu'

Presumably, other 32-bit FPU-enabled SuperH SoCs are affected too.

Signed-off-by: Guennadi Liakhovetski <g.liakhovetski< at >gmx.de>
---

This is for a 4-days old next, discard if already fixed.

diff --git a/arch/sh/kernel/process.c b/arch/sh/kernel/process.c
index 9b7a459..02a6f07 100644
--- a/arch/sh/kernel/process.c
+++ b/arch/sh/kernel/process.c
< at >< at > -5,6 +5,8 < at >< at >
 #include <linux/export.h>
 #include <linux/stackprotector.h>
 
+#include <asm/fpu.h>
+
 struct kmem_cache *task_xstate_cachep = NULL;
 unsigned int xstate_size;
 
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[PATCH] clocksource: em_sti: Emma Mobile STI driver V3

Magnus Damm — 2012-05-25T07:03:44

From: Magnus Damm <damm< at >opensource.se>

This is V3 of the Emma Mobile STI timer driver.

The STI hardware is based on a single 48-bit 32kHz
counter that together with two individual compare
registers can generate interrupts. There are no
timer operating modes selectable which means that
the timer can not clear on match.

This driver is providing clocksource support for the
48-bit counter. Clockevents are also supported using
the same timer in oneshot mode.

Signed-off-by: Magnus Damm <damm< at >opensource.se>
---

 Thanks to Thomas Gleixner for his reviews!

 Changes since V2 :
 - use raw spinlocks
 - get rid of periodic support
 - get rid of now unused private data
 - rename em_sti_update() to em_sti_set_next()

 Changes since V1 :
 - removed unused early timer cruft
 - reduce number of functions
 - use request_irq() instead setup_irq() since we run late during boot
 - replace confusing flags with perhaps equally confusing active[] array
 - use clockevents_config_and_register() for registration
 - update frequency with clockevents_config()
 - use 2 ticks as minimum
 - verify oneshot timer and return error to clock event layer

 Verified V2 in the following modes on EMEV2:
 - clocksource only
 - clockevent in periodic mode only
 - clocksource and clockevent in periodic mode
 - clocksource and clockevent in oneshot mode

 arch/arm/mach-shmobile/Kconfig |    6 
 drivers/clocksource/Makefile   |    1 
 drivers/clocksource/em_sti.c   |  399 ++++++++++++++++++++++++++++++++++++++++
 3 files changed, 406 insertions(+)

--- 0008/arch/arm/mach-shmobile/Kconfig
+++ work/arch/arm/mach-shmobile/Kconfig2012-05-25 15:18:20.000000000 +0900
< at >< at > -183,6 +183,12 < at >< at > config SH_TIMER_TMU
 help
   This enables build of the TMU timer driver.
 
+config EM_TIMER_STI
+bool "STI timer driver"
+default y
+help
+  This enables build of the STI timer driver.
+
 endmenu
 
 config SH_CLK_CPG
--- 0001/drivers/clocksource/Makefile
+++ work/drivers/clocksource/Makefile2012-05-25 15:18:20.000000000 +0900
< at >< at > -6,6 +6,7 < at >< at > obj-$(CONFIG_CS5535_CLOCK_EVENT_SRC)+=
 obj-$(CONFIG_SH_TIMER_CMT)+= sh_cmt.o
 obj-$(CONFIG_SH_TIMER_MTU2)+= sh_mtu2.o
 obj-$(CONFIG_SH_TIMER_TMU)+= sh_tmu.o
+obj-$(CONFIG_EM_TIMER_STI)+= em_sti.o
 obj-$(CONFIG_CLKBLD_I8253)+= i8253.o
 obj-$(CONFIG_CLKSRC_MMIO)+= mmio.o
 obj-$(CONFIG_DW_APB_TIMER)+= dw_apb_timer.o
--- /dev/null
+++ work/drivers/clocksource/em_sti.c2012-05-25 15:59:02.000000000 +0900
< at >< at > -0,0 +1,399 < at >< at >
+/*
+ * Emma Mobile Timer Support - STI
+ *
+ *  Copyright (C) 2012 Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/irq.h>
+#include <linux/err.h>
+#include <linux/delay.h>
+#include <linux/clocksource.h>
+#include <linux/clockchips.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+
+enum { USER_CLOCKSOURCE, USER_CLOCKEVENT, USER_NR };
+
+struct em_sti_priv {
+void __iomem *base;
+struct clk *clk;
+struct platform_device *pdev;
+unsigned int active[USER_NR];
+unsigned long rate;
+raw_spinlock_t lock;
+struct clock_event_device ced;
+struct clocksource cs;
+};
+
+#define STI_CONTROL 0x00
+#define STI_COMPA_H 0x10
+#define STI_COMPA_L 0x14
+#define STI_COMPB_H 0x18
+#define STI_COMPB_L 0x1c
+#define STI_COUNT_H 0x20
+#define STI_COUNT_L 0x24
+#define STI_COUNT_RAW_H 0x28
+#define STI_COUNT_RAW_L 0x2c
+#define STI_SET_H 0x30
+#define STI_SET_L 0x34
+#define STI_INTSTATUS 0x40
+#define STI_INTRAWSTATUS 0x44
+#define STI_INTENSET 0x48
+#define STI_INTENCLR 0x4c
+#define STI_INTFFCLR 0x50
+
+static inline unsigned long em_sti_read(struct em_sti_priv *p, int offs)
+{
+return ioread32(p->base + offs);
+}
+
+static inline void em_sti_write(struct em_sti_priv *p, int offs,
+unsigned long value)
+{
+iowrite32(value, p->base + offs);
+}
+
+static int em_sti_enable(struct em_sti_priv *p)
+{
+int ret;
+
+/* enable clock */
+ret = clk_enable(p->clk);
+if (ret) {
+dev_err(&p->pdev->dev, "cannot enable clock\n");
+return ret;
+}
+
+/* configure channel, periodic mode and maximum timeout */
+p->rate = clk_get_rate(p->clk);
+
+/* reset the counter */
+em_sti_write(p, STI_SET_H, 0x40000000);
+em_sti_write(p, STI_SET_L, 0x00000000);
+
+/* mask and clear pending interrupts */
+em_sti_write(p, STI_INTENCLR, 3);
+em_sti_write(p, STI_INTFFCLR, 3);
+
+/* enable updates of counter registers */
+em_sti_write(p, STI_CONTROL, 1);
+
+return 0;
+}
+
+static void em_sti_disable(struct em_sti_priv *p)
+{
+/* mask interrupts */
+em_sti_write(p, STI_INTENCLR, 3);
+
+/* stop clock */
+clk_disable(p->clk);
+}
+
+static cycle_t em_sti_count(struct em_sti_priv *p)
+{
+cycle_t ticks;
+unsigned long flags;
+
+/* the STI hardware buffers the 48-bit count, but to
+ * break it out into two 32-bit access the registers
+ * must be accessed in a certain order.
+ * Always read STI_COUNT_H before STI_COUNT_L.
+ */
+raw_spin_lock_irqsave(&p->lock, flags);
+ticks = (cycle_t)(em_sti_read(p, STI_COUNT_H) & 0xffff) << 32;
+ticks |= em_sti_read(p, STI_COUNT_L);
+raw_spin_unlock_irqrestore(&p->lock, flags);
+
+return ticks;
+}
+
+static cycle_t em_sti_set_next(struct em_sti_priv *p, cycle_t next)
+{
+unsigned long flags;
+
+raw_spin_lock_irqsave(&p->lock, flags);
+
+/* mask compare A interrupt */
+em_sti_write(p, STI_INTENCLR, 1);
+
+/* update compare A value */
+em_sti_write(p, STI_COMPA_H, next >> 32);
+em_sti_write(p, STI_COMPA_L, next & 0xffffffff);
+
+/* clear compare A interrupt source */
+em_sti_write(p, STI_INTFFCLR, 1);
+
+/* unmask compare A interrupt */
+em_sti_write(p, STI_INTENSET, 1);
+
+raw_spin_unlock_irqrestore(&p->lock, flags);
+
+return next;
+}
+
+static irqreturn_t em_sti_interrupt(int irq, void *dev_id)
+{
+struct em_sti_priv *p = dev_id;
+
+p->ced.event_handler(&p->ced);
+return IRQ_HANDLED;
+}
+
+static int em_sti_start(struct em_sti_priv *p, unsigned int user)
+{
+unsigned long flags;
+int used_before;
+int ret = 0;
+
+raw_spin_lock_irqsave(&p->lock, flags);
+used_before = p->active[USER_CLOCKSOURCE] | p->active[USER_CLOCKEVENT];
+if (!used_before)
+ret = em_sti_enable(p);
+
+if (!ret)
+p->active[user] = 1;
+raw_spin_unlock_irqrestore(&p->lock, flags);
+
+return ret;
+}
+
+static void em_sti_stop(struct em_sti_priv *p, unsigned int user)
+{
+unsigned long flags;
+int used_before, used_after;
+
+raw_spin_lock_irqsave(&p->lock, flags);
+used_before = p->active[USER_CLOCKSOURCE] | p->active[USER_CLOCKEVENT];
+p->active[user] = 0;
+used_after = p->active[USER_CLOCKSOURCE] | p->active[USER_CLOCKEVENT];
+
+if (used_before && !used_after)
+em_sti_disable(p);
+raw_spin_unlock_irqrestore(&p->lock, flags);
+}
+
+static struct em_sti_priv *cs_to_em_sti(struct clocksource *cs)
+{
+return container_of(cs, struct em_sti_priv, cs);
+}
+
+static cycle_t em_sti_clocksource_read(struct clocksource *cs)
+{
+return em_sti_count(cs_to_em_sti(cs));
+}
+
+static int em_sti_clocksource_enable(struct clocksource *cs)
+{
+int ret;
+struct em_sti_priv *p = cs_to_em_sti(cs);
+
+ret = em_sti_start(p, USER_CLOCKSOURCE);
+if (!ret)
+__clocksource_updatefreq_hz(cs, p->rate);
+return ret;
+}
+
+static void em_sti_clocksource_disable(struct clocksource *cs)
+{
+em_sti_stop(cs_to_em_sti(cs), USER_CLOCKSOURCE);
+}
+
+static void em_sti_clocksource_resume(struct clocksource *cs)
+{
+em_sti_clocksource_enable(cs);
+}
+
+static int em_sti_register_clocksource(struct em_sti_priv *p)
+{
+struct clocksource *cs = &p->cs;
+
+memset(cs, 0, sizeof(*cs));
+cs->name = dev_name(&p->pdev->dev);
+cs->rating = 200;
+cs->read = em_sti_clocksource_read;
+cs->enable = em_sti_clocksource_enable;
+cs->disable = em_sti_clocksource_disable;
+cs->suspend = em_sti_clocksource_disable;
+cs->resume = em_sti_clocksource_resume;
+cs->mask = CLOCKSOURCE_MASK(48);
+cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
+
+dev_info(&p->pdev->dev, "used as clock source\n");
+
+/* Register with dummy 1 Hz value, gets updated in ->enable() */
+clocksource_register_hz(cs, 1);
+return 0;
+}
+
+static struct em_sti_priv *ced_to_em_sti(struct clock_event_device *ced)
+{
+return container_of(ced, struct em_sti_priv, ced);
+}
+
+static void em_sti_clock_event_mode(enum clock_event_mode mode,
+    struct clock_event_device *ced)
+{
+struct em_sti_priv *p = ced_to_em_sti(ced);
+
+/* deal with old setting first */
+switch (ced->mode) {
+case CLOCK_EVT_MODE_ONESHOT:
+em_sti_stop(p, USER_CLOCKEVENT);
+break;
+default:
+break;
+}
+
+switch (mode) {
+case CLOCK_EVT_MODE_ONESHOT:
+dev_info(&p->pdev->dev, "used for oneshot clock events\n");
+em_sti_start(p, USER_CLOCKEVENT);
+clockevents_config(&p->ced, p->rate);
+break;
+case CLOCK_EVT_MODE_SHUTDOWN:
+case CLOCK_EVT_MODE_UNUSED:
+em_sti_stop(p, USER_CLOCKEVENT);
+break;
+default:
+break;
+}
+}
+
+static int em_sti_clock_event_next(unsigned long delta,
+   struct clock_event_device *ced)
+{
+struct em_sti_priv *p = ced_to_em_sti(ced);
+cycle_t next;
+int safe;
+
+next = em_sti_set_next(p, em_sti_count(p) + delta);
+safe = em_sti_count(p) < (next - 1);
+
+return !safe;
+}
+
+static void em_sti_register_clockevent(struct em_sti_priv *p)
+{
+struct clock_event_device *ced = &p->ced;
+
+memset(ced, 0, sizeof(*ced));
+ced->name = dev_name(&p->pdev->dev);
+ced->features = CLOCK_EVT_FEAT_ONESHOT;
+ced->rating = 200;
+ced->cpumask = cpumask_of(0);
+ced->set_next_event = em_sti_clock_event_next;
+ced->set_mode = em_sti_clock_event_mode;
+
+dev_info(&p->pdev->dev, "used for clock events\n");
+
+/* Register with dummy 1 Hz value, gets updated in ->set_mode() */
+clockevents_config_and_register(ced, 1, 2, 0xffffffff);
+}
+
+static int __devinit em_sti_probe(struct platform_device *pdev)
+{
+struct em_sti_priv *p;
+struct resource *res;
+int irq, ret;
+
+p = kzalloc(sizeof(*p), GFP_KERNEL);
+if (p == NULL) {
+dev_err(&pdev->dev, "failed to allocate driver data\n");
+ret = -ENOMEM;
+goto err0;
+}
+
+p->pdev = pdev;
+platform_set_drvdata(pdev, p);
+
+res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+if (!res) {
+dev_err(&pdev->dev, "failed to get I/O memory\n");
+ret = -EINVAL;
+goto err0;
+}
+
+irq = platform_get_irq(pdev, 0);
+if (irq < 0) {
+dev_err(&pdev->dev, "failed to get irq\n");
+ret = -EINVAL;
+goto err0;
+}
+
+/* map memory, let base point to the STI instance */
+p->base = ioremap_nocache(res->start, resource_size(res));
+if (p->base == NULL) {
+dev_err(&pdev->dev, "failed to remap I/O memory\n");
+ret = -ENXIO;
+goto err0;
+}
+
+/* get hold of clock */
+p->clk = clk_get(&pdev->dev, "sclk");
+if (IS_ERR(p->clk)) {
+dev_err(&pdev->dev, "cannot get clock\n");
+ret = PTR_ERR(p->clk);
+goto err1;
+}
+
+if (request_irq(irq, em_sti_interrupt,
+IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
+dev_name(&pdev->dev), p)) {
+dev_err(&pdev->dev, "failed to request low IRQ\n");
+ret = -ENOENT;
+goto err2;
+}
+
+raw_spin_lock_init(&p->lock);
+em_sti_register_clockevent(p);
+em_sti_register_clocksource(p);
+return 0;
+
+err2:
+clk_put(p->clk);
+err1:
+iounmap(p->base);
+err0:
+kfree(p);
+return ret;
+}
+
+static int __devexit em_sti_remove(struct platform_device *pdev)
+{
+return -EBUSY; /* cannot unregister clockevent and clocksource */
+}
+
+static struct platform_driver em_sti_device_driver = {
+.probe= em_sti_probe,
+.remove= __devexit_p(em_sti_remove),
+.driver= {
+.name= "em_sti",
+}
+};
+
+module_platform_driver(em_sti_device_driver);
+
+MODULE_AUTHOR("Magnus Damm");
+MODULE_DESCRIPTION("Renesas Emma Mobile STI Timer Driver");
+MODULE_LICENSE("GPL v2");
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[PATCH] lib/decompress_unxz.c: removing all memory helper functions

T Makphaibulchoke — 2012-05-24T16:03:56

The patch cleans up the file lib/decompress_unxz.c by removing all memory
helper functions, e.g., memmove.  By doing so, any architecture's preboot
environment supporting the XZ decompression needs to define its own copy of
any of the missing memory helper functions.

The patch makes sure that all 4 architectures' preboot currently supporting
the XZ decompressor, arm, s390, sh and x86, build without error when using
the XZ compression.

Adding a prototype for the memcmp function required by the XZ decompressor to
workaround compiler's implicit type error.  Also removing both the memmove and
memcpy defines workaround, to disable lib/decompress_unxz.c from duplicating
both functions.

Adding the missing memcmp function, required by the XZ decompressor, to the
s390 preboot environment.

Adding both the missing memmove and memcmp functions, required by the XZ
decompressor, to the sh preboot environment.

Adding the missing memmove function, required by XZ decompressor, to the x86
preboot environment.

Signed-off-by: T. Makphaibulchoke <tmac< at >hp.com>
---
 arch/arm/boot/compressed/decompress.c |    3 +-
 arch/s390/boot/compressed/misc.c      |   14 +++++
 arch/sh/boot/compressed/misc.c        |   32 ++++++++++++
 arch/x86/boot/compressed/string.c     |   18 +++++++
 lib/decompress_unxz.c                 |   85 +++++++--------------------------
 lib/xz/xz_private.h                   |    7 ++-
 6 files changed, 87 insertions(+), 72 deletions(-)

diff --git a/arch/arm/boot/compressed/decompress.c b/arch/arm/boot/compressed/decompress.c
index f41b38c..80a2219 100644
--- a/arch/arm/boot/compressed/decompress.c
+++ b/arch/arm/boot/compressed/decompress.c
< at >< at > -9,6 +9,7 < at >< at >
 extern unsigned long free_mem_ptr;
 extern unsigned long free_mem_end_ptr;
 extern void error(char *);
+extern int memcmp(const void *, const void *, size_t);
 
 #define STATIC static
 #define STATIC_RW_DATA/* non-static please */
< at >< at > -45,8 +46,6 < at >< at > extern void error(char *);
 #endif
 
 #ifdef CONFIG_KERNEL_XZ
-#define memmove memmove
-#define memcpy memcpy
 #include "../../../../lib/decompress_unxz.c"
 #endif
 
diff --git a/arch/s390/boot/compressed/misc.c b/arch/s390/boot/compressed/misc.c
index 465eca7..b966af3 100644
--- a/arch/s390/boot/compressed/misc.c
+++ b/arch/s390/boot/compressed/misc.c
< at >< at > -87,6 +87,20 < at >< at > void *memcpy(void *__dest, __const void *__src, size_t __n)
 return __builtin_memcpy(__dest, __src, __n);
 }
 
+int memcmp(const void *cs, const void *ct, size_t count)
+{
+const unsigned char *su1, *su2;
+int res = 0;
+
+for (su1 = cs, su2 = ct; 0 < count; ++su1, ++su2, count--) {
+res = *su1 - *su2;
+if (res != 0)
+break;
+}
+
+return res;
+}
+
 void *memmove(void *__dest, __const void *__src, size_t __n)
 {
 char *d;
diff --git a/arch/sh/boot/compressed/misc.c b/arch/sh/boot/compressed/misc.c
index 95470a4..09e740d 100644
--- a/arch/sh/boot/compressed/misc.c
+++ b/arch/sh/boot/compressed/misc.c
< at >< at > -94,6 +94,38 < at >< at > void* memcpy(void* __dest, __const void* __src,
 return __dest;
 }
 
+void *memmove(void *dest, const void *src, size_t size)
+{
+uint8_t *d = dest;
+const uint8_t *s = src;
+size_t i;
+
+if (d < s) {
+for (i = 0; i < size; ++i)
+d[i] = s[i];
+} else if (d > s) {
+i = size;
+while (i-- > 0)
+d[i] = s[i];
+}
+
+return dest;
+}
+
+int memcmp(const void *cs, const void *ct, size_t count)
+{
+const unsigned char *su1, *su2;
+int res = 0;
+
+for (su1 = cs, su2 = ct; 0 < count; ++su1, ++su2, count--) {
+res = *su1 - *su2;
+if (res != 0)
+break;
+}
+
+return res;
+}
+
 static void error(char *x)
 {
 puts("\n\n");
diff --git a/arch/x86/boot/compressed/string.c b/arch/x86/boot/compressed/string.c
index ffb9c5c..2f4fdfa 100644
--- a/arch/x86/boot/compressed/string.c
+++ b/arch/x86/boot/compressed/string.c
< at >< at > -8,4 +8,22 < at >< at > int memcmp(const void *s1, const void *s2, size_t len)
 return diff;
 }
 
+void *memmove(void *dest, const void *src, size_t size)
+{
+uint8_t *d = dest;
+const uint8_t *s = src;
+size_t i;
+
+if (d < s) {
+for (i = 0; i < size; ++i)
+d[i] = s[i];
+} else if (d > s) {
+i = size;
+while (i-- > 0)
+d[i] = s[i];
+}
+
+return dest;
+}
+
 #include "../string.c"
diff --git a/lib/decompress_unxz.c b/lib/decompress_unxz.c
index 9f34eb5..bd09c2f 100644
--- a/lib/decompress_unxz.c
+++ b/lib/decompress_unxz.c
< at >< at > -160,75 +160,24 < at >< at >
 #define vfree(ptr) do { if (ptr != NULL) free(ptr); } while (0)
 
 /*
- * FIXME: Not all basic memory functions are provided in architecture-specific
- * files (yet). We define our own versions here for now, but this should be
- * only a temporary solution.
+ * To support XZ-decompressed file in preboot environment, the following
+ * functions, memcmp, memset, memcpy and memmove, needed to be defined in
+ * architecture-specific preboot environment.
+ *
+ * Not all architecture-specific preboot environment currently support all of
+ * the above functions.
+ *
+ * If your architecture does not support any of the above functions, simply
+ * add the missing function(s) to the architecture-specific preboot string.c
+ * or misc.c file, for example arch/x86/boot/compressed/string.c for the x86
+ * architecture.
+ *
+ * memcmp is not used much and any remotely sane implementation is fast enough.
+ * memmove speed matters in multi-call mode.  Any missing memory helper
+ * functions, including a decent implementation of an in-place memmove function
+ * could be found in lib/string.c
  *
- * memeq and memzero are not used much and any remotely sane implementation
- * is fast enough. memcpy/memmove speed matters in multi-call mode, but
- * the kernel image is decompressed in single-call mode, in which only
- * memcpy speed can matter and only if there is a lot of uncompressible data
- * (LZMA2 stores uncompressible chunks in uncompressed form). Thus, the
- * functions below should just be kept small; it's probably not worth
- * optimizing for speed.
- */
-
-#ifndef memeq
-static bool memeq(const void *a, const void *b, size_t size)
-{
-const uint8_t *x = a;
-const uint8_t *y = b;
-size_t i;
-
-for (i = 0; i < size; ++i)
-if (x[i] != y[i])
-return false;
-
-return true;
-}
-#endif
-
-#ifndef memzero
-static void memzero(void *buf, size_t size)
-{
-uint8_t *b = buf;
-uint8_t *e = b + size;
-
-while (b != e)
-*b++ = '\0';
-}
-#endif
-
-#ifndef memmove
-/* Not static to avoid a conflict with the prototype in the Linux headers. */
-void *memmove(void *dest, const void *src, size_t size)
-{
-uint8_t *d = dest;
-const uint8_t *s = src;
-size_t i;
-
-if (d < s) {
-for (i = 0; i < size; ++i)
-d[i] = s[i];
-} else if (d > s) {
-i = size;
-while (i-- > 0)
-d[i] = s[i];
-}
-
-return dest;
-}
-#endif
-
-/*
- * Since we need memmove anyway, would use it as memcpy too.
- * Commented out for now to avoid breaking things.
  */
-/*
-#ifndef memcpy
-#define memcpy memmove
-#endif
-*/
 
 #include "xz/xz_crc32.c"
 #include "xz/xz_dec_stream.c"
diff --git a/lib/xz/xz_private.h b/lib/xz/xz_private.h
index 482b90f..a997dca 100644
--- a/lib/xz/xz_private.h
+++ b/lib/xz/xz_private.h
< at >< at > -37,9 +37,12 < at >< at >
 #ifdef CONFIG_XZ_DEC_SPARC
 #define XZ_DEC_SPARC
 #endif
-#define memeq(a, b, size) (memcmp(a, b, size) == 0)
-#define memzero(buf, size) memset(buf, 0, size)
 #endif
+/* Make all environments, including preboot, use memcmp for memeq */
+#define memeq(a, b, size) (memcmp(a, b, size) == 0)
+/* To suppress redefine warning in some architecture's preboot */
+#undef memzero
+#define memzero(buf, size) memset(buf, 0, size)
 #define get_le32(p) le32_to_cpup((const uint32_t *)(p))
 #else
 /*

[PATCH] ARM: mach-shmobile: add missing GPIO IRQ configuration on mackerel

Guennadi Liakhovetski — 2012-05-24T13:18:44

SDHI0 card-detect GPIO IRQ on mackarel currently works, because it is the
default configuration of IRQ26. However, we should not rely on this and
should configure the function explicitly.

Signed-off-by: Guennadi Liakhovetski <g.liakhovetski< at >gmx.de>
---
 arch/arm/mach-shmobile/board-mackerel.c |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index b577f7c..150122a 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
< at >< at > -1512,6 +1512,9 < at >< at > static void __init mackerel_init(void)
 gpio_request(GPIO_FN_SDHID0_1, NULL);
 gpio_request(GPIO_FN_SDHID0_0, NULL);
 
+/* SDHI0 PORT172 card-detect IRQ26 */
+gpio_request(GPIO_FN_IRQ26_172, NULL);
+
 #if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
 /* enable SDHI1 */
 gpio_request(GPIO_FN_SDHICMD1, NULL);

[GIT PULL] sh updates for 3.5-rc1

Paul Mundt — 2012-05-22T12:13:13

The following changes since commit 42ea7d7f2a7356962022cdd124d9043c488ca5e2:

  Merge branch 'fixes' of git://git.linaro.org/people/rmk/linux-arm (2012-05-17 16:52:29 -0700)

are available in the git repository at:

  git://github.com/pmundt/linux-sh.git tags/sh-for-linus

for you to fetch changes up to 5f19f14fed7786652b9617c633db101d26a42251:

  sh: intc: Kill off special reservation interface. (2012-05-22 19:07:55 +0900)

----------------------------------------------------------------
SuperH updates for 3.5-rc1 merge window

- New CPUs: SH7734 (SH-4A), SH7264 and SH7269 (SH-2A)
- New boards: RSK2+SH7264, RSK2+SH7269
- Unbreaking kgdb for SMP
- Consolidation of _32/_64 page fault handling.
- watchdog and legacy DMA chainsawing, part 1
- Conversion to evt2irq() hwirq lookup, to support relocation
  of vectored IRQs for irqdomains.

----------------------------------------------------------------
Filippo Arcidiacono (1):
      sh: initial stack protector support.

Kautuk Consul (1):
      sh/mm/fault_32.c: Port OOM changes to do_page_fault

Nobuhiro Iwamatsu (7):
      sh: sh4a: Change the specification method of IRQ to SCIx_IRQ_MUXED
      sh: sh4: Change the specification method of IRQ to SCIx_IRQ_MUXED
      sh: sh3: Change the specification method of IRQ to SCIx_IRQ_MUXED
      sh: sh2: Change the specification method of IRQ to SCIx_IRQ_MUXED
      sh: Add initial support for SH7734 CPU subtype
      sh: Add support pinmux for SH7734
      sh: Fix mistake of the member variable of plat_sci_port for SH7343

Paul Mundt (85):
      sh: kgdb: Fix up basic SMP support.
      sh: kgdb: Individual register get/set support.
      sh: kgdb: Fill out sleeping_thread_to_gdb_regs() state.
      sh: kgdb: Fix up NULL pointer deref by kgdb_nmicallback.
      sh: kgdb: Unset CACHE_FLUSH_IS_SAFE for SMP.
      sh: clkfwk: Support variable size accesses for MSTP clocks.
      sh64: Port OOM changes to do_page_fault
      sh64: Kill off dead page fault debug cruft.
      MAINTAINERS: Update git URL for SH.
      sh: clkfwk: Support variable size accesses for div4/div6 clocks.
      Merge branch 'common/clkfwk' into sh-latest
      Merge branch 'sh/kgdb' into sh-latest
      Merge branches 'sh/st-integration' and 'sh/stackprotector' into sh-latest
      sh64: Kill off unused trap_no/error_code from thread_struct.
      Merge branch 'sh/rsk-updates' into sh-latest
      sh: Provide stubbed I/O routines for NO_IOPORT case.
      watchdog: shwdt: Migrate from reboot notifier to platform shutdown.
      watchdog: shwdt: Conversion to watchdog core.
      watchdog: shwdt: Migrate to per-device locking.
      watchdog: shwdt: Trim down private data structure.
      watchdog: shwdt: Basic clock framework support.
      watchdog: shwdt: Preliminary runtime PM support.
      watchdog: shwdt: Use finer grained clock control.
      Merge branches 'sh/wdt' and 'sh/rsk-updates' into sh-latest
      sh: Fix up comment noise in sh7269 pinmux code.
      sh: Tidy up and generalize page fault error paths.
      sh64: Provide EXPEVT helper.
      sh: Support thread fault code encoding.
      sh64: Utilize thread fault code encoding.
      sh: Ensure fixmap and store queue space can co-exist.
      sh64: Kill off unused fixed I/O mapping window.
      sh: Enable shared page fault handler for _32/_64.
      sh64: Migrate to __update_tlb() API.
      sh64: Invert page fault fast-path error path values.
      sh64: Fix up caller-save register settings for fast-path.
      sh64: Tidy up and consolidate the TLB miss fast path.
      sh64: Set additional fault code values.
      sh: sh7786 evt2irq migration.
      sh: sh7343 evt2irq migration.
      sh: sh7366 evt2irq migration.
      sh: sh7722 evt2irq migration.
      sh: sh7723 evt2irq migration.
      sh: sh7724 evt2irq migration.
      sh: sh7757 evt2irq migration.
      sh: sh7763 evt2irq migration.
      sh: sh7770 evt2irq migration.
      sh: sh7780 evt2irq migration.
      sh: sh7785 evt2irq migration.
      sh: sh-x3 evt2irq migration.
      sh: sh4-202 evt2irq migration.
      sh: sh7750 evt2irq migration.
      sh: sh7760 evt2irq migration.
      sh: sh7705 evt2irq migration.
      sh: sh7706/sh7707/sh7709/sh7709 evt2irq migration.
      sh: sh7710/sh7712 evt2irq migration.
      sh: sh7720 evt2irq migration.
      sh: edosk7705 evt2irq migration.
      sh: edosk7760 evt2irq migration.
      sh: espt evt2irq migration.
      sh: magicpanelr2 evt2irq migration.
      sh: sh7757lcr evt2irq migration.
      sh: mach-se evt2irq migration.
      sh: hp6xx evt2irq migration.
      sh: sh7785lcr evt2irq migration.
      sh: urquell evt2irq migration.
      sh: ap325rxa evt2irq migration.
      sh: ecovec24 evt2irq migration.
      sh: kfr2r09 evt2irq migration.
      sh: landisk evt2irq migration.
      sh: migor evt2irq migration.
      sh: sdk7780 evt2irq migration.
      sh: sh7763rdp evt2irq migration.
      sh: cpu dma evt2irq migration.
      sh: legacy PCI evt2irq migration.
      Merge branch 'sh/evt2irq-migration' into sh-latest
      serial: sh-sci: Fix for port types without BRI interrupts.
      Revert "sh: Ensure fixmap and store queue space can co-exist."
      sh64: Fix up vmalloc fault range check.
      sh: Move sh4a dma header from cpu-sh4 to cpu-sh4a.
      sh: Tidy up some of the cpu legacy dma header mess.
      sh: Kill off MAX_DMA_ADDRESS leftovers.
      sh: dma: More legacy cpu dma chainsawing.
      sh: Kill off machvec IRQ hinting.
      sh: Enable PIO API for hp6xx and se770x.
      sh: intc: Kill off special reservation interface.

Phil Edworthy (6):
      sh: Add sh7264 device
      sh: Add RSK2+SH7264 board
      sh: Add pinmux for sh7264
      sh: Add sh7269 device
      sh: Add RSK2+SH7269 board
      sh: Add pinmux for sh7269

Shimoda, Yoshihiro (2):
      serial: sh-sci: modify sci_break_ctl()
      serial: sh-sci: Update break_ctl handling for all SCSPTR-capable regtypes.

Stuart Menefy (2):
      sh: Improve oops error reporting
      sh: Move board specific options into the Board support menu

 MAINTAINERS                                        |    2 +-
 arch/sh/Kconfig                                    |   45 +-
 arch/sh/Makefile                                   |    4 +
 arch/sh/boards/Kconfig                             |    7 +-
 arch/sh/boards/board-edosk7705.c                   |    4 +-
 arch/sh/boards/board-edosk7760.c                   |   16 +-
 arch/sh/boards/board-espt.c                        |    3 +-
 arch/sh/boards/board-magicpanelr2.c                |   27 +-
 arch/sh/boards/board-polaris.c                     |    1 -
 arch/sh/boards/board-secureedge5410.c              |    1 -
 arch/sh/boards/board-sh7757lcr.c                   |   27 +-
 arch/sh/boards/board-sh7785lcr.c                   |   15 +-
 arch/sh/boards/board-urquell.c                     |    3 +-
 arch/sh/boards/mach-ap325rxa/setup.c               |   15 +-
 arch/sh/boards/mach-cayman/setup.c                 |    1 -
 arch/sh/boards/mach-ecovec24/setup.c               |   44 +-
 arch/sh/boards/mach-hp6xx/setup.c                  |    5 +-
 arch/sh/boards/mach-kfr2r09/setup.c                |   15 +-
 arch/sh/boards/mach-lboxre2/setup.c                |    1 -
 arch/sh/boards/mach-microdev/setup.c               |    1 -
 arch/sh/boards/mach-migor/setup.c                  |   13 +-
 arch/sh/boards/mach-rsk/Kconfig                    |   10 +
 arch/sh/boards/mach-rsk/Makefile                   |    2 +
 arch/sh/boards/mach-rsk/devices-rsk7264.c          |   58 +
 arch/sh/boards/mach-rsk/devices-rsk7269.c          |   60 +
 arch/sh/boards/mach-sdk7780/setup.c                |    1 -
 arch/sh/boards/mach-se/7206/setup.c                |    1 -
 arch/sh/boards/mach-se/770x/setup.c                |   11 -
 arch/sh/boards/mach-se/7721/setup.c                |    1 -
 arch/sh/boards/mach-se/7722/setup.c                |    3 +-
 arch/sh/boards/mach-se/7724/setup.c                |   32 +-
 arch/sh/boards/mach-se/7751/setup.c                |    1 -
 arch/sh/boards/mach-se/7780/setup.c                |    1 -
 arch/sh/boards/mach-se/board-se7619.c              |    1 -
 arch/sh/boards/mach-sh03/setup.c                   |    1 -
 arch/sh/boards/mach-sh7763rdp/setup.c              |    6 +-
 arch/sh/configs/rsk7264_defconfig                  |   80 +
 arch/sh/configs/rsk7269_defconfig                  |   65 +
 arch/sh/drivers/dma/Kconfig                        |   17 -
 arch/sh/drivers/dma/dma-sh.c                       |  290 +-
 arch/sh/drivers/dma/dma-sysfs.c                    |    2 +-
 arch/sh/drivers/pci/fixups-landisk.c               |    3 +-
 arch/sh/drivers/pci/fixups-r7780rp.c               |    7 +-
 arch/sh/drivers/pci/fixups-sdk7780.c               |   18 +-
 arch/sh/drivers/pci/fixups-se7751.c                |    5 +-
 arch/sh/drivers/pci/fixups-sh03.c                  |   19 +-
 arch/sh/drivers/pci/fixups-snapgear.c              |   11 +-
 arch/sh/drivers/pci/pcie-sh7786.c                  |    3 +-
 arch/sh/include/asm/dma-sh.h                       |   87 -
 arch/sh/include/asm/dma.h                          |    9 -
 arch/sh/include/asm/fixmap.h                       |    2 +-
 arch/sh/include/asm/i2c-sh7760.h                   |    2 -
 arch/sh/include/asm/io.h                           |    5 +
 arch/sh/include/asm/io_noioport.h                  |   41 +
 arch/sh/include/asm/irq.h                          |   13 +-
 arch/sh/include/asm/kdebug.h                       |    2 +
 arch/sh/include/asm/kgdb.h                         |   30 +-
 arch/sh/include/asm/machvec.h                      |    1 -
 arch/sh/include/asm/pgtable_64.h                   |    3 -
 arch/sh/include/asm/processor.h                    |    5 +-
 arch/sh/include/asm/processor_64.h                 |    3 -
 arch/sh/include/asm/stackprotector.h               |   27 +
 arch/sh/include/asm/thread_info.h                  |   46 +-
 arch/sh/include/asm/traps_64.h                     |   14 +
 arch/sh/include/cpu-sh2/cpu/dma.h                  |   23 -
 arch/sh/include/cpu-sh2a/cpu/dma.h                 |    1 -
 arch/sh/include/cpu-sh2a/cpu/sh7264.h              |  176 ++
 arch/sh/include/cpu-sh2a/cpu/sh7269.h              |  201 ++
 arch/sh/include/cpu-sh3/cpu/dma.h                  |   13 +-
 arch/sh/include/cpu-sh4/cpu/dma-sh4a.h             |   83 -
 arch/sh/include/cpu-sh4/cpu/dma.h                  |   25 +-
 arch/sh/include/cpu-sh4/cpu/freq.h                 |    5 +
 arch/sh/include/cpu-sh4/cpu/sh7734.h               |  306 +++
 arch/sh/include/cpu-sh4a/cpu/dma.h                 |   72 +
 arch/sh/include/cpu-sh5/cpu/dma.h                  |    6 -
 arch/sh/include/mach-common/mach/hp6xx.h           |    7 +-
 arch/sh/include/mach-common/mach/lboxre2.h         |   13 +-
 arch/sh/include/mach-common/mach/sdk7780.h         |    5 +-
 arch/sh/include/mach-common/mach/titan.h           |   12 +-
 arch/sh/include/mach-dreamcast/mach/dma.h          |    2 -
 arch/sh/include/mach-landisk/mach/iodata_landisk.h |   19 +-
 arch/sh/include/mach-se/mach/se.h                  |   19 +-
 arch/sh/include/mach-se/mach/se7343.h              |    9 +-
 arch/sh/include/mach-se/mach/se7721.h              |    6 +-
 arch/sh/include/mach-se/mach/se7722.h              |    9 +-
 arch/sh/include/mach-se/mach/se7724.h              |    7 +-
 arch/sh/include/mach-se/mach/se7751.h              |    3 +-
 arch/sh/include/mach-se/mach/se7780.h              |    7 +-
 arch/sh/kernel/cpu/proc.c                          |    4 +-
 arch/sh/kernel/cpu/sh2/setup-sh7619.c              |    6 +-
 arch/sh/kernel/cpu/sh2a/Makefile                   |    4 +
 arch/sh/kernel/cpu/sh2a/clock-sh7264.c             |  153 ++
 arch/sh/kernel/cpu/sh2a/clock-sh7269.c             |  184 ++
 arch/sh/kernel/cpu/sh2a/pinmux-sh7264.c            | 2136 +++++++++++++++
 arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c            | 2800 ++++++++++++++++++++
 arch/sh/kernel/cpu/sh2a/probe.c                    |    6 +
 arch/sh/kernel/cpu/sh2a/setup-mxg.c                |    2 +-
 arch/sh/kernel/cpu/sh2a/setup-sh7201.c             |   16 +-
 arch/sh/kernel/cpu/sh2a/setup-sh7203.c             |    8 +-
 arch/sh/kernel/cpu/sh2a/setup-sh7206.c             |    8 +-
 arch/sh/kernel/cpu/sh2a/setup-sh7264.c             |  606 +++++
 arch/sh/kernel/cpu/sh2a/setup-sh7269.c             |  615 +++++
 arch/sh/kernel/cpu/sh3/entry.S                     |   11 +-
 arch/sh/kernel/cpu/sh3/setup-sh7705.c              |   13 +-
 arch/sh/kernel/cpu/sh3/setup-sh770x.c              |   15 +-
 arch/sh/kernel/cpu/sh3/setup-sh7710.c              |   13 +-
 arch/sh/kernel/cpu/sh3/setup-sh7720.c              |   32 +-
 arch/sh/kernel/cpu/sh4/probe.c                     |    3 +
 arch/sh/kernel/cpu/sh4/setup-sh4-202.c             |   12 +-
 arch/sh/kernel/cpu/sh4/setup-sh7750.c              |   17 +-
 arch/sh/kernel/cpu/sh4/setup-sh7760.c              |   26 +-
 arch/sh/kernel/cpu/sh4a/Makefile                   |    3 +
 arch/sh/kernel/cpu/sh4a/clock-sh7734.c             |  266 ++
 arch/sh/kernel/cpu/sh4a/pinmux-sh7734.c            | 2497 +++++++++++++++++
 arch/sh/kernel/cpu/sh4a/setup-sh7343.c             |   31 +-
 arch/sh/kernel/cpu/sh4a/setup-sh7366.c             |   23 +-
 arch/sh/kernel/cpu/sh4a/setup-sh7722.c             |   47 +-
 arch/sh/kernel/cpu/sh4a/setup-sh7723.c             |   47 +-
 arch/sh/kernel/cpu/sh4a/setup-sh7724.c             |   77 +-
 arch/sh/kernel/cpu/sh4a/setup-sh7734.c             |  800 ++++++
 arch/sh/kernel/cpu/sh4a/setup-sh7757.c             |   90 +-
 arch/sh/kernel/cpu/sh4a/setup-sh7763.c             |   30 +-
 arch/sh/kernel/cpu/sh4a/setup-sh7770.c             |   39 +-
 arch/sh/kernel/cpu/sh4a/setup-sh7780.c             |   37 +-
 arch/sh/kernel/cpu/sh4a/setup-sh7785.c             |   43 +-
 arch/sh/kernel/cpu/sh4a/setup-sh7786.c             |   47 +-
 arch/sh/kernel/cpu/sh4a/setup-shx3.c               |   31 +-
 arch/sh/kernel/cpu/sh5/entry.S                     |   22 +-
 arch/sh/kernel/cpu/sh5/fpu.c                       |    3 -
 arch/sh/kernel/irq.c                               |    6 +-
 arch/sh/kernel/kgdb.c                              |  105 +-
 arch/sh/kernel/machvec.c                           |    3 -
 arch/sh/kernel/process.c                           |    7 +
 arch/sh/kernel/process_32.c                        |    5 +
 arch/sh/kernel/traps_64.c                          |    2 -
 arch/sh/mm/Makefile                                |    8 +-
 arch/sh/mm/fault.c                                 |  514 ++++
 arch/sh/mm/fault_32.c                              |  374 ---
 arch/sh/mm/fault_64.c                              |  265 --
 arch/sh/mm/tlb-sh5.c                               |   40 +
 arch/sh/mm/tlbex_32.c                              |   78 +
 arch/sh/mm/tlbex_64.c                              |  166 ++
 arch/sh/mm/tlbflush_64.c                           |  294 +-
 arch/sh/tools/mach-types                           |    2 +
 drivers/sh/clk/cpg.c                               |   77 +-
 drivers/sh/intc/dynamic.c                          |    8 -
 drivers/tty/serial/sh-sci.c                        |   49 +-
 drivers/watchdog/Kconfig                           |    1 +
 drivers/watchdog/shwdt.c                           |  306 +--
 include/linux/serial_sci.h                         |    2 +
 include/linux/sh_clk.h                             |   34 +-
 include/linux/sh_intc.h                            |    1 -
 152 files changed, 13243 insertions(+), 2205 deletions(-)
 create mode 100644 arch/sh/boards/mach-rsk/devices-rsk7264.c
 create mode 100644 arch/sh/boards/mach-rsk/devices-rsk7269.c
 create mode 100644 arch/sh/configs/rsk7264_defconfig
 create mode 100644 arch/sh/configs/rsk7269_defconfig
 delete mode 100644 arch/sh/include/asm/dma-sh.h
 create mode 100644 arch/sh/include/asm/io_noioport.h
 create mode 100644 arch/sh/include/asm/stackprotector.h
 delete mode 100644 arch/sh/include/cpu-sh2/cpu/dma.h
 delete mode 100644 arch/sh/include/cpu-sh2a/cpu/dma.h
 create mode 100644 arch/sh/include/cpu-sh2a/cpu/sh7264.h
 create mode 100644 arch/sh/include/cpu-sh2a/cpu/sh7269.h
 delete mode 100644 arch/sh/include/cpu-sh4/cpu/dma-sh4a.h
 create mode 100644 arch/sh/include/cpu-sh4/cpu/sh7734.h
 create mode 100644 arch/sh/include/cpu-sh4a/cpu/dma.h
 delete mode 100644 arch/sh/include/cpu-sh5/cpu/dma.h
 create mode 100644 arch/sh/kernel/cpu/sh2a/clock-sh7264.c
 create mode 100644 arch/sh/kernel/cpu/sh2a/clock-sh7269.c
 create mode 100644 arch/sh/kernel/cpu/sh2a/pinmux-sh7264.c
 create mode 100644 arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c
 create mode 100644 arch/sh/kernel/cpu/sh2a/setup-sh7264.c
 create mode 100644 arch/sh/kernel/cpu/sh2a/setup-sh7269.c
 create mode 100644 arch/sh/kernel/cpu/sh4a/clock-sh7734.c
 create mode 100644 arch/sh/kernel/cpu/sh4a/pinmux-sh7734.c
 create mode 100644 arch/sh/kernel/cpu/sh4a/setup-sh7734.c
 create mode 100644 arch/sh/mm/fault.c
 delete mode 100644 arch/sh/mm/fault_32.c
 delete mode 100644 arch/sh/mm/fault_64.c
 create mode 100644 arch/sh/mm/tlbex_32.c
 create mode 100644 arch/sh/mm/tlbex_64.c
--
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[PATCH 0/2] ARM: mach-shmobile: kzm9g: add FSI support

2012-05-22T02:33:45

Hi Rafael, Magnus
Cc Simon

The necessary missing patches for kzm9g will be merged on v3.5 kernel.
These are ASoC
(and already exists on linux-next tree)

These patch set add FSI sound support to kzm9g board for v3.5 kernel.

Kuninori Morimoto (2):
      ARM: mach-shmobile: clock-sh73a0: add FSI clock
      ARM: mach-shmobile: kzm9g: add FSI-AK4648 support
--
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[PATCH 0/11] ARM: mach-shmobile: armadillo: add FSI/HDMI/Camera support

Kuninori Morimoto — 2012-05-22T02:26:06

Hi Rafael, Magnus
Cc Simon

The necessary missing patches for Armadillo will be merged on v3.5 kernel.
These are ASoC/FSI/HDMI/CEU/.
(and already exists on linux-next tree)

These patch set add HDMI/camera/FSI sound x2 to Armadillo board for v3.5 kernel.

Kuninori Morimoto (11):
      ARM: mach-shmobile: intc-r8a7740: add HDMI support
      ARM: mach-shmobile: setup-r8a7740: add MERAM work-around
      ARM: mach-shmobile: clock-r8a7740: add HDMI clock
      ARM: mach-shmobile: clock-r8a7740: add CEU support
      ARM: mach-shmobile: clock-r8a7740: add FSI parent control support
      ARM: mach-shmobile: pfc-r8a7740: Add HDMI GPIO support
      ARM: mach-shmobile: pfc-r8a7740: add FSI-B (for HDMI) support
      ARM: mach-shmobile: armadillo800eva: add HDMI support
      ARM: mach-shmobile: armadillo800eva: add camera support
      ARM: mach-shmobile: armadillo800eva: Add FSI-WM8978 support
      ARM: mach-shmobile: armadillo800eva: add FSI-HDMI support

Best regards
---
Kuninori Morimoto
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Compile Failure SH7203

Felix Born — 2012-05-19T14:07:43

Hi,
I get an error while compiling the kernel for sh7203.
I' am using the Linux/sh 3.3.0 Kernel.
Can anyone give me some hints?
The compile log is listed below:
=============================================
   CHK     include/linux/version.h
   CHK     include/generated/utsrelease.h
make[1]: `include/generated/machtypes.h' is up to date.
   CC      arch/sh/kernel/asm-offsets.s
In file included from include/asm-generic/getorder.h:7:0,
                  from /home/testo/SH2A/sh7203_gcc-3.4.6_kernel_mod/linux-3.3.0-sh7203/arch/sh/include/asm/page.h:187,
                  from /home/testo/SH2A/sh7203_gcc-3.4.6_kernel_mod/linux-3.3.0-sh7203/arch/sh/include/asm/mmu.h:38,
                  from /home/testo/SH2A/sh7203_gcc-3.4.6_kernel_mod/linux-3.3.0-sh7203/arch/sh/include/asm/system_32.h:5,
                  from /home/testo/SH2A/sh7203_gcc-3.4.6_kernel_mod/linux-3.3.0-sh7203/arch/sh/include/asm/system.h:179,
                  from include/asm-generic/bitops/atomic.h:5,
                  from /home/testo/SH2A/sh7203_gcc-3.4.6_kernel_mod/linux-3.3.0-sh7203/arch/sh/include/asm/bitops.h:21,
                  from include/linux/bitops.h:22,
                  from include/linux/thread_info.h:52,
                  from include/linux/preempt.h:9,
                  from include/linux/spinlock.h:50,
                  from include/linux/mmzone.h:7,
                  from include/linux/gfp.h:4,
                  from include/linux/mm.h:8,
                  from arch/sh/kernel/asm-offsets.c:13:
include/linux/log2.h: In function '__ilog2_u32':
include/linux/log2.h:34:2: error: implicit declaration of function 'fls'
include/linux/log2.h: In function '__ilog2_u64':
include/linux/log2.h:42:2: error: implicit declaration of function 'fls64'
include/linux/log2.h: In function '__roundup_pow_of_two':
include/linux/log2.h:63:2: error: implicit declaration of function 'fls_long'
In file included from /home/testo/SH2A/sh7203_gcc-3.4.6_kernel_mod/linux-3.3.0-sh7203/arch/sh/include/asm/bitops.h:98:0,
                  from include/linux/bitops.h:22,
                  from include/linux/thread_info.h:52,
                  from include/linux/preempt.h:9,
                  from include/linux/spinlock.h:50,
                  from include/linux/mmzone.h:7,
                  from include/linux/gfp.h:4,
                  from include/linux/mm.h:8,
                  from arch/sh/kernel/asm-offsets.c:13:
include/asm-generic/bitops/fls.h: At top level:
include/asm-generic/bitops/fls.h:12:28: error: static declaration of 'fls' follows non-static declaration
include/linux/log2.h:34:9: note: previous implicit declaration of 'fls' was here
In file included from /home/testo/SH2A/sh7203_gcc-3.4.6_kernel_mod/linux-3.3.0-sh7203/arch/sh/include/asm/bitops.h:100:0,
                  from include/linux/bitops.h:22,
                  from include/linux/thread_info.h:52,
                  from include/linux/preempt.h:9,
                  from include/linux/spinlock.h:50,
                  from include/linux/mmzone.h:7,
                  from include/linux/gfp.h:4,
                  from include/linux/mm.h:8,
                  from arch/sh/kernel/asm-offsets.c:13:
include/asm-generic/bitops/fls64.h:18:28: error: static declaration of 'fls64' follows non-static declaration
include/linux/log2.h:42:9: note: previous implicit declaration of 'fls64' was here
In file included from include/linux/thread_info.h:52:0,
                  from include/linux/preempt.h:9,
                  from include/linux/spinlock.h:50,
                  from include/linux/mmzone.h:7,
                  from include/linux/gfp.h:4,
                  from include/linux/mm.h:8,
                  from arch/sh/kernel/asm-offsets.c:13:
include/linux/bitops.h:160:24: error: conflicting types for 'fls_long'
include/linux/log2.h:63:16: note: previous implicit declaration of 'fls_long' was here
make[1]: *** [arch/sh/kernel/asm-offsets.s] Error 1
make: *** [prepare0] Error 2
=============================================
Thanks.
Kind Regards.
Felix Born

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[PATCH 0/8] irqdomain cleanups + identity mapping support

Paul Mundt — 2012-05-19T06:11:40

Here's the current patch stack I've got against the irqdomain code, which
is about what I need to start being able to reasonably start converting
the SH INTC subsystem over to it.

This whole series is also available via git at:

git://github.com/pmundt/linux-sh.git common/irqdomain

but I've not yet created a signed tag to pull from as there's likely
still a fair bit of work to do. The diffstat looks innocuous enough, but
is obviously of no real value in this case:

Paul Mundt (8):
      irqdomain: Support removal of IRQ domains.
      irqdomain: Export remaining public API symbols.
      irqdomain: Make irq_domain_simple_map() static.
      irqdomain: Simple NUMA awareness.
      irqdomain: Kill off duplicate definitions.
      irqdomain: Support identity mapped VIRQ allocation.
      irqdomain: trivial pr_fmt conversion.
      irqdomain: Support insertion of existing IRQ allocations.

 include/linux/irqdomain.h |   12 +-
 include/linux/of.h        |   10 +-
 kernel/irq/irqdomain.c    |  187 ++++++++++++++++++++++++++++++++++++++--------
 3 files changed, 168 insertions(+), 41 deletions(-)

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[GIT PULL] Renesas sh73a0 fix for v3.5

Rafael J. Wysocki — 2012-05-18T21:44:59

Hi,

Please pull changes since commit d48b97b403d23f6df0b990cee652bdf9a52337a3

    Linux 3.4-rc6

with top-most commit 4da773193414788b52ae14bc246543390faca5ce

    ARM: mach-shmobile: sh73a0: fixup PINT/IRQ16-IRQ31 irq number conflict

from the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/rafael/renesas.git soc-core

to receive an sh73a0 fix related to the allocation of IRQs for v3.5.

This is based on material that has been merged into the arm-soc tree already.

Thanks!


 arch/arm/mach-shmobile/include/mach/sh73a0.h |   34 +++++++++++++++++++++++--
 1 files changed, 31 insertions(+), 3 deletions(-)

---------------

Kuninori Morimoto (1):
      ARM: mach-shmobile: sh73a0: fixup PINT/IRQ16-IRQ31 irq number conflict

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[PATCH v5 6/6] net: sh_eth: use NAPI

Shimoda, Yoshihiro — 2012-05-18T01:58:36

This patch modifies the driver to use NAPI.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh< at >renesas.com>
---
 about v5:
  - fix two racing sh_eth_txfree() in sh_eth_start_xmit() and sh_eth_poll()

 drivers/net/ethernet/renesas/sh_eth.c |  109 +++++++++++++++++++++------------
 drivers/net/ethernet/renesas/sh_eth.h |    3 +
 2 files changed, 73 insertions(+), 39 deletions(-)

diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c
index c64a31c..1dc9b6e 100644
--- a/drivers/net/ethernet/renesas/sh_eth.c
+++ b/drivers/net/ethernet/renesas/sh_eth.c
< at >< at > -1035,7 +1035,7 < at >< at > static int sh_eth_txfree(struct net_device *ndev)
 }

 /* Packet receive function */
-static int sh_eth_rx(struct net_device *ndev)
+static int sh_eth_rx(struct net_device *ndev, int *work, int budget)
 {
 struct sh_eth_private *mdp = netdev_priv(ndev);
 struct sh_eth_rxdesc *rxdesc;
< at >< at > -1047,7 +1047,8 < at >< at > static int sh_eth_rx(struct net_device *ndev)
 u32 desc_status;

 rxdesc = &mdp->rx_ring[entry];
-while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
+while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT)) &&
+       *work < budget) {
 desc_status = edmac_to_cpu(mdp, rxdesc->status);
 pkt_len = rxdesc->frame_length;

< at >< at > -1087,13 +1088,17 < at >< at > static int sh_eth_rx(struct net_device *ndev)
 skb_reserve(skb, NET_IP_ALIGN);
 skb_put(skb, pkt_len);
 skb->protocol = eth_type_trans(skb, ndev);
-netif_rx(skb);
-ndev->stats.rx_packets++;
-ndev->stats.rx_bytes += pkt_len;
+if (netif_receive_skb(skb) == NET_RX_DROP) {
+ndev->stats.rx_dropped++;
+} else {
+ndev->stats.rx_packets++;
+ndev->stats.rx_bytes += pkt_len;
+}
 }
 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT);
 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
 rxdesc = &mdp->rx_ring[entry];
+(*work)++;
 }

 /* Refill the Rx ring buffers. */
< at >< at > -1125,7 +1130,7 < at >< at > static int sh_eth_rx(struct net_device *ndev)

 /* Restart Rx engine if stopped. */
 /* If we don't need to check status, don't. -KDU */
-if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
+if (*work < budget && !(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
 /* fix the values for the next receiving */
 mdp->cur_rx = mdp->dirty_rx = (sh_eth_read(ndev, RDFAR) -
        sh_eth_read(ndev, RDLAR)) >> 4;
< at >< at > -1281,38 +1286,61 < at >< at > static irqreturn_t sh_eth_interrupt(int irq, void *netdev)

 /* Get interrpt stat */
 intr_status = sh_eth_read(ndev, EESR);
-/* Clear interrupt */
 if (intr_status & (EESR_FRC | EESR_RMAF | EESR_RRF |
 EESR_RTLF | EESR_RTSF | EESR_PRE | EESR_CERF |
 cd->tx_check | cd->eesr_err_check)) {
-sh_eth_write(ndev, intr_status, EESR);
+if (napi_schedule_prep(&mdp->napi)) {
+/* Disable interrupts of the channel */
+sh_eth_write(ndev, 0, EESIPR);
+__napi_schedule(&mdp->napi);
+}
 ret = IRQ_HANDLED;
-} else
-goto other_irq;
-
-if (intr_status & (EESR_FRC | /* Frame recv*/
-EESR_RMAF | /* Multi cast address recv*/
-EESR_RRF  | /* Bit frame recv */
-EESR_RTLF | /* Long frame recv*/
-EESR_RTSF | /* short frame recv */
-EESR_PRE  | /* PHY-LSI recv error */
-EESR_CERF)){ /* recv frame CRC error */
-sh_eth_rx(ndev);
 }

-/* Tx Check */
-if (intr_status & cd->tx_check) {
-sh_eth_txfree(ndev);
-netif_wake_queue(ndev);
+spin_unlock(&mdp->lock);
+
+return ret;
+}
+
+static int sh_eth_poll(struct napi_struct *napi, int budget)
+{
+struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
+  napi);
+struct net_device *ndev = mdp->ndev;
+struct sh_eth_cpu_data *cd = mdp->cd;
+int work_done = 0, txfree_num;
+u32 intr_status = sh_eth_read(ndev, EESR);
+
+/* Clear interrupt flags */
+sh_eth_write(ndev, intr_status, EESR);
+
+/* check txdesc */
+txfree_num = sh_eth_txfree(ndev);
+if (txfree_num) {
+netif_tx_lock(ndev);
+if (netif_queue_stopped(ndev))
+netif_wake_queue(ndev);
+netif_tx_unlock(ndev);
 }

+/* check rxdesc */
+sh_eth_rx(ndev, &work_done, budget);
+
+/* check error flags */
 if (intr_status & cd->eesr_err_check)
 sh_eth_error(ndev, intr_status);

-other_irq:
-spin_unlock(&mdp->lock);
+/* get current interrupt flags */
+intr_status = sh_eth_read(ndev, EESR);

-return ret;
+/* check whether this driver should call napi_complete() */
+if (work_done < budget) {
+napi_complete(napi);
+/* Enable all interrupts */
+sh_eth_write(ndev, cd->eesipr_value, EESIPR);
+}
+
+return work_done;
 }

 /* PHY state control function */
< at >< at > -1545,6 +1573,7 < at >< at > static int sh_eth_set_ringparam(struct net_device *ndev,
 /* Stop the chip's Tx and Rx processes. */
 sh_eth_write(ndev, 0, EDTRR);
 sh_eth_write(ndev, 0, EDRRR);
+napi_disable(&mdp->napi);
 synchronize_irq(ndev->irq);
 }

< at >< at > -1569,6 +1598,7 < at >< at > static int sh_eth_set_ringparam(struct net_device *ndev,
 }

 if (netif_running(ndev)) {
+napi_enable(&mdp->napi);
 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
 /* Setting the Rx mode will start the Rx process. */
 sh_eth_write(ndev, EDRRR_R, EDRRR);
< at >< at > -1600,6 +1630,8 < at >< at > static int sh_eth_open(struct net_device *ndev)

 pm_runtime_get_sync(&mdp->pdev->dev);

+napi_enable(&mdp->napi);
+
 ret = request_irq(ndev->irq, sh_eth_interrupt,
 #if defined(CONFIG_CPU_SUBTYPE_SH7763) || \
 defined(CONFIG_CPU_SUBTYPE_SH7764) || \
< at >< at > -1678,19 +1710,6 < at >< at > static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
 struct sh_eth_private *mdp = netdev_priv(ndev);
 struct sh_eth_txdesc *txdesc;
 u32 entry;
-unsigned long flags;
-
-spin_lock_irqsave(&mdp->lock, flags);
-if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
-if (!sh_eth_txfree(ndev)) {
-if (netif_msg_tx_queued(mdp))
-dev_warn(&ndev->dev, "TxFD exhausted.\n");
-netif_stop_queue(ndev);
-spin_unlock_irqrestore(&mdp->lock, flags);
-return NETDEV_TX_BUSY;
-}
-}
-spin_unlock_irqrestore(&mdp->lock, flags);

 entry = mdp->cur_tx % mdp->num_tx_ring;
 mdp->tx_skbuff[entry] = skb;
< at >< at > -1716,6 +1735,13 < at >< at > static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);

+if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
+if (netif_msg_tx_queued(mdp)) {
+dev_warn(&ndev->dev, "TxFD exhausted.\n");
+netif_stop_queue(ndev);
+}
+}
+
 return NETDEV_TX_OK;
 }

< at >< at > -1739,6 +1765,8 < at >< at > static int sh_eth_close(struct net_device *ndev)
 phy_disconnect(mdp->phydev);
 }

+napi_disable(&mdp->napi);
+
 free_irq(ndev->irq, ndev);

 /* Free all the skbuffs in the Rx queue. */
< at >< at > -2368,6 +2396,9 < at >< at > static int sh_eth_drv_probe(struct platform_device *pdev)
 #endif
 sh_eth_set_default_cpu_data(mdp->cd);

+mdp->ndev = ndev;
+netif_napi_add(ndev, &mdp->napi, sh_eth_poll, SH_ETH_NAPI_WEIGHT);
+
 /* set function */
 ndev->netdev_ops = &sh_eth_netdev_ops;
 SET_ETHTOOL_OPS(ndev, &sh_eth_ethtool_ops);
diff --git a/drivers/net/ethernet/renesas/sh_eth.h b/drivers/net/ethernet/renesas/sh_eth.h
index f1dbc27..93dad7b 100644
--- a/drivers/net/ethernet/renesas/sh_eth.h
+++ b/drivers/net/ethernet/renesas/sh_eth.h
< at >< at > -35,6 +35,7 < at >< at >
 #define PKT_BUF_SZ1538
 #define SH_ETH_TSU_TIMEOUT_MS500
 #define SH_ETH_TSU_CAM_ENTRIES32
+#define SH_ETH_NAPI_WEIGHT32

 enum {
 /* E-DMAC registers */
< at >< at > -728,6 +729,8 < at >< at > struct sh_eth_private {
 int duplex;
 int port;/* for TSU */
 int vlan_num_ids;/* for VLAN tag filter */
+struct napi_struct napi;
+struct net_device *ndev;

 unsigned no_ether_link:1;
 unsigned ether_link_active_low:1;

[PATCH][RESEND] gpio: Emma Mobile GPIO driver V2

Magnus Damm — 2012-05-17T06:22:23

From: Magnus Damm <damm< at >opensource.se>

This patch is V2 of the Emma Mobile GPIO driver. This
driver is designed to be reusable between multiple SoCs
that share the same basic building block, but so far it
has only been used on Emma Mobile EV2.

Each driver instance handles 32 GPIOs with individually
maskable IRQs. The driver operates on two I/O memory 
ranges and the 32 GPIOs are hooked up to two interrupts.

In the case of Emma Mobile EV2 this GPIO building block
is used as main external interrupt controller hooking up
159 GPIOS as 159 interrupts via 5 driver instances and
10 interrupts to the GIC and the Cortex-A9 Dual.

Signed-off-by: Magnus Damm <damm< at >opensource.se>
Acked-by: Linus Walleij <linus.walleij< at >linaro.org>
---

 Rafael, can you please pick up?

 Changes since V1:
 - use inline for private data functions using container_of() 
 - use BIT(n) instead of 1 << n
 - added legacy irq domain support for static mappings
 - use irqd_to_hwirq() instead of own offset calculation
 - convert irqchip callbacks to not care about virq
 - rework IRQ handler to read interrupt status inside loop

 Changes not made:
 - ioread/iowrite are still used over readl/writel
 - no request_mem_region
 - no devm_ alloc/ioremap
 - kept the kconfig dependencies as in V1

 Many thanks to Linus Walleij and Arnd Bergmann for
 their help with the code review!

 drivers/gpio/Kconfig                  |    6 
 drivers/gpio/Makefile                 |    1 
 drivers/gpio/gpio-em.c                |  418 +++++++++++++++++++++++++++++++++
 include/linux/platform_data/gpio-em.h |   10 
 4 files changed, 435 insertions(+)

--- 0001/drivers/gpio/Kconfig
+++ work/drivers/gpio/Kconfig2012-05-15 14:50:42.000000000 +0900
< at >< at > -103,6 +103,12 < at >< at > config GPIO_IT8761E
 help
   Say yes here to support GPIO functionality of IT8761E super I/O chip.
 
+config GPIO_EM
+tristate "Emma Mobile GPIO"
+depends on ARM
+help
+  Say yes here to support GPIO on Renesas Emma Mobile SoCs.
+
 config GPIO_EP93XX
 def_bool y
 depends on ARCH_EP93XX
--- 0001/drivers/gpio/Makefile
+++ work/drivers/gpio/Makefile2012-05-15 14:50:42.000000000 +0900
< at >< at > -16,6 +16,7 < at >< at > obj-$(CONFIG_GPIO_BT8XX)+= gpio-bt8xx.o
 obj-$(CONFIG_GPIO_CS5535)+= gpio-cs5535.o
 obj-$(CONFIG_GPIO_DA9052)+= gpio-da9052.o
 obj-$(CONFIG_ARCH_DAVINCI)+= gpio-davinci.o
+obj-$(CONFIG_GPIO_EM)+= gpio-em.o
 obj-$(CONFIG_GPIO_EP93XX)+= gpio-ep93xx.o
 obj-$(CONFIG_GPIO_GE_FPGA)+= gpio-ge.o
 obj-$(CONFIG_GPIO_ICH)+= gpio-ich.o
--- /dev/null
+++ work/drivers/gpio/gpio-em.c2012-05-16 00:07:20.000000000 +0900
< at >< at > -0,0 +1,418 < at >< at >
+/*
+ * Emma Mobile GPIO Support - GIO
+ *
+ *  Copyright (C) 2012 Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/bitops.h>
+#include <linux/err.h>
+#include <linux/gpio.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/platform_data/gpio-em.h>
+
+struct em_gio_priv {
+void __iomem *base0;
+void __iomem *base1;
+unsigned int irq_base;
+spinlock_t sense_lock;
+struct platform_device *pdev;
+struct gpio_chip gpio_chip;
+struct irq_chip irq_chip;
+struct irq_domain *irq_domain;
+};
+
+#define GIO_E1 0x00
+#define GIO_E0 0x04
+#define GIO_EM 0x04
+#define GIO_OL 0x08
+#define GIO_OH 0x0c
+#define GIO_I 0x10
+#define GIO_IIA 0x14
+#define GIO_IEN 0x18
+#define GIO_IDS 0x1c
+#define GIO_IIM 0x1c
+#define GIO_RAW 0x20
+#define GIO_MST 0x24
+#define GIO_IIR 0x28
+
+#define GIO_IDT0 0x40
+#define GIO_IDT1 0x44
+#define GIO_IDT2 0x48
+#define GIO_IDT3 0x4c
+#define GIO_RAWBL 0x50
+#define GIO_RAWBH 0x54
+#define GIO_IRBL 0x58
+#define GIO_IRBH 0x5c
+
+#define GIO_IDT(n) (GIO_IDT0 + ((n) * 4))
+
+static inline unsigned long em_gio_read(struct em_gio_priv *p, int offs)
+{
+if (offs < GIO_IDT0)
+return ioread32(p->base0 + offs);
+else
+return ioread32(p->base1 + (offs - GIO_IDT0));
+}
+
+static inline void em_gio_write(struct em_gio_priv *p, int offs,
+unsigned long value)
+{
+if (offs < GIO_IDT0)
+iowrite32(value, p->base0 + offs);
+else
+iowrite32(value, p->base1 + (offs - GIO_IDT0));
+}
+
+static inline struct em_gio_priv *irq_to_priv(struct irq_data *d)
+{
+struct irq_chip *chip = irq_data_get_irq_chip(d);
+return container_of(chip, struct em_gio_priv, irq_chip);
+}
+
+static void em_gio_irq_disable(struct irq_data *d)
+{
+struct em_gio_priv *p = irq_to_priv(d);
+
+em_gio_write(p, GIO_IDS, BIT(irqd_to_hwirq(d)));
+}
+
+static void em_gio_irq_enable(struct irq_data *d)
+{
+struct em_gio_priv *p = irq_to_priv(d);
+
+em_gio_write(p, GIO_IEN, BIT(irqd_to_hwirq(d)));
+}
+
+#define GIO_ASYNC(x) (x + 8)
+
+static unsigned char em_gio_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
+[IRQ_TYPE_EDGE_RISING] = GIO_ASYNC(0x00),
+[IRQ_TYPE_EDGE_FALLING] = GIO_ASYNC(0x01),
+[IRQ_TYPE_LEVEL_HIGH] = GIO_ASYNC(0x02),
+[IRQ_TYPE_LEVEL_LOW] = GIO_ASYNC(0x03),
+[IRQ_TYPE_EDGE_BOTH] = GIO_ASYNC(0x04),
+};
+
+static int em_gio_irq_set_type(struct irq_data *d, unsigned int type)
+{
+unsigned char value = em_gio_sense_table[type & IRQ_TYPE_SENSE_MASK];
+struct em_gio_priv *p = irq_to_priv(d);
+unsigned int reg, offset, shift;
+unsigned long flags;
+unsigned long tmp;
+
+if (!value)
+return -EINVAL;
+
+offset = irqd_to_hwirq(d);
+
+pr_debug("gio: sense irq = %d, mode = %d\n", offset, value);
+
+/* 8 x 4 bit fields in 4 IDT registers */
+reg = GIO_IDT(offset >> 3);
+shift = (offset & 0x07) << 4;
+
+spin_lock_irqsave(&p->sense_lock, flags);
+
+/* disable the interrupt in IIA */
+tmp = em_gio_read(p, GIO_IIA);
+tmp &= ~BIT(offset);
+em_gio_write(p, GIO_IIA, tmp);
+
+/* change the sense setting in IDT */
+tmp = em_gio_read(p, reg);
+tmp &= ~(0xf << shift);
+tmp |= value << shift;
+em_gio_write(p, reg, tmp);
+
+/* clear pending interrupts */
+em_gio_write(p, GIO_IIR, BIT(offset));
+
+/* enable the interrupt in IIA */
+tmp = em_gio_read(p, GIO_IIA);
+tmp |= BIT(offset);
+em_gio_write(p, GIO_IIA, tmp);
+
+spin_unlock_irqrestore(&p->sense_lock, flags);
+
+return 0;
+}
+
+static irqreturn_t em_gio_irq_handler(int irq, void *dev_id)
+{
+struct em_gio_priv *p = dev_id;
+unsigned long pending;
+unsigned int offset, irqs_handled = 0;
+
+while ((pending = em_gio_read(p, GIO_MST))) {
+offset = __ffs(pending);
+em_gio_write(p, GIO_IIR, BIT(offset));
+generic_handle_irq(irq_find_mapping(p->irq_domain, offset));
+irqs_handled++;
+}
+
+return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
+}
+
+static inline struct em_gio_priv *gpio_to_priv(struct gpio_chip *chip)
+{
+return container_of(chip, struct em_gio_priv, gpio_chip);
+}
+
+static int em_gio_direction_input(struct gpio_chip *chip, unsigned offset)
+{
+em_gio_write(gpio_to_priv(chip), GIO_E0, BIT(offset));
+return 0;
+}
+
+static int em_gio_get(struct gpio_chip *chip, unsigned offset)
+{
+return (int)(em_gio_read(gpio_to_priv(chip), GIO_I) & BIT(offset));
+}
+
+static void __em_gio_set(struct gpio_chip *chip, unsigned int reg,
+ unsigned shift, int value)
+{
+/* upper 16 bits contains mask and lower 16 actual value */
+em_gio_write(gpio_to_priv(chip), reg,
+     (1 << (shift + 16)) | (value << shift));
+}
+
+static void em_gio_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+/* output is split into two registers */
+if (offset < 16)
+__em_gio_set(chip, GIO_OL, offset, value);
+else
+__em_gio_set(chip, GIO_OH, offset - 16, value);
+}
+
+static int em_gio_direction_output(struct gpio_chip *chip, unsigned offset,
+   int value)
+{
+/* write GPIO value to output before selecting output mode of pin */
+em_gio_set(chip, offset, value);
+em_gio_write(gpio_to_priv(chip), GIO_E1, BIT(offset));
+return 0;
+}
+
+static int em_gio_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+return irq_find_mapping(gpio_to_priv(chip)->irq_domain, offset);
+}
+
+static int em_gio_irq_domain_map(struct irq_domain *h, unsigned int virq,
+ irq_hw_number_t hw)
+{
+struct em_gio_priv *p = h->host_data;
+
+pr_debug("gio: map hw irq = %d, virq = %d\n", (int)hw, virq);
+
+irq_set_chip_data(virq, h->host_data);
+irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
+set_irq_flags(virq, IRQF_VALID); /* kill me now */
+return 0;
+}
+
+static struct irq_domain_ops em_gio_irq_domain_ops = {
+.map= em_gio_irq_domain_map,
+};
+
+static int __devinit em_gio_irq_domain_init(struct em_gio_priv *p)
+{
+struct platform_device *pdev = p->pdev;
+struct gpio_em_config *pdata = pdev->dev.platform_data;
+
+p->irq_base = irq_alloc_descs(pdata->irq_base, 0,
+      pdata->number_of_pins, numa_node_id());
+if (IS_ERR_VALUE(p->irq_base)) {
+dev_err(&pdev->dev, "cannot get irq_desc\n");
+return -ENXIO;
+}
+pr_debug("gio: hw base = %d, nr = %d, sw base = %d\n",
+ pdata->gpio_base, pdata->number_of_pins, p->irq_base);
+
+p->irq_domain = irq_domain_add_legacy(pdev->dev.of_node,
+      pdata->number_of_pins,
+      p->irq_base, 0,
+      &em_gio_irq_domain_ops, p);
+if (!p->irq_domain) {
+irq_free_descs(p->irq_base, pdata->number_of_pins);
+return -ENXIO;
+}
+
+return 0;
+}
+
+static void __devexit em_gio_irq_domain_cleanup(struct em_gio_priv *p)
+{
+struct gpio_em_config *pdata = p->pdev->dev.platform_data;
+
+irq_free_descs(p->irq_base, pdata->number_of_pins);
+/* FIXME: irq domain wants to be freed! */
+}
+
+static int __devinit em_gio_probe(struct platform_device *pdev)
+{
+struct gpio_em_config *pdata = pdev->dev.platform_data;
+struct em_gio_priv *p;
+struct resource *io[2], *irq[2];
+struct gpio_chip *gpio_chip;
+struct irq_chip *irq_chip;
+const char *name = dev_name(&pdev->dev);
+int ret;
+
+p = kzalloc(sizeof(*p), GFP_KERNEL);
+if (!p) {
+dev_err(&pdev->dev, "failed to allocate driver data\n");
+ret = -ENOMEM;
+goto err0;
+}
+
+p->pdev = pdev;
+platform_set_drvdata(pdev, p);
+spin_lock_init(&p->sense_lock);
+
+io[0] = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+io[1] = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+irq[0] = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+irq[1] = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
+
+if (!io[0] || !io[1] || !irq[0] || !irq[1] || !pdata) {
+dev_err(&pdev->dev, "missing IRQ, IOMEM or configuration\n");
+ret = -EINVAL;
+goto err1;
+}
+
+p->base0 = ioremap_nocache(io[0]->start, resource_size(io[0]));
+if (!p->base0) {
+dev_err(&pdev->dev, "failed to remap low I/O memory\n");
+ret = -ENXIO;
+goto err1;
+}
+
+p->base1 = ioremap_nocache(io[1]->start, resource_size(io[1]));
+if (!p->base1) {
+dev_err(&pdev->dev, "failed to remap high I/O memory\n");
+ret = -ENXIO;
+goto err2;
+}
+
+gpio_chip = &p->gpio_chip;
+gpio_chip->direction_input = em_gio_direction_input;
+gpio_chip->get = em_gio_get;
+gpio_chip->direction_output = em_gio_direction_output;
+gpio_chip->set = em_gio_set;
+gpio_chip->to_irq = em_gio_to_irq;
+gpio_chip->label = name;
+gpio_chip->owner = THIS_MODULE;
+gpio_chip->base = pdata->gpio_base;
+gpio_chip->ngpio = pdata->number_of_pins;
+
+irq_chip = &p->irq_chip;
+irq_chip->name = name;
+irq_chip->irq_mask = em_gio_irq_disable;
+irq_chip->irq_unmask = em_gio_irq_enable;
+irq_chip->irq_enable = em_gio_irq_enable;
+irq_chip->irq_disable = em_gio_irq_disable;
+irq_chip->irq_set_type = em_gio_irq_set_type;
+irq_chip->flags= IRQCHIP_SKIP_SET_WAKE;
+
+ret = em_gio_irq_domain_init(p);
+if (ret) {
+dev_err(&pdev->dev, "cannot initialize irq domain\n");
+goto err3;
+}
+
+if (request_irq(irq[0]->start, em_gio_irq_handler, 0, name, p)) {
+dev_err(&pdev->dev, "failed to request low IRQ\n");
+ret = -ENOENT;
+goto err4;
+}
+
+if (request_irq(irq[1]->start, em_gio_irq_handler, 0, name, p)) {
+dev_err(&pdev->dev, "failed to request high IRQ\n");
+ret = -ENOENT;
+goto err5;
+}
+
+ret = gpiochip_add(gpio_chip);
+if (ret) {
+dev_err(&pdev->dev, "failed to add GPIO controller\n");
+goto err6;
+}
+return 0;
+
+err6:
+free_irq(irq[1]->start, pdev);
+err5:
+free_irq(irq[0]->start, pdev);
+err4:
+em_gio_irq_domain_cleanup(p);
+err3:
+iounmap(p->base1);
+err2:
+iounmap(p->base0);
+err1:
+kfree(p);
+err0:
+return ret;
+}
+
+static int __devexit em_gio_remove(struct platform_device *pdev)
+{
+struct em_gio_priv *p = platform_get_drvdata(pdev);
+struct resource *irq[2];
+int ret;
+
+ret = gpiochip_remove(&p->gpio_chip);
+if (ret)
+return ret;
+
+irq[0] = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+irq[1] = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
+
+free_irq(irq[1]->start, pdev);
+free_irq(irq[0]->start, pdev);
+em_gio_irq_domain_cleanup(p);
+iounmap(p->base1);
+iounmap(p->base0);
+kfree(p);
+return 0;
+}
+
+static struct platform_driver em_gio_device_driver = {
+.probe= em_gio_probe,
+.remove= __devexit_p(em_gio_remove),
+.driver= {
+.name= "em_gio",
+}
+};
+
+module_platform_driver(em_gio_device_driver);
+
+MODULE_AUTHOR("Magnus Damm");
+MODULE_DESCRIPTION("Renesas Emma Mobile GIO Driver");
+MODULE_LICENSE("GPL v2");
--- /dev/null
+++ work/include/linux/platform_data/gpio-em.h2012-05-15 14:50:43.000000000 +0900
< at >< at > -0,0 +1,10 < at >< at >
+#ifndef __GPIO_EM_H__
+#define __GPIO_EM_H__
+
+struct gpio_em_config {
+unsigned int gpio_base;
+unsigned int irq_base;
+unsigned int number_of_pins;
+};
+
+#endif /* __GPIO_EM_H__ */
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ap4 (sh7372) regression in 3.3 / 3.4 with serial console - boot failures

Guennadi Liakhovetski — 2012-05-16T13:36:10

Hi all

I'm observing a regression with 3.3 and 3.4 kernels, 3.2 seems to be ok. 
The system (confirmed with mackerel and ap4evb) hangs during boot at 
random times. This can be directly after "freeing init memory," or some 
time during the OS start up, or immediately after the start up has 
completed. But if it managed to boot, it continues to run, I've never seen 
it hanging after I ssh onto the system. It also seems, that the 
probability to hang increases with time after the initial system power on. 
A simple short power off doesn't solve the problem.

Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/
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[PATCH v4 6/6] net: sh_eth: use NAPI

Shimoda, Yoshihiro — 2012-05-16T04:29:11

This patch modifies the driver to use NAPI.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh< at >renesas.com>
---
 about v4:
  - modify sh_eth_poll() for strict synchronization of the xmit
  - remove private spin_lock/unlock in the sh_eth_start_xmit()

 drivers/net/ethernet/renesas/sh_eth.c |   93 ++++++++++++++++++++++-----------
 drivers/net/ethernet/renesas/sh_eth.h |    3 +
 2 files changed, 66 insertions(+), 30 deletions(-)

diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c
index c64a31c..edc7dfe 100644
--- a/drivers/net/ethernet/renesas/sh_eth.c
+++ b/drivers/net/ethernet/renesas/sh_eth.c
< at >< at > -1035,7 +1035,7 < at >< at > static int sh_eth_txfree(struct net_device *ndev)
 }

 /* Packet receive function */
-static int sh_eth_rx(struct net_device *ndev)
+static int sh_eth_rx(struct net_device *ndev, int *work, int budget)
 {
 struct sh_eth_private *mdp = netdev_priv(ndev);
 struct sh_eth_rxdesc *rxdesc;
< at >< at > -1047,7 +1047,8 < at >< at > static int sh_eth_rx(struct net_device *ndev)
 u32 desc_status;

 rxdesc = &mdp->rx_ring[entry];
-while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
+while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT)) &&
+       *work < budget) {
 desc_status = edmac_to_cpu(mdp, rxdesc->status);
 pkt_len = rxdesc->frame_length;

< at >< at > -1087,13 +1088,17 < at >< at > static int sh_eth_rx(struct net_device *ndev)
 skb_reserve(skb, NET_IP_ALIGN);
 skb_put(skb, pkt_len);
 skb->protocol = eth_type_trans(skb, ndev);
-netif_rx(skb);
-ndev->stats.rx_packets++;
-ndev->stats.rx_bytes += pkt_len;
+if (netif_receive_skb(skb) == NET_RX_DROP) {
+ndev->stats.rx_dropped++;
+} else {
+ndev->stats.rx_packets++;
+ndev->stats.rx_bytes += pkt_len;
+}
 }
 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT);
 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
 rxdesc = &mdp->rx_ring[entry];
+(*work)++;
 }

 /* Refill the Rx ring buffers. */
< at >< at > -1125,7 +1130,7 < at >< at > static int sh_eth_rx(struct net_device *ndev)

 /* Restart Rx engine if stopped. */
 /* If we don't need to check status, don't. -KDU */
-if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
+if (*work < budget && !(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
 /* fix the values for the next receiving */
 mdp->cur_rx = mdp->dirty_rx = (sh_eth_read(ndev, RDFAR) -
        sh_eth_read(ndev, RDLAR)) >> 4;
< at >< at > -1281,38 +1286,61 < at >< at > static irqreturn_t sh_eth_interrupt(int irq, void *netdev)

 /* Get interrpt stat */
 intr_status = sh_eth_read(ndev, EESR);
-/* Clear interrupt */
 if (intr_status & (EESR_FRC | EESR_RMAF | EESR_RRF |
 EESR_RTLF | EESR_RTSF | EESR_PRE | EESR_CERF |
 cd->tx_check | cd->eesr_err_check)) {
-sh_eth_write(ndev, intr_status, EESR);
+if (napi_schedule_prep(&mdp->napi)) {
+/* Disable interrupts of the channel */
+sh_eth_write(ndev, 0, EESIPR);
+__napi_schedule(&mdp->napi);
+}
 ret = IRQ_HANDLED;
-} else
-goto other_irq;
-
-if (intr_status & (EESR_FRC | /* Frame recv*/
-EESR_RMAF | /* Multi cast address recv*/
-EESR_RRF  | /* Bit frame recv */
-EESR_RTLF | /* Long frame recv*/
-EESR_RTSF | /* short frame recv */
-EESR_PRE  | /* PHY-LSI recv error */
-EESR_CERF)){ /* recv frame CRC error */
-sh_eth_rx(ndev);
 }

-/* Tx Check */
-if (intr_status & cd->tx_check) {
-sh_eth_txfree(ndev);
-netif_wake_queue(ndev);
+spin_unlock(&mdp->lock);
+
+return ret;
+}
+
+static int sh_eth_poll(struct napi_struct *napi, int budget)
+{
+struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
+  napi);
+struct net_device *ndev = mdp->ndev;
+struct sh_eth_cpu_data *cd = mdp->cd;
+int work_done = 0, txfree_num;
+u32 intr_status = sh_eth_read(ndev, EESR);
+
+/* Clear interrupt flags */
+sh_eth_write(ndev, intr_status, EESR);
+
+/* check txdesc */
+txfree_num = sh_eth_txfree(ndev);
+if (txfree_num) {
+netif_tx_lock(ndev);
+if (netif_queue_stopped(ndev))
+netif_wake_queue(ndev);
+netif_tx_unlock(ndev);
 }

+/* check rxdesc */
+sh_eth_rx(ndev, &work_done, budget);
+
+/* check error flags */
 if (intr_status & cd->eesr_err_check)
 sh_eth_error(ndev, intr_status);

-other_irq:
-spin_unlock(&mdp->lock);
+/* get current interrupt flags */
+intr_status = sh_eth_read(ndev, EESR);

-return ret;
+/* check whether this driver should call napi_complete() */
+if (work_done < budget) {
+napi_complete(napi);
+/* Enable all interrupts */
+sh_eth_write(ndev, cd->eesipr_value, EESIPR);
+}
+
+return work_done;
 }

 /* PHY state control function */
< at >< at > -1545,6 +1573,7 < at >< at > static int sh_eth_set_ringparam(struct net_device *ndev,
 /* Stop the chip's Tx and Rx processes. */
 sh_eth_write(ndev, 0, EDTRR);
 sh_eth_write(ndev, 0, EDRRR);
+napi_disable(&mdp->napi);
 synchronize_irq(ndev->irq);
 }

< at >< at > -1569,6 +1598,7 < at >< at > static int sh_eth_set_ringparam(struct net_device *ndev,
 }

 if (netif_running(ndev)) {
+napi_enable(&mdp->napi);
 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
 /* Setting the Rx mode will start the Rx process. */
 sh_eth_write(ndev, EDRRR_R, EDRRR);
< at >< at > -1600,6 +1630,8 < at >< at > static int sh_eth_open(struct net_device *ndev)

 pm_runtime_get_sync(&mdp->pdev->dev);

+napi_enable(&mdp->napi);
+
 ret = request_irq(ndev->irq, sh_eth_interrupt,
 #if defined(CONFIG_CPU_SUBTYPE_SH7763) || \
 defined(CONFIG_CPU_SUBTYPE_SH7764) || \
< at >< at > -1678,19 +1710,15 < at >< at > static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
 struct sh_eth_private *mdp = netdev_priv(ndev);
 struct sh_eth_txdesc *txdesc;
 u32 entry;
-unsigned long flags;

-spin_lock_irqsave(&mdp->lock, flags);
 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
 if (!sh_eth_txfree(ndev)) {
 if (netif_msg_tx_queued(mdp))
 dev_warn(&ndev->dev, "TxFD exhausted.\n");
 netif_stop_queue(ndev);
-spin_unlock_irqrestore(&mdp->lock, flags);
 return NETDEV_TX_BUSY;
 }
 }
-spin_unlock_irqrestore(&mdp->lock, flags);

 entry = mdp->cur_tx % mdp->num_tx_ring;
 mdp->tx_skbuff[entry] = skb;
< at >< at > -1739,6 +1767,8 < at >< at > static int sh_eth_close(struct net_device *ndev)
 phy_disconnect(mdp->phydev);
 }

+napi_disable(&mdp->napi);
+
 free_irq(ndev->irq, ndev);

 /* Free all the skbuffs in the Rx queue. */
< at >< at > -2368,6 +2398,9 < at >< at > static int sh_eth_drv_probe(struct platform_device *pdev)
 #endif
 sh_eth_set_default_cpu_data(mdp->cd);

+mdp->ndev = ndev;
+netif_napi_add(ndev, &mdp->napi, sh_eth_poll, SH_ETH_NAPI_WEIGHT);
+
 /* set function */
 ndev->netdev_ops = &sh_eth_netdev_ops;
 SET_ETHTOOL_OPS(ndev, &sh_eth_ethtool_ops);
diff --git a/drivers/net/ethernet/renesas/sh_eth.h b/drivers/net/ethernet/renesas/sh_eth.h
index f1dbc27..93dad7b 100644
--- a/drivers/net/ethernet/renesas/sh_eth.h
+++ b/drivers/net/ethernet/renesas/sh_eth.h
< at >< at > -35,6 +35,7 < at >< at >
 #define PKT_BUF_SZ1538
 #define SH_ETH_TSU_TIMEOUT_MS500
 #define SH_ETH_TSU_CAM_ENTRIES32
+#define SH_ETH_NAPI_WEIGHT32

 enum {
 /* E-DMAC registers */
< at >< at > -728,6 +729,8 < at >< at > struct sh_eth_private {
 int duplex;
 int port;/* for TSU */
 int vlan_num_ids;/* for VLAN tag filter */
+struct napi_struct napi;
+struct net_device *ndev;

 unsigned no_ether_link:1;
 unsigned ether_link_active_low:1;

ALSA dma_area not utilizing D-cahce

MASAO TAKAHASHI — 2012-05-16T00:51:23

Hi everybody. 
Please advice me to resolve my problem.
1.  My environment
    HardwareAlpha-project MS104-SH4AG with SH7764
kernelsh-linux-2.6.29
2. My problem
I am ussing a proprietary ALSA driver for SH7764 SSI.
I have found runtime->dma_area address refers DMA area
via D-cache.
So, playback is too late after executing snd_pcm_writei().
Until D-cache writeback is done, sound data stays in D-cache.
I want to read and write from/to main memory 
without D-cache.

3. My idea to solve this problem
add some codes in xxx_prepare() routine as follows

save_playback_area = runtime->dma_area;
runtime->dma_area = P2SEGADDR(runtime->dma_area);

Is my idea right?

Best regards.

Masao Takahashi in Japan

---------- 

MASAO TAKAHASHI <masao-takahashi< at >kanno.co.jp>
KANNO WORKS CO., LTD. JAPAN
TEL 093-436-2330
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[PATCH/RFC] gpio: Emma Mobile GPIO DT prototype

Magnus Damm — 2012-05-15T15:52:49

From: Magnus Damm <damm< at >opensource.se>

Here is my first attempt on EMEV2 GPIO DT support.

More or less only dry coded at this point - only tested
with platform devices using pdata->irq_base = 0.

The IRQ bits seem quite fine to me, but perhaps some
people will dislike the idea of runtime selection if
linear or legacy irq domain should be used. The reason
for both is that the linear irq domain is used in the
case when we want to have a static preallocated range
of IRQs configurable via platform data, and the linear
range is used for DT together with the ->xlate feature.

I am yet to try to tie in the actual GPIO pins using DT.
So please consider this as an early preview of DT support.

Pointers in any direction would be greatly appreciated.

Not-yet-signed-off-by: Magnus Damm <damm< at >opensource.se>
---

 Applies on top of:
 "[PATCH] gpio: Emma Mobile GPIO driver V2"

 drivers/gpio/gpio-em.c |   44 +++++++++++++++++++++++++++++++++++++++-----
 1 file changed, 39 insertions(+), 5 deletions(-)

--- 0011/drivers/gpio/gpio-em.c
+++ work/drivers/gpio/gpio-em.c2012-05-16 00:24:30.000000000 +0900
< at >< at > -41,6 +41,11 < at >< at > struct em_gio_priv {
 struct gpio_chip gpio_chip;
 struct irq_chip irq_chip;
 struct irq_domain *irq_domain;
+
+unsigned int (*hook_irq)(struct irq_domain *domain,
+ irq_hw_number_t hwirq);
+unsigned int (*demux_irq)(struct irq_domain *domain,
+  irq_hw_number_t hwirq);
 };
 
 #define GIO_E1 0x00
< at >< at > -169,7 +174,7 < at >< at > static irqreturn_t em_gio_irq_handler(in
 while ((pending = em_gio_read(p, GIO_MST))) {
 offset = __ffs(pending);
 em_gio_write(p, GIO_IIR, BIT(offset));
-generic_handle_irq(irq_find_mapping(p->irq_domain, offset));
+generic_handle_irq(p->demux_irq(p->irq_domain, offset));
 irqs_handled++;
 }
 
< at >< at > -220,7 +225,9 < at >< at > static int em_gio_direction_output(struc
 
 static int em_gio_to_irq(struct gpio_chip *chip, unsigned offset)
 {
-return irq_find_mapping(gpio_to_priv(chip)->irq_domain, offset);
+struct em_gio_priv *p = gpio_to_priv(chip);
+
+return p->hook_irq(p->irq_domain, offset);
 }
 
 static int em_gio_irq_domain_map(struct irq_domain *h, unsigned int virq,
< at >< at > -238,9 +245,10 < at >< at > static int em_gio_irq_domain_map(struct
 
 static struct irq_domain_ops em_gio_irq_domain_ops = {
 .map= em_gio_irq_domain_map,
+.xlate= irq_domain_xlate_twocell,
 };
 
-static int __devinit em_gio_irq_domain_init(struct em_gio_priv *p)
+static int __devinit em_gio_irq_domain_init_legacy(struct em_gio_priv *p)
 {
 struct platform_device *pdev = p->pdev;
 struct gpio_em_config *pdata = pdev->dev.platform_data;
< at >< at > -263,6 +271,27 < at >< at > static int __devinit em_gio_irq_domain_i
 return -ENXIO;
 }
 
+p->hook_irq = irq_find_mapping;
+p->demux_irq = irq_find_mapping;
+return 0;
+}
+
+static int __devinit em_gio_irq_domain_init_linear(struct em_gio_priv *p)
+{
+struct platform_device *pdev = p->pdev;
+struct gpio_em_config *pdata = pdev->dev.platform_data;
+
+pr_debug("gio: hw base = %d, nr = %d, sw base = dynamic\n",
+ pdata->gpio_base, pdata->number_of_pins);
+
+p->irq_domain = irq_domain_add_linear(pdev->dev.of_node,
+      pdata->number_of_pins,
+      &em_gio_irq_domain_ops, p);
+if (!p->irq_domain)
+return -ENXIO;
+
+p->hook_irq = irq_create_mapping;
+p->demux_irq = irq_linear_revmap;
 return 0;
 }
 
< at >< at > -270,7 +299,8 < at >< at > static void __devexit em_gio_irq_domain_
 {
 struct gpio_em_config *pdata = p->pdev->dev.platform_data;
 
-irq_free_descs(p->irq_base, pdata->number_of_pins);
+if (p->irq_base)
+irq_free_descs(p->irq_base, pdata->number_of_pins);
 /* FIXME: irq domain wants to be freed! */
 }
 
< at >< at > -340,7 +370,11 < at >< at > static int __devinit em_gio_probe(struct
 irq_chip->irq_set_type = em_gio_irq_set_type;
 irq_chip->flags= IRQCHIP_SKIP_SET_WAKE;
 
-ret = em_gio_irq_domain_init(p);
+if (pdata->irq_base)
+ret = em_gio_irq_domain_init_legacy(p); /* static */
+else
+ret = em_gio_irq_domain_init_linear(p); /* dynamic */
+
 if (ret) {
 dev_err(&pdev->dev, "cannot initialize irq domain\n");
 goto err3;
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[PATCH] gpio: Emma Mobile GPIO driver V2

Magnus Damm — 2012-05-15T15:43:33

From: Magnus Damm <damm< at >opensource.se>

This patch is V2 of the Emma Mobile GPIO driver. This
driver is designed to be reusable between multiple SoCs
that share the same basic building block, but so far it
has only been used on Emma Mobile EV2.

Each driver instance handles 32 GPIOs with individually
maskable IRQs. The driver operates on two I/O memory 
ranges and the 32 GPIOs are hooked up to two interrupts.

In the case of Emma Mobile EV2 this GPIO building block
is used as main external interrupt controller hooking up
159 GPIOS as 159 interrupts via 5 driver instances and
10 interrupts to the GIC and the Cortex-A9 Dual.

Signed-off-by: Magnus Damm <damm< at >opensource.se>
---

 Changes since V1:
 - use inline for private data functions using container_of() 
 - use BIT(n) instead of 1 << n
 - added legacy irq domain support for static mappings
 - use irqd_to_hwirq() instead of own offset calculation
 - convert irqchip callbacks to not care about virq
 - rework IRQ handler to read interrupt status inside loop

 Changes not made:
 - ioread/iowrite are still used over readl/writel
 - no request_mem_region
 - no devm_ alloc/ioremap
 - kept the kconfig dependencies as in V1

 Many thanks to Linus Walleij and Arnd Bergmann for
 their help with the code review!

 Incremental DT feature patch will be posted shortly.

 drivers/gpio/Kconfig                  |    6 
 drivers/gpio/Makefile                 |    1 
 drivers/gpio/gpio-em.c                |  418 +++++++++++++++++++++++++++++++++
 include/linux/platform_data/gpio-em.h |   10 
 4 files changed, 435 insertions(+)

--- 0001/drivers/gpio/Kconfig
+++ work/drivers/gpio/Kconfig2012-05-15 14:50:42.000000000 +0900
< at >< at > -103,6 +103,12 < at >< at > config GPIO_IT8761E
 help
   Say yes here to support GPIO functionality of IT8761E super I/O chip.
 
+config GPIO_EM
+tristate "Emma Mobile GPIO"
+depends on ARM
+help
+  Say yes here to support GPIO on Renesas Emma Mobile SoCs.
+
 config GPIO_EP93XX
 def_bool y
 depends on ARCH_EP93XX
--- 0001/drivers/gpio/Makefile
+++ work/drivers/gpio/Makefile2012-05-15 14:50:42.000000000 +0900
< at >< at > -16,6 +16,7 < at >< at > obj-$(CONFIG_GPIO_BT8XX)+= gpio-bt8xx.o
 obj-$(CONFIG_GPIO_CS5535)+= gpio-cs5535.o
 obj-$(CONFIG_GPIO_DA9052)+= gpio-da9052.o
 obj-$(CONFIG_ARCH_DAVINCI)+= gpio-davinci.o
+obj-$(CONFIG_GPIO_EM)+= gpio-em.o
 obj-$(CONFIG_GPIO_EP93XX)+= gpio-ep93xx.o
 obj-$(CONFIG_GPIO_GE_FPGA)+= gpio-ge.o
 obj-$(CONFIG_GPIO_ICH)+= gpio-ich.o
--- /dev/null
+++ work/drivers/gpio/gpio-em.c2012-05-16 00:07:20.000000000 +0900
< at >< at > -0,0 +1,418 < at >< at >
+/*
+ * Emma Mobile GPIO Support - GIO
+ *
+ *  Copyright (C) 2012 Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/bitops.h>
+#include <linux/err.h>
+#include <linux/gpio.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/platform_data/gpio-em.h>
+
+struct em_gio_priv {
+void __iomem *base0;
+void __iomem *base1;
+unsigned int irq_base;
+spinlock_t sense_lock;
+struct platform_device *pdev;
+struct gpio_chip gpio_chip;
+struct irq_chip irq_chip;
+struct irq_domain *irq_domain;
+};
+
+#define GIO_E1 0x00
+#define GIO_E0 0x04
+#define GIO_EM 0x04
+#define GIO_OL 0x08
+#define GIO_OH 0x0c
+#define GIO_I 0x10
+#define GIO_IIA 0x14
+#define GIO_IEN 0x18
+#define GIO_IDS 0x1c
+#define GIO_IIM 0x1c
+#define GIO_RAW 0x20
+#define GIO_MST 0x24
+#define GIO_IIR 0x28
+
+#define GIO_IDT0 0x40
+#define GIO_IDT1 0x44
+#define GIO_IDT2 0x48
+#define GIO_IDT3 0x4c
+#define GIO_RAWBL 0x50
+#define GIO_RAWBH 0x54
+#define GIO_IRBL 0x58
+#define GIO_IRBH 0x5c
+
+#define GIO_IDT(n) (GIO_IDT0 + ((n) * 4))
+
+static inline unsigned long em_gio_read(struct em_gio_priv *p, int offs)
+{
+if (offs < GIO_IDT0)
+return ioread32(p->base0 + offs);
+else
+return ioread32(p->base1 + (offs - GIO_IDT0));
+}
+
+static inline void em_gio_write(struct em_gio_priv *p, int offs,
+unsigned long value)
+{
+if (offs < GIO_IDT0)
+iowrite32(value, p->base0 + offs);
+else
+iowrite32(value, p->base1 + (offs - GIO_IDT0));
+}
+
+static inline struct em_gio_priv *irq_to_priv(struct irq_data *d)
+{
+struct irq_chip *chip = irq_data_get_irq_chip(d);
+return container_of(chip, struct em_gio_priv, irq_chip);
+}
+
+static void em_gio_irq_disable(struct irq_data *d)
+{
+struct em_gio_priv *p = irq_to_priv(d);
+
+em_gio_write(p, GIO_IDS, BIT(irqd_to_hwirq(d)));
+}
+
+static void em_gio_irq_enable(struct irq_data *d)
+{
+struct em_gio_priv *p = irq_to_priv(d);
+
+em_gio_write(p, GIO_IEN, BIT(irqd_to_hwirq(d)));
+}
+
+#define GIO_ASYNC(x) (x + 8)
+
+static unsigned char em_gio_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
+[IRQ_TYPE_EDGE_RISING] = GIO_ASYNC(0x00),
+[IRQ_TYPE_EDGE_FALLING] = GIO_ASYNC(0x01),
+[IRQ_TYPE_LEVEL_HIGH] = GIO_ASYNC(0x02),
+[IRQ_TYPE_LEVEL_LOW] = GIO_ASYNC(0x03),
+[IRQ_TYPE_EDGE_BOTH] = GIO_ASYNC(0x04),
+};
+
+static int em_gio_irq_set_type(struct irq_data *d, unsigned int type)
+{
+unsigned char value = em_gio_sense_table[type & IRQ_TYPE_SENSE_MASK];
+struct em_gio_priv *p = irq_to_priv(d);
+unsigned int reg, offset, shift;
+unsigned long flags;
+unsigned long tmp;
+
+if (!value)
+return -EINVAL;
+
+offset = irqd_to_hwirq(d);
+
+pr_debug("gio: sense irq = %d, mode = %d\n", offset, value);
+
+/* 8 x 4 bit fields in 4 IDT registers */
+reg = GIO_IDT(offset >> 3);
+shift = (offset & 0x07) << 4;
+
+spin_lock_irqsave(&p->sense_lock, flags);
+
+/* disable the interrupt in IIA */
+tmp = em_gio_read(p, GIO_IIA);
+tmp &= ~BIT(offset);
+em_gio_write(p, GIO_IIA, tmp);
+
+/* change the sense setting in IDT */
+tmp = em_gio_read(p, reg);
+tmp &= ~(0xf << shift);
+tmp |= value << shift;
+em_gio_write(p, reg, tmp);
+
+/* clear pending interrupts */
+em_gio_write(p, GIO_IIR, BIT(offset));
+
+/* enable the interrupt in IIA */
+tmp = em_gio_read(p, GIO_IIA);
+tmp |= BIT(offset);
+em_gio_write(p, GIO_IIA, tmp);
+
+spin_unlock_irqrestore(&p->sense_lock, flags);
+
+return 0;
+}
+
+static irqreturn_t em_gio_irq_handler(int irq, void *dev_id)
+{
+struct em_gio_priv *p = dev_id;
+unsigned long pending;
+unsigned int offset, irqs_handled = 0;
+
+while ((pending = em_gio_read(p, GIO_MST))) {
+offset = __ffs(pending);
+em_gio_write(p, GIO_IIR, BIT(offset));
+generic_handle_irq(irq_find_mapping(p->irq_domain, offset));
+irqs_handled++;
+}
+
+return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
+}
+
+static inline struct em_gio_priv *gpio_to_priv(struct gpio_chip *chip)
+{
+return container_of(chip, struct em_gio_priv, gpio_chip);
+}
+
+static int em_gio_direction_input(struct gpio_chip *chip, unsigned offset)
+{
+em_gio_write(gpio_to_priv(chip), GIO_E0, BIT(offset));
+return 0;
+}
+
+static int em_gio_get(struct gpio_chip *chip, unsigned offset)
+{
+return (int)(em_gio_read(gpio_to_priv(chip), GIO_I) & BIT(offset));
+}
+
+static void __em_gio_set(struct gpio_chip *chip, unsigned int reg,
+ unsigned shift, int value)
+{
+/* upper 16 bits contains mask and lower 16 actual value */
+em_gio_write(gpio_to_priv(chip), reg,
+     (1 << (shift + 16)) | (value << shift));
+}
+
+static void em_gio_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+/* output is split into two registers */
+if (offset < 16)
+__em_gio_set(chip, GIO_OL, offset, value);
+else
+__em_gio_set(chip, GIO_OH, offset - 16, value);
+}
+
+static int em_gio_direction_output(struct gpio_chip *chip, unsigned offset,
+   int value)
+{
+/* write GPIO value to output before selecting output mode of pin */
+em_gio_set(chip, offset, value);
+em_gio_write(gpio_to_priv(chip), GIO_E1, BIT(offset));
+return 0;
+}
+
+static int em_gio_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+return irq_find_mapping(gpio_to_priv(chip)->irq_domain, offset);
+}
+
+static int em_gio_irq_domain_map(struct irq_domain *h, unsigned int virq,
+ irq_hw_number_t hw)
+{
+struct em_gio_priv *p = h->host_data;
+
+pr_debug("gio: map hw irq = %d, virq = %d\n", (int)hw, virq);
+
+irq_set_chip_data(virq, h->host_data);
+irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
+set_irq_flags(virq, IRQF_VALID); /* kill me now */
+return 0;
+}
+
+static struct irq_domain_ops em_gio_irq_domain_ops = {
+.map= em_gio_irq_domain_map,
+};
+
+static int __devinit em_gio_irq_domain_init(struct em_gio_priv *p)
+{
+struct platform_device *pdev = p->pdev;
+struct gpio_em_config *pdata = pdev->dev.platform_data;
+
+p->irq_base = irq_alloc_descs(pdata->irq_base, 0,
+      pdata->number_of_pins, numa_node_id());
+if (IS_ERR_VALUE(p->irq_base)) {
+dev_err(&pdev->dev, "cannot get irq_desc\n");
+return -ENXIO;
+}
+pr_debug("gio: hw base = %d, nr = %d, sw base = %d\n",
+ pdata->gpio_base, pdata->number_of_pins, p->irq_base);
+
+p->irq_domain = irq_domain_add_legacy(pdev->dev.of_node,
+      pdata->number_of_pins,
+      p->irq_base, 0,
+      &em_gio_irq_domain_ops, p);
+if (!p->irq_domain) {
+irq_free_descs(p->irq_base, pdata->number_of_pins);
+return -ENXIO;
+}
+
+return 0;
+}
+
+static void __devexit em_gio_irq_domain_cleanup(struct em_gio_priv *p)
+{
+struct gpio_em_config *pdata = p->pdev->dev.platform_data;
+
+irq_free_descs(p->irq_base, pdata->number_of_pins);
+/* FIXME: irq domain wants to be freed! */
+}
+
+static int __devinit em_gio_probe(struct platform_device *pdev)
+{
+struct gpio_em_config *pdata = pdev->dev.platform_data;
+struct em_gio_priv *p;
+struct resource *io[2], *irq[2];
+struct gpio_chip *gpio_chip;
+struct irq_chip *irq_chip;
+const char *name = dev_name(&pdev->dev);
+int ret;
+
+p = kzalloc(sizeof(*p), GFP_KERNEL);
+if (!p) {
+dev_err(&pdev->dev, "failed to allocate driver data\n");
+ret = -ENOMEM;
+goto err0;
+}
+
+p->pdev = pdev;
+platform_set_drvdata(pdev, p);
+spin_lock_init(&p->sense_lock);
+
+io[0] = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+io[1] = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+irq[0] = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+irq[1] = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
+
+if (!io[0] || !io[1] || !irq[0] || !irq[1] || !pdata) {
+dev_err(&pdev->dev, "missing IRQ, IOMEM or configuration\n");
+ret = -EINVAL;
+goto err1;
+}
+
+p->base0 = ioremap_nocache(io[0]->start, resource_size(io[0]));
+if (!p->base0) {
+dev_err(&pdev->dev, "failed to remap low I/O memory\n");
+ret = -ENXIO;
+goto err1;
+}
+
+p->base1 = ioremap_nocache(io[1]->start, resource_size(io[1]));
+if (!p->base1) {
+dev_err(&pdev->dev, "failed to remap high I/O memory\n");
+ret = -ENXIO;
+goto err2;
+}
+
+gpio_chip = &p->gpio_chip;
+gpio_chip->direction_input = em_gio_direction_input;
+gpio_chip->get = em_gio_get;
+gpio_chip->direction_output = em_gio_direction_output;
+gpio_chip->set = em_gio_set;
+gpio_chip->to_irq = em_gio_to_irq;
+gpio_chip->label = name;
+gpio_chip->owner = THIS_MODULE;
+gpio_chip->base = pdata->gpio_base;
+gpio_chip->ngpio = pdata->number_of_pins;
+
+irq_chip = &p->irq_chip;
+irq_chip->name = name;
+irq_chip->irq_mask = em_gio_irq_disable;
+irq_chip->irq_unmask = em_gio_irq_enable;
+irq_chip->irq_enable = em_gio_irq_enable;
+irq_chip->irq_disable = em_gio_irq_disable;
+irq_chip->irq_set_type = em_gio_irq_set_type;
+irq_chip->flags= IRQCHIP_SKIP_SET_WAKE;
+
+ret = em_gio_irq_domain_init(p);
+if (ret) {
+dev_err(&pdev->dev, "cannot initialize irq domain\n");
+goto err3;
+}
+
+if (request_irq(irq[0]->start, em_gio_irq_handler, 0, name, p)) {
+dev_err(&pdev->dev, "failed to request low IRQ\n");
+ret = -ENOENT;
+goto err4;
+}
+
+if (request_irq(irq[1]->start, em_gio_irq_handler, 0, name, p)) {
+dev_err(&pdev->dev, "failed to request high IRQ\n");
+ret = -ENOENT;
+goto err5;
+}
+
+ret = gpiochip_add(gpio_chip);
+if (ret) {
+dev_err(&pdev->dev, "failed to add GPIO controller\n");
+goto err6;
+}
+return 0;
+
+err6:
+free_irq(irq[1]->start, pdev);
+err5:
+free_irq(irq[0]->start, pdev);
+err4:
+em_gio_irq_domain_cleanup(p);
+err3:
+iounmap(p->base1);
+err2:
+iounmap(p->base0);
+err1:
+kfree(p);
+err0:
+return ret;
+}
+
+static int __devexit em_gio_remove(struct platform_device *pdev)
+{
+struct em_gio_priv *p = platform_get_drvdata(pdev);
+struct resource *irq[2];
+int ret;
+
+ret = gpiochip_remove(&p->gpio_chip);
+if (ret)
+return ret;
+
+irq[0] = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+irq[1] = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
+
+free_irq(irq[1]->start, pdev);
+free_irq(irq[0]->start, pdev);
+em_gio_irq_domain_cleanup(p);
+iounmap(p->base1);
+iounmap(p->base0);
+kfree(p);
+return 0;
+}
+
+static struct platform_driver em_gio_device_driver = {
+.probe= em_gio_probe,
+.remove= __devexit_p(em_gio_remove),
+.driver= {
+.name= "em_gio",
+}
+};
+
+module_platform_driver(em_gio_device_driver);
+
+MODULE_AUTHOR("Magnus Damm");
+MODULE_DESCRIPTION("Renesas Emma Mobile GIO Driver");
+MODULE_LICENSE("GPL v2");
--- /dev/null
+++ work/include/linux/platform_data/gpio-em.h2012-05-15 14:50:43.000000000 +0900
< at >< at > -0,0 +1,10 < at >< at >
+#ifndef __GPIO_EM_H__
+#define __GPIO_EM_H__
+
+struct gpio_em_config {
+unsigned int gpio_base;
+unsigned int irq_base;
+unsigned int number_of_pins;
+};
+
+#endif /* __GPIO_EM_H__ */
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Will You Be Trusted?

Mr.Saeed Ahmed. — 2012-05-09T06:27:58


Dear Friend,

As you read this, I don't want you to feel sorry for me,because, I
believe everyone will die someday,and am contacting you because
I really do need your help and I want you to help me with all your
effort and time for just seven to fourteen workings days of your time.I
want you to be honest and truthful with me that you will help me
with my last wish as a dying man.

Please i need a reliable person who will usethe Money($18 milliondollars)to
build orphanage home or charity organization.

Please kindly reply to my most confidential email if you are really
interested in helping me please: mr.saeed01< at >linuxmail.org


God be with you.

Mr.Saeed Ahmed.

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[PATCH] sh: Fix mistake of the member variable of plat_sci_port for SH7343

Nobuhiro Iwamatsu — 2012-05-15T01:26:11

The current code was going to initialize irq of plat_sci_port.
Not irq, irqs is right.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj< at >renesas.com>
---
 arch/sh/kernel/cpu/sh4a/setup-sh7343.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
index 476f474..5773643 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
< at >< at > -56,7 +56,7 < at >< at > static struct plat_sci_port scif2_platform_data = {
 .scscr= SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
 .scbrr_algo_id= SCBRR_ALGO_2,
 .type           = PORT_SCIF,
-.irq            = SCIx_IRQ_MUXED(evt2irq(0xC40)),
+.irqs           = SCIx_IRQ_MUXED(evt2irq(0xC40)),
 };
 
 static struct platform_device scif2_device = {

[PATCH v4 0/8] sh_flctl hardware ECC mode cleanup

Bastian Hecht — 2012-05-14T12:14:39

changelog v4:

  - removed arch/arm related patches
  - rebased on current l2-mtd.git
  - fixed some compiler warnings
- patch 2: use "int irq" when removing irq binding in error case to fix smatch breakage
- patch 7 and 8: just directly use the void __iomem pointer instead of the unprecise void pointer to fix sparse breakage

changelog v3:

Just a rebase on current l2-mtd.git.

changelog v2:
  - extract the iounmap calls from patch "Add support for error IRQ" into a new patch.
  - swapped patches "Add support for error IRQ" and "Add error IRQ resource"
  - corrected an indentation mistake

This series cleans up the flctl when run in hardware ecc mode. The first 2 patches make sure we catch all errors that result from hardware transmission. The other patches handle how the ecc is layed out, correct some code to write and read it and make sure we propagate the statistics about errors/repairs to the nand base.

Bastian Hecht (8):
  mtd: sh_flctl: Add missing iounmap()
  mtd: sh_flctl: Add support for error IRQ
  mtd: sh_flctl: Use different OOB layout
  mtd: sh_flctl: Fix hardware ECC behaviour
  mtd: sh_flctl: Simplify the hardware ecc page read/write
  mtd: sh_flctl: Group sector accesses into a single transfer
  mtd: sh_flctl: Restructure the hardware ECC handling
  mtd: sh_flctl: Use user oob data in hardware ECC mode

 drivers/mtd/nand/sh_flctl.c  |  299 ++++++++++++++++++++++++------------------
 include/linux/mtd/sh_flctl.h |   23 +++-
 2 files changed, 187 insertions(+), 135 deletions(-)