gmane.linux.ports.arm.kernel
http://blog.gmane.org/gmane.linux.ports.arm.kernel
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1901-01-01T00:00+00:00
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[PATCH] ARM: imx_v6_v7_defconfig: Add sound support
http://comments.gmane.org/gmane.linux.ports.arm.kernel/169465
<pre>From: Fabio Estevam <fabio.estevam< at >freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam< at >freescale.com>
---
arch/arm/configs/imx_v6_v7_defconfig | 10 ++++++++++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index b1d3675..59beb7a 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
< at >< at > -131,6 +131,8 < at >< at > CONFIG_GPIO_SYSFS=y
CONFIG_WATCHDOG=y
CONFIG_IMX2_WDT=y
CONFIG_MFD_MC13XXX=y
+CONFIG_MFD_MC13XXX_SPI=y
+CONFIG_MFD_MC13XXX_I2C=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_MC13783=y
< at >< at > -166,6 +168,14 < at >< at > CONFIG_LOGO=y
CONFIG_LOGO_LINUX_MONO=y
CONFIG_LOGO_LINUX_VGA16=y
CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_SOC=y
+CONFIG_SND_IMX_SOC=y
+CONFIG_SND_SOC_PHYCORE_AC97=y
+CONFIG_SND_SOC_EUKREA_TLV320=y
+CONFIG_SND_SOC_IMX_SGTL5000=y
+CONFIG_SND_SOC_IMX_MC13783=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_MXC=y
</pre>
Fabio Estevam
2012-05-26T16:52:08
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[PATCH v9 0/3] MTD: at91: Add PMECC support for at91 nand flash driver
http://comments.gmane.org/gmane.linux.ports.arm.kernel/169456
<pre>Code is based on 3.4-rc2
Changes since v8,
use _relaxed read/write in most place. use writel in operations of Control Register since it needs memory barrier.
allocate the data for PMECC computation.
add pmecc prefix for related variable/functions.
modify code according to J.C's suggestion. except:
>> +for (i = 2; i <= 2 * host->cap; i += 2) {
> manage the j in the for loop
since that will change to:
+for (i = 2, j = 1; i <= 2 * host->cap; i += 2, j = i / 2) {
it is not as simple as original one.
Changes since v7,
add time out for PMECC status reading.
modify the oobfree[0].offset to 2.
fix coding style.
Changes since v6,
split into 3 patches.
remove of_flat_dt_is_compatible() function. use additional dt parameter "has-pmecc".
refine the error handling code.
refine original atmel_nand_init_params() function.
Changes since v5,
add has_pmecc field to replace cpu_has_pmecc() function. Use compatible check in when proble.
simplify the pmecc_get_ecc_bytes() function.
Changes since v4,
fix typo and checkpatch warnings.
fix according to JC's suggestion. replace cpu_is_xxx() with DT
modify dt binding atmel nand document to add pmecc support.
tested in sam9263 without break hw ecc.
add ecc.strength.
Josh Wu (3):
extract the hw ecc function.
add DT variables.
add pmecc support
.../devicetree/bindings/mtd/atmel-nand.txt | 6 +
drivers/mtd/nand/atmel_nand.c | 939 ++++++++++++++++++--
drivers/mtd/nand/atmel_nand_ecc.h | 127 ++-
3 files changed, 997 insertions(+), 75 deletions(-)
</pre>
Josh Wu
2012-05-26T13:24:34
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[PATCH 01/15] ARM: mx5: Use clk_prepare_enable/clk_disable_unprepare
http://comments.gmane.org/gmane.linux.ports.arm.kernel/169418
<pre>From: Fabio Estevam <fabio.estevam< at >freescale.com>
Prepare the clock before enabling it.
Cc: <linux-arm-kernel< at >lists.infradead.org>
Signed-off-by: Fabio Estevam <fabio.estevam< at >freescale.com>
---
arch/arm/mach-imx/mm-imx5.c | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c
index feeee17..fcad95c 100644
--- a/arch/arm/mach-imx/mm-imx5.c
+++ b/arch/arm/mach-imx/mm-imx5.c
< at >< at > -35,11 +35,11 < at >< at > static void imx5_idle(void)
return;
clk_prepare(gpc_dvfs_clk);
}
-clk_enable(gpc_dvfs_clk);
+clk_prepare_enable(gpc_dvfs_clk);
mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
if (!tzic_enable_wake())
cpu_do_idle();
-clk_disable(gpc_dvfs_clk);
+clk_disable_unprepare(gpc_dvfs_clk);
}
/*
</pre>
Fabio Estevam
2012-05-25T23:14:42
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[STABLE PATCH] ARM: 7409/1: Do not call flush_cache_user_range with mmap_sem held
http://comments.gmane.org/gmane.linux.ports.arm.kernel/169382
<pre>From: Dima Zavin <dima< at >android.com>
commit 435a7ef52db7d86e67a009b36cac1457f8972391 upstream
We can't be holding the mmap_sem while calling flush_cache_user_range
because the flush can fault. If we fault on a user address, the
page fault handler will try to take mmap_sem again. Since both places
acquire the read lock, most of the time it succeeds. However, if another
thread tries to acquire the write lock on the mmap_sem (e.g. mmap) in
between the call to flush_cache_user_range and the fault, the down_read
in do_page_fault will deadlock.
[will: removed drop of vma parameter as already queued by rmk (7365/1)]
Cc: <stable< at >vger.kernel.org> # 2.6.32+: 4542b6a0: ARM: 7365/1
Cc: <stable< at >vger.kernel.org> # 2.6.32+
Acked-by: Catalin Marinas <catalin.marinas< at >arm.com>
Signed-off-by: Dima Zavin <dima< at >android.com>
Signed-off-by: John Stultz <john.stultz< at >linaro.org>
Signed-off-by: Will Deacon <will.deacon< at >arm.com>
Signed-off-by: Russell King <rmk+kernel< at >arm.linux.org.uk>
---
Greg: This patch is a candidate for -stable, but its dependency (listed
above) wasn't marked as such, hence this retrospective submission.
arch/arm/kernel/traps.c | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index 55b2f3d..63d402f 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
< at >< at > -496,7 +496,9 < at >< at > do_cache_op(unsigned long start, unsigned long end, int flags)
if (end > vma->vm_end)
end = vma->vm_end;
+up_read(&mm->mmap_sem);
flush_cache_user_range(start, end);
+return;
}
up_read(&mm->mmap_sem);
}
</pre>
Will Deacon
2012-05-25T14:38:04
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[PATCH 1/2] mtd mxc_nand: use 32bit copy functions
http://comments.gmane.org/gmane.linux.ports.arm.kernel/169380
<pre>The following commit changes the function used to copy from/to
the hardware buffer to memcpy_[from|to]io. This does not work
since the hardware cannot handle the byte accesses used by these
functions. Instead of reverting this patch introduce 32bit
correspondents of these functions.
commit 5775ba36ea9c760c2d7e697dac04f2f7fc95aa62
Author: Uwe Kleine-König <u.kleine-koenig< at >pengutronix.de>
Date: Tue Apr 24 10:05:22 2012 +0200
mtd: mxc_nand: fix several sparse warnings about incorrect address space
Signed-off-by: Uwe Kleine-König <u.kleine-koenig< at >pengutronix.de>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy< at >linux.intel.com>
Signed-off-by: Sascha Hauer <s.hauer< at >pengutronix.de>
Cc: Uwe Kleine-König <u.kleine-koenig< at >pengutronix.de>
---
drivers/mtd/nand/mxc_nand.c | 36 ++++++++++++++++++++++++++++--------
1 file changed, 28 insertions(+), 8 deletions(-)
diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
index fd14966..4d27ddc 100644
--- a/drivers/mtd/nand/mxc_nand.c
+++ b/drivers/mtd/nand/mxc_nand.c
< at >< at > -273,6 +273,26 < at >< at > static struct nand_ecclayout nandv2_hw_eccoob_4k = {
static const char *part_probes[] = { "RedBoot", "cmdlinepart", "ofpart", NULL };
+static void memcpy32_fromio(void *trg, const volatile void __iomem *src, size_t size)
+{
+int i;
+u32 *t = trg;
+const volatile u32 *s = src;
+
+for (i = 0; i < (size >> 2); i++)
+*t++ = __raw_readl(s++);
+}
+
+static void memcpy32_toio(volatile void __iomem *trg, const void *src, int size)
+{
+int i;
+volatile u32 *t = trg;
+const u32 *s = src;
+
+for (i = 0; i < (size >> 2); i++)
+__raw_writel(*s++, t++);
+}
+
static int check_int_v3(struct mxc_nand_host *host)
{
uint32_t tmp;
< at >< at > -519,7 +539,7 < at >< at > static void send_read_id_v3(struct mxc_nand_host *host)
wait_op_done(host, true);
-memcpy_fromio(host->data_buf, host->main_area0, 16);
+memcpy32_fromio(host->data_buf, host->main_area0, 16);
}
/* Request the NANDFC to perform a read of the NAND device ID. */
< at >< at > -535,7 +555,7 < at >< at > static void send_read_id_v1_v2(struct mxc_nand_host *host)
/* Wait for operation to complete */
wait_op_done(host, true);
-memcpy_fromio(host->data_buf, host->main_area0, 16);
+memcpy32_fromio(host->data_buf, host->main_area0, 16);
if (this->options & NAND_BUSWIDTH_16) {
/* compress the ID info */
< at >< at > -797,16 +817,16 < at >< at > static void copy_spare(struct mtd_info *mtd, bool bfrom)
if (bfrom) {
for (i = 0; i < n - 1; i++)
-memcpy_fromio(d + i * j, s + i * t, j);
+memcpy32_fromio(d + i * j, s + i * t, j);
/* the last section */
-memcpy_fromio(d + i * j, s + i * t, mtd->oobsize - i * j);
+memcpy32_fromio(d + i * j, s + i * t, mtd->oobsize - i * j);
} else {
for (i = 0; i < n - 1; i++)
-memcpy_toio(&s[i * t], &d[i * j], j);
+memcpy32_toio(&s[i * t], &d[i * j], j);
/* the last section */
-memcpy_toio(&s[i * t], &d[i * j], mtd->oobsize - i * j);
+memcpy32_toio(&s[i * t], &d[i * j], mtd->oobsize - i * j);
}
}
< at >< at > -1070,7 +1090,7 < at >< at > static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
host->devtype_data->send_page(mtd, NFC_OUTPUT);
-memcpy_fromio(host->data_buf, host->main_area0, mtd->writesize);
+memcpy32_fromio(host->data_buf, host->main_area0, mtd->writesize);
copy_spare(mtd, true);
break;
< at >< at > -1086,7 +1106,7 < at >< at > static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
break;
case NAND_CMD_PAGEPROG:
-memcpy_toio(host->main_area0, host->data_buf, mtd->writesize);
+memcpy32_toio(host->main_area0, host->data_buf, mtd->writesize);
copy_spare(mtd, false);
host->devtype_data->send_page(mtd, NFC_INPUT);
host->devtype_data->send_cmd(host, command, true);
</pre>
Sascha Hauer
2012-05-25T14:22:41
-
Booting mx27 on linux-next
http://comments.gmane.org/gmane.linux.ports.arm.kernel/169379
<pre>Hi Sascha,
Just tried booting a mx27pdk on linux-next and it failed to boot.
Any patches I am missing?
Just wanted to check with you first prior to start debugging it.
Regards,
Fabio Estevam
</pre>
Fabio Estevam
2012-05-25T13:56:07
-
[PATCH] ARM: at91: aic can use fast eoi handler type
http://comments.gmane.org/gmane.linux.ports.arm.kernel/169371
<pre>From: Ludovic Desroches <ludovic.desroches< at >atmel.com>
The Advanced Interrupt Controller allows to use the fast EOI handler type.
It lets remove the Atmel specific workaround into arch/arm/kernel/irq.c used
to indicate to the AIC the end of the interrupt treatment.
Signed-off-by: Ludovic Desroches <ludovic.desroches< at >atmel.com>
---
arch/arm/kernel/irq.c | 3 ---
arch/arm/mach-at91/gpio.c | 10 ++++++++--
arch/arm/mach-at91/include/mach/irqs.h | 7 -------
arch/arm/mach-at91/irq.c | 10 ++++++++--
4 files changed, 16 insertions(+), 14 deletions(-)
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index 71ccdbf..6236d1a 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
< at >< at > -85,9 +85,6 < at >< at > void handle_IRQ(unsigned int irq, struct pt_regs *regs)
generic_handle_irq(irq);
}
-/* AT91 specific workaround */
-irq_finish(irq);
-
irq_exit();
set_irq_regs(old_regs);
}
diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
index 325837a..ee38e6d 100644
--- a/arch/arm/mach-at91/gpio.c
+++ b/arch/arm/mach-at91/gpio.c
< at >< at > -520,6 +520,11 < at >< at > static void gpio_irq_unmask(struct irq_data *d)
__raw_writel(mask, pio + PIO_IER);
}
+static void gpio_irq_eoi(struct irq_data *d)
+{
+at91_aic_write(AT91_AIC_EOICR, 0);
+}
+
static int gpio_irq_type(struct irq_data *d, unsigned type)
{
switch (type) {
< at >< at > -581,6 +586,7 < at >< at > static struct irq_chip gpio_irqchip = {
.irq_unmask= gpio_irq_unmask,
/* .irq_set_type is set dynamically */
.irq_set_wake= gpio_irq_set_wake,
+.irq_eoi= gpio_irq_eoi,
};
static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
< at >< at > -725,7 +731,7 < at >< at > static int at91_gpio_irq_map(struct irq_domain *h, unsigned int virq,
* shorter, and the AIC handles interrupts sanely.
*/
irq_set_chip_and_handler(virq, &gpio_irqchip,
- handle_simple_irq);
+ handle_fasteoi_irq);
set_irq_flags(virq, IRQF_VALID);
irq_set_chip_data(virq, at91_gpio);
< at >< at > -839,7 +845,7 < at >< at > void __init at91_gpio_irq_setup(void)
* shorter, and the AIC handles interrupts sanely.
*/
irq_set_chip_and_handler(virq, &gpio_irqchip,
- handle_simple_irq);
+ handle_fasteoi_irq);
set_irq_flags(virq, IRQF_VALID);
irq_set_chip_data(virq, this);
diff --git a/arch/arm/mach-at91/include/mach/irqs.h b/arch/arm/mach-at91/include/mach/irqs.h
index ac8b7df..2d510ee 100644
--- a/arch/arm/mach-at91/include/mach/irqs.h
+++ b/arch/arm/mach-at91/include/mach/irqs.h
< at >< at > -28,13 +28,6 < at >< at >
/*
- * Acknowledge interrupt with AIC after interrupt has been handled.
- * (by kernel/irq.c)
- */
-#define irq_finish(irq) do { at91_aic_write(AT91_AIC_EOICR, 0); } while (0)
-
-
-/*
* IRQ interrupt symbols are the AT91xxx_ID_* symbols
* for IRQs handled directly through the AIC, or else the AT91_PIN_*
* symbols in gpio.h for ones handled indirectly as GPIOs.
diff --git a/arch/arm/mach-at91/irq.c b/arch/arm/mach-at91/irq.c
index 601b4ee..40714f1 100644
--- a/arch/arm/mach-at91/irq.c
+++ b/arch/arm/mach-at91/irq.c
< at >< at > -55,6 +55,11 < at >< at > static void at91_aic_unmask_irq(struct irq_data *d)
at91_aic_write(AT91_AIC_IECR, 1 << d->hwirq);
}
+static void at91_aic_eoi(struct irq_data *d)
+{
+at91_aic_write(AT91_AIC_EOICR, 0);
+}
+
unsigned int at91_extern_irq;
#define is_extern_irq(hwirq) ((1 << (hwirq)) & at91_extern_irq)
< at >< at > -133,6 +138,7 < at >< at > static struct irq_chip at91_aic_chip = {
.irq_unmask= at91_aic_unmask_irq,
.irq_set_type= at91_aic_set_type,
.irq_set_wake= at91_aic_set_wake,
+.irq_eoi= at91_aic_eoi,
};
static void __init at91_aic_hw_init(unsigned int spu_vector)
< at >< at > -171,7 +177,7 < at >< at > static int at91_aic_irq_map(struct irq_domain *h, unsigned int virq,
/* Active Low interrupt, without priority */
at91_aic_write(AT91_AIC_SMR(hw), AT91_AIC_SRCTYPE_LOW);
-irq_set_chip_and_handler(virq, &at91_aic_chip, handle_level_irq);
+irq_set_chip_and_handler(virq, &at91_aic_chip, handle_fasteoi_irq);
set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
return 0;
< at >< at > -271,7 +277,7 < at >< at > void __init at91_aic_init(unsigned int priority[NR_AIC_IRQS])
/* Active Low interrupt, with the specified priority */
at91_aic_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]);
-irq_set_chip_and_handler(i, &at91_aic_chip, handle_level_irq);
+irq_set_chip_and_handler(i, &at91_aic_chip, handle_fasteoi_irq);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
}
</pre>
ludovic.desroches< at >atmel.com
2012-05-25T12:55:11
-
[PATCH 1/2] ARM: mx28: add gpmi-nand support
http://comments.gmane.org/gmane.linux.ports.arm.kernel/169351
<pre>add gpmi-nand device tree support.
add gpmi-nand pinctrl support.
Also enable the gpmi support for mx28-evk board.
Signed-off-by: Huang Shijie <b32955< at >freescale.com>
---
add pinctrl for gpmi-nand.
---
arch/arm/boot/dts/imx28-evk.dts | 6 ++++++
arch/arm/boot/dts/imx28.dtsi | 35 ++++++++++++++++++++++++++---------
2 files changed, 32 insertions(+), 9 deletions(-)
diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
index ee520a5..e53cf67 100644
--- a/arch/arm/boot/dts/imx28-evk.dts
+++ b/arch/arm/boot/dts/imx28-evk.dts
< at >< at > -22,6 +22,12 < at >< at >
apb< at >80000000 {
apbh< at >80000000 {
+gpmi-nand< at >8000c000 {
+pinctrl-names = "default";
+pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
+status = "okay";
+};
+
ssp0: ssp< at >80010000 {
compatible = "fsl,imx28-mmc";
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 4634cb8..2636339 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
< at >< at > -68,15 +68,15 < at >< at >
status = "disabled";
};
-bch< at >8000a000 {
-reg = <0x8000a000 2000>;
-interrupts = <41>;
-status = "disabled";
-};
-
-gpmi< at >8000c000 {
-reg = <0x8000c000 2000>;
-interrupts = <42 88>;
+gpmi-nand< at >8000c000 {
+compatible = "fsl,imx28-gpmi-nand";
+#address-cells = <1>;
+#size-cells = <1>;
+reg = <0x8000c000 2000>, <0x8000a000 2000>;
+reg-names = "gpmi-nand", "bch";
+interrupts = <88>, <41>;
+interrupt-names = "gpmi-dma", "bch";
+fsl,gpmi-dma-channel = <4>;
status = "disabled";
};
< at >< at > -167,6 +167,23 < at >< at >
fsl,pull-up = <0>;
};
+gpmi_pins_a: gpmi-nand< at >0 {
+reg = <0>;
+fsl,pinmux-ids = <0x0000 0x0010 0x0020
+0x0030 0x0040 0x0050 0x0060
+0x0070 0x0100 0x0110 0x0140
+0x0150 0x0180 0x0190 0x01a0
+0x01b0 0x01c0 >;
+fsl,drive-strength = <0>;
+fsl,voltage = <1>;
+fsl,pull-up = <0>;
+};
+
+gpmi_status_cfg: gpmi-status-cfg {
+fsl,pinmux-ids = <0x0180 0x0190 0x01c0>;
+fsl,drive-strength = <2>;
+};
+
mac0_pins_a: mac0< at >0 {
reg = <0>;
fsl,pinmux-ids = <0x4000 0x4010 0x4020
</pre>
Huang Shijie
2012-05-25T09:25:35
-
[PATCH 0/4] mmp audio support
http://comments.gmane.org/gmane.linux.ports.arm.kernel/169323
<pre>These four patches provide mmp audio support under alsa via dmaengine
Support platfrom pxa688 and pxa910
mmp_tdma.c and mmp-pcm.c is shared for pxa688 and pxa910
pxa688 (mmp2) use mmp2-sspa.c
pxa910 directly use pxa-ssp.c
mmp_tdma.c is under dmaengine framework
Verified on brownstone (pxa688) and ttc-dkb
Zhangfei Gao (4):
dmaengine: mmp_tdma: add mmp tdma support
ASoC: mmp: add audio dma support
ASOC: mmp: add sspa support
ASoC: add mmp brownstone support
drivers/dma/Kconfig | 10 +
drivers/dma/Makefile | 1 +
drivers/dma/mmp_tdma.c | 677 +++++++++++++++++++++++++++++++
include/linux/platform_data/mmp_audio.h | 22 +
include/linux/platform_data/mmp_dma.h | 20 +
sound/soc/pxa/Kconfig | 20 +
sound/soc/pxa/Makefile | 6 +
sound/soc/pxa/brownstone.c | 303 ++++++++++++++
sound/soc/pxa/mmp-pcm.c | 448 ++++++++++++++++++++
sound/soc/pxa/mmp-sspa.c | 536 ++++++++++++++++++++++++
sound/soc/pxa/mmp-sspa.h | 92 +++++
11 files changed, 2135 insertions(+), 0 deletions(-)
create mode 100644 drivers/dma/mmp_tdma.c
create mode 100644 include/linux/platform_data/mmp_audio.h
create mode 100644 include/linux/platform_data/mmp_dma.h
create mode 100644 sound/soc/pxa/brownstone.c
create mode 100644 sound/soc/pxa/mmp-pcm.c
create mode 100644 sound/soc/pxa/mmp-sspa.c
create mode 100644 sound/soc/pxa/mmp-sspa.h
</pre>
Zhangfei Gao
2012-05-25T07:10:59
-
[ehci-mxc] USB stopped working in i.MX27 based Visstrim_M10 board.
http://comments.gmane.org/gmane.linux.ports.arm.kernel/169237
<pre>Hi,
in kernel 3.4 USB doesn't work anymore in Visstrim_M10 board. It is
based on an i.MX27 chip and this is the log I get when connecting an
UVC webcam:
ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
ehci_hcd: block sizes: qh 64 qtd 96 itd 160 sitd 96
mxc-ehci mxc-ehci.0: initializing i.MX USB Controller
mxc-ehci mxc-ehci.0: Freescale On-Chip EHCI Host Controller
mxc-ehci mxc-ehci.0: new USB bus registered, assigned bus number 1
mxc-ehci mxc-ehci.0: reset hcs_params 0x10011 dbg=0 ind cc=0 pcc=0
ordered ports=1
mxc-ehci mxc-ehci.0: reset hcc_params 0006 thresh 0 uframes 256/512/1024 park
mxc-ehci mxc-ehci.0: park 0
mxc-ehci mxc-ehci.0: reset command 0080002 (park)=0 ithresh=8
period=1024 Reset HALT
mxc-ehci mxc-ehci.0: ...powerdown ports...
mxc-ehci mxc-ehci.0: irq 56, io mem 0x10024000
mxc-ehci mxc-ehci.0: init command 0010005 (park)=0 ithresh=1 period=512 RUN
mxc-ehci mxc-ehci.0: USB 2.0 started, EHCI 1.00
usb usb1: default language 0x0409
usb usb1: udev 1, busnum 1, minor = 0
usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
usb usb1: Product: Freescale On-Chip EHCI Host Controller
usb usb1: Manufacturer: Linux 3.4.0-00005-gf095ebc ehci_hcd
usb usb1: SerialNumber: mxc-ehci.0
usb usb1: usb_probe_device
usb usb1: configuration #1 chosen from 1 choice
usb usb1: adding 1-0:1.0 (config #1, interface 0)
hub 1-0:1.0: usb_probe_interface
hub 1-0:1.0: usb_probe_interface - got id
hub 1-0:1.0: USB hub found
hub 1-0:1.0: 1 port detected
hub 1-0:1.0: standalone hub
hub 1-0:1.0: individual port power switching
hub 1-0:1.0: individual port over-current protection
hub 1-0:1.0: Single TT
hub 1-0:1.0: TT requires at most 8 FS bit times (666 ns)
hub 1-0:1.0: power on to power good time: 20ms
hub 1-0:1.0: local power source is good
hub 1-0:1.0: enabling power on all ports
rtc-ds1307 0-0068: rtc core: registered m41t00 as rtc0
i2c /dev entries driver
soc-camera-pdrv soc-camera-pdrv.0: Probing soc-camera-pdrv.0
mx2-camera mx2-camera.0: Camera driver attached to camera 0
tvp5150 0-005d: chip found < at > 0xba (imx-i2c)
mxc-ehci mxc-ehci.0: GetStatus port:1 status 80001803 64 ACK POWER
sig=j CSC CONNECT
hub 1-0:1.0: port 1: status 0101 change 0001
tvp5150 0-005d: *** unknown tvp5151 chip detected.
tvp5150 0-005d: *** Rom ver is 1.0
hub 1-0:1.0: state 7 ports 1 chg 0002 evt 0000
hub 1-0:1.0: port 1, status 0101, change 0000, 12 Mb/s
usb 1-1: new high-speed USB device number 2 using mxc-ehci
mx2-camera mx2-camera.0: Camera driver detached from camera 0
mx2-camera mx2-camera.0: MX2 Camera (CSI) driver probed, clock
frequency: 6250000
m2m-deinterlace m2m-deinterlace.0: mem2mem-deinterlace Device
registered as /dev/video1
i.MX SDHC driver
Registered led device: visstrim:ld0
Registered led device: visstrim:ld1
Registered led device: visstrim:ld2
Registered led device: visstrim:ld3
mxc-ehci mxc-ehci.0: port 1 high speed
mxc-ehci mxc-ehci.0: GetStatus port:1 status 88001205 68 ACK POWER
sig=se0 LPM PE CONNECT
asoc: tlv320aic32x4-hifi <-> imx-ssi.0 mapping ok
TCP: cubic registered
NET: Registered protocol family 17
input: gpio-keys as /devices/platform/gpio-keys/input/input0
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 1
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 2
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 3
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 4
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 5
rtc-ds1307 0-0068: setting system clock to 2012-05-24 10:45:41 UTC (1337856341)
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 6
ALSA device list:
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 7
#0: visstrim_m10-audio
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 8
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 9
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 10
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 11
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 12
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 13
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 14
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 15
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 16
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 17
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 18
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 19
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 20
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 21
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 22
VFS: Mounted root (squashfs filesystem) readonly on device 31:2.
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 23
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 24
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 25
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 26
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 27
devtmpfs: mounted
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 28
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 29
Freeing init memory: 104K
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 30
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 31
mxc-ehci mxc-ehci.0: devpath 1 ep0in 3strikes
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 1
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 2
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 3
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 4
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 5
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 6
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 7
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 8
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 9
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 10
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 11
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 12
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 13
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 14
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 15
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 16
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 17
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 18
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 19
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 20
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 21
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 22
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 23
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 24
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 25
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 26
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 27
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 28
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 29
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 30
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 31
mxc-ehci mxc-ehci.0: devpath 1 ep0in 3strikes
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 1
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 2
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 3
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 4
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 5
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 6
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 7
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 8
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 9
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 10
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 11
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 12
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 13
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 14
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 15
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 16
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 17
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 18
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 19
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 20
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 21
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 22
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 23
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 24
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 25
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 26
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 27
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 28
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 29
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 30
mxc-ehci mxc-ehci.0: detected XactErr len 0/8 retry 31
mxc-ehci mxc-ehci.0: devpath 1 ep0in 3strikes
usb 1-1: device descriptor read/all, error -71
mxc-ehci mxc-ehci.0: port 1 high speed
mxc-ehci mxc-ehci.0: GetStatus port:1 status 80001805 64 ACK POWER
sig=j PE CONNECT
usb 1-1: new full-speed USB device number 3 using mxc-ehci
eth0: Freescale FEC PHY driver [Generic PHY]
(mii_bus:phy_addr=imx27-fec-1:1b, irq=-1)
PHY: imx27-fec-1:1b - Link is Up - 100/Full
usb 1-1: khubd timed out on ep0in len=0/64
usb 1-1: khubd timed out on ep0in len=0/64
usb 1-1: khubd timed out on ep0in len=0/64
usb 1-1: device descriptor read/64, error -110
usb usb1: clear tt buffer port 1, a0 ep0 t00080a88
usb 1-1: khubd timed out on ep0in len=0/64
usb usb1: clear tt buffer port 1, a0 ep0 t00000000
usb 1-1: khubd timed out on ep0in len=0/64
usb 1-1: khubd timed out on ep0in len=0/64
usb 1-1: device descriptor read/64, error -110
usb 1-1: new full-speed USB device number 4 using mxc-ehci
mx2-camera mx2-camera.0: Camera driver attached to camera 0
mx2-camera mx2-camera.0: Camera driver detached from camera 0
usb 1-1: khubd timed out on ep0out len=0/0
usb 1-1: khubd timed out on ep0out len=0/0
usb 1-1: device not accepting address 4, error -110
usb 1-1: new full-speed USB device number 5 using mxc-ehci
usb 1-1: khubd timed out on ep0out len=0/0
usb 1-1: khubd timed out on ep0out len=0/0
usb 1-1: device not accepting address 5, error -110
hub 1-0:1.0: unable to enumerate USB device on port 1
hub 1-0:1.0: state 7 ports 1 chg 0000 evt 0002
# lsusb
Bus 001 Device 001: ID 1d6b:0002
What I find out is that this worked properly in kernel 3.0 and stopped
working in 3.1. Has anybody found something similar with an i.MX27
based board?
Regards.
</pre>
javier Martin
2012-05-24T11:00:08
-
[PATCH 1/5] ARM: imx6q: add DT node for apbh-dma
http://comments.gmane.org/gmane.linux.ports.arm.kernel/169232
<pre>add DT node for apbh-dma.
Signed-off-by: Huang Shijie <b32955< at >freescale.com>
---
arch/arm/boot/dts/imx6q.dtsi | 5 +++++
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 8c90cba..cccac33 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
< at >< at > -87,6 +87,11 < at >< at >
interrupt-parent = <&intc>;
ranges;
+dma-apbh< at >00110000 {
+compatible = "fsl,imx6q-dma-apbh";
+reg = <0x00110000 0x2000>;
+};
+
timer< at >00a00600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x00a00600 0x20>;
</pre>
Huang Shijie
2012-05-24T10:50:55
-
[PATCH] ARM: mx28: add gpmi-nand dt support
http://comments.gmane.org/gmane.linux.ports.arm.kernel/169230
<pre>add gpmi-nand device tree support.
Also enable the gpmi support for mx28-evk board.
Signed-off-by: Huang Shijie <b32955< at >freescale.com>
---
arch/arm/boot/dts/imx28-evk.dts | 4 ++++
arch/arm/boot/dts/imx28.dtsi | 18 +++++++++---------
2 files changed, 13 insertions(+), 9 deletions(-)
diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
index ee520a5..5fff6c9 100644
--- a/arch/arm/boot/dts/imx28-evk.dts
+++ b/arch/arm/boot/dts/imx28-evk.dts
< at >< at > -22,6 +22,10 < at >< at >
apb< at >80000000 {
apbh< at >80000000 {
+gpmi-nand< at >8000c000 {
+status = "okay";
+};
+
ssp0: ssp< at >80010000 {
compatible = "fsl,imx28-mmc";
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 4634cb8..2358089 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
< at >< at > -68,15 +68,15 < at >< at >
status = "disabled";
};
-bch< at >8000a000 {
-reg = <0x8000a000 2000>;
-interrupts = <41>;
-status = "disabled";
-};
-
-gpmi< at >8000c000 {
-reg = <0x8000c000 2000>;
-interrupts = <42 88>;
+gpmi-nand< at >8000c000 {
+compatible = "fsl,imx28-gpmi-nand";
+#address-cells = <1>;
+#size-cells = <1>;
+reg = <0x8000c000 2000>, <0x8000a000 2000>;
+reg-names = "gpmi-nand", "bch";
+interrupts = <88>, <41>;
+interrupt-names = "gpmi-dma", "bch";
+fsl,gpmi-dma-channel = <4>;
status = "disabled";
};
</pre>
Huang Shijie
2012-05-24T10:45:38
-
[PATCH] Consolidate stack size information into THREAD_SIZE_ORDER
http://comments.gmane.org/gmane.linux.ports.arm.kernel/169181
<pre>This reduces the number of magic values in the code, as well as
makes it easier to experiment with larger or smaller stack sizes.
Signed-off-by: Tim Bird <tim.bird< at >am.sony.com>
PATCH FOLLOWS
---
arch/arm/include/asm/thread_info.h | 2 +-
arch/arm/kernel/entry-header.S | 8 ++++----
arch/arm/mm/proc-macros.S | 4 ++--
3 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h
index 0f04d84..5172c36 100644
--- a/arch/arm/include/asm/thread_info.h
+++ b/arch/arm/include/asm/thread_info.h
< at >< at > -16,7 +16,7 < at >< at >
#include <asm/fpstate.h>
#define THREAD_SIZE_ORDER1
-#define THREAD_SIZE8192
+#define THREAD_SIZE(4096 << THREAD_SIZE_ORDER)
#define THREAD_START_SP(THREAD_SIZE - 8)
#ifndef __ASSEMBLY__
diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S
index 9a8531e..f94216b 100644
--- a/arch/arm/kernel/entry-header.S
+++ b/arch/arm/kernel/entry-header.S
< at >< at > -109,8 +109,8 < at >< at >
.endm
.macroget_thread_info, rd
-mov\rd, sp, lsr #13
-mov\rd, \rd, lsl #13
+mov\rd, sp, lsr #12 + THREAD_SIZE_ORDER
+mov\rd, \rd, lsl #12 + THREAD_SIZE_ORDER
.endm
< at >
< at >< at > -150,8 +150,8 < at >< at >
.macroget_thread_info, rd
mov\rd, sp
-lsr\rd, \rd, #13
-mov\rd, \rd, lsl #13
+lsr\rd, \rd, #12 + THREAD_SIZE_ORDER
+mov\rd, \rd, lsl #12 + THREAD_SIZE_ORDER
.endm
< at >
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
index 2d8ff3a..7006c88 100644
--- a/arch/arm/mm/proc-macros.S
+++ b/arch/arm/mm/proc-macros.S
< at >< at > -30,8 +30,8 < at >< at >
* act_mm - get current->active_mm
*/
.macroact_mm, rd
-bic\rd, sp, #8128
-bic\rd, \rd, #63
+mov\rd, sp, lsr #12 + THREAD_SIZE_ORDER
+mov\rd, \rd, lsl #12 + THREAD_SIZE_ORDER
ldr\rd, [\rd, #TI_TASK]
ldr\rd, [\rd, #TSK_ACTIVE_MM]
.endm
</pre>
Tim Bird
2012-05-24T00:34:13
-
[PATCH] [ARM] Unconditional call to smp_cross_call on UP crashes
http://comments.gmane.org/gmane.linux.ports.arm.kernel/169168
<pre>omap2plus_defconfig builds with SMP & SMP_ON_UP set.
On beagle (which is UP) is_smp() returns false and we don't call
smp_init_cpus which in turn does not initialize smp_cross_call which
remains NULL.
When issuing a reboot we OOPS with a NULL dereference on stop smp_call.
Fixed by checking is_smp in smp_send_stop()
Restarting system.
Unable to handle kernel NULL pointer dereference at virtual address 00000000
pgd = dda50000
[00000000] *pgd=9e723831, *pte=00000000, *ppte=00000000
Internal error: Oops: 80000007 [#1] SMP ARM
Modules linked in:
CPU: 0 Not tainted (3.4.0-00001-gb15b046 #30)
PC is at 0x0
LR is at smp_send_stop+0x4c/0xe8
pc : [<00000000>] lr : [<c00188cc>] psr: 60000013
sp : de7b5e70 ip : 00000000 fp : 00000001
r10: 00000000 r9 : de7b4000 r8 : c07263d0
r7 : 00000000 r6 : c06e1294 r5 : 000f4240 r4 : de7b5e74
r3 : 00000000 r2 : 00000000 r1 : 00000006 r0 : de7b5e74
Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment user
Control: 10c5387d Table: 9da50019 DAC: 00000015
Process reboot (pid: 2229, stack limit = 0xde7b42f8)
Stack: (0xde7b5e70 to 0xde7b6000)
5e60: 00000000 00000000 00000000 01234567
5e80: de7b4000 c001475c 4321fedc c0052570 0000003e 00000000 c081db78 0000003e
5ea0: 00000001 00000002 00000002 c00891f0 00000002 dd5ba0ac 00000002 00000000
5ec0: dd5ba0ac de7b4000 c009eef4 de7b4000 c00f44dc de7b4000 c00f44dc 00000000
5ee0: c0c94d24 de7b4000 00000000 00000000 00000002 00000002 00000000 c00891f0
5f00: 00000002 00000000 00000000 c011286c 00000000 dd5ba060 60000013 00000000
5f20: dd688d8c 00000000 de7b4000 c06e20f8 dec14760 dec14750 de7b4000 c06e20f8
5f40: 00011f10 c01128a0 00000002 00000000 c011286c c00fa014 dd8c3180 de7b4000
5f60: c0013380 de508bc0 00000001 60000010 00000001 ef000000 00000001 c0089bfc
5f80: 00000000 00000001 00000004 00000058 00000000 00000001 00000004 00000058
5fa0: c0013428 c0013260 00000000 00000001 fee1dead 28121969 01234567 00000000
5fc0: 00000000 00000001 00000004 00000058 00000001 00000001 00000000 00000001
5fe0: b6e76200 beba4c90 00009210 b6e76218 60000010 fee1dead 00000000 00000000
[<c00188cc>] (smp_send_stop+0x4c/0xe8) from [<c001475c>] (machine_restart+0xc/0x54)
[<c001475c>] (machine_restart+0xc/0x54) from [<c0052570>] (sys_reboot+0x140/0x204)
[<c0052570>] (sys_reboot+0x140/0x204) from [<c0013260>] (ret_fast_syscall+0x0/0x3c)
Code: bad PC value
---[ end trace f5035e8726d1f51b ]---
Signed-off-by: Pantelis Antoniou <panto< at >antoniou-consulting.com>
---
arch/arm/kernel/smp.c | 4 ++++
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 8f46446..2a61335 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
< at >< at > -588,6 +588,10 < at >< at > void smp_send_stop(void)
unsigned long timeout;
struct cpumask mask;
+/* make sure we don't bother if not SMP */
+if (!is_smp())
+return;
+
cpumask_copy(&mask, cpu_online_mask);
cpumask_clear_cpu(smp_processor_id(), &mask);
smp_cross_call(&mask, IPI_CPU_STOP);
</pre>
Pantelis Antoniou
2012-05-24T19:40:51
-
perf_event_v7.c compilation failure in next-20120523
http://comments.gmane.org/gmane.linux.ports.arm.kernel/169157
<pre>Will,
In next-20120523, the following two commits of yours collided:
d33c88c ARM: 7315/1: perf: add support for the Cortex-A7 PMU
(adds new entry to perf_event_v7.c)
b3426c5 ARM: perf: remove arm_perf_pmu_ids global enumeration
(removes a field from entries in perf_event_v7.c)
This causes:
The following fixes the compilation error, although I put no thought
into whether it actually works at run-time:
</pre>
Stephen Warren
2012-05-23T17:00:06
-
[PATCH] ixp4xx: fix compilation by adding gpiolib support
http://comments.gmane.org/gmane.linux.ports.arm.kernel/169155
<pre>Once again, ixp4xx no longer even compiles. This patch fixes the issue
by converting over to gpiolib. This patch was first made by Imre and
posted by Marc, and I added in Russell's suggestion to empty the gpio
header file.
This fix should also go for 3.1, 3.2, 3.3, and 3.4.
Signed-off-by: Richard Cochran <richardcochran< at >gmail.com>
Cc: <stable< at >vger.kernel.org>
---
arch/arm/Kconfig | 2 +-
arch/arm/mach-ixp4xx/common.c | 48 +++++++++++++++++-
arch/arm/mach-ixp4xx/include/mach/gpio.h | 79 +-----------------------------
3 files changed, 48 insertions(+), 81 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 36586dba..7a8660a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
< at >< at > -556,7 +556,7 < at >< at > config ARCH_IXP4XX
select ARCH_HAS_DMA_SET_COHERENT_MASK
select CLKSRC_MMIO
select CPU_XSCALE
-select GENERIC_GPIO
+select ARCH_REQUIRE_GPIOLIB
select GENERIC_CLOCKEVENTS
select MIGHT_HAVE_PCI
select NEED_MACH_IO_H
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index ebbd7fc..a9f8094 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
< at >< at > -28,6 +28,7 < at >< at >
#include <linux/clockchips.h>
#include <linux/io.h>
#include <linux/export.h>
+#include <linux/gpio.h>
#include <mach/udc.h>
#include <mach/hardware.h>
< at >< at > -107,7 +108,7 < at >< at > static signed char irq2gpio[32] = {
7, 8, 9, 10, 11, 12, -1, -1,
};
-int gpio_to_irq(int gpio)
+static int ixp4xx_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
{
int irq;
< at >< at > -117,7 +118,6 < at >< at > int gpio_to_irq(int gpio)
}
return -EINVAL;
}
-EXPORT_SYMBOL(gpio_to_irq);
int irq_to_gpio(unsigned int irq)
{
< at >< at > -383,12 +383,56 < at >< at > static struct platform_device *ixp46x_devices[] __initdata = {
unsigned long ixp4xx_exp_bus_size;
EXPORT_SYMBOL(ixp4xx_exp_bus_size);
+static int ixp4xx_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
+{
+gpio_line_config(gpio, IXP4XX_GPIO_IN);
+
+return 0;
+}
+
+static int ixp4xx_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
+int level)
+{
+gpio_line_set(gpio, level);
+gpio_line_config(gpio, IXP4XX_GPIO_OUT);
+
+return 0;
+}
+
+static int ixp4xx_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
+{
+int value;
+
+gpio_line_get(gpio, &value);
+
+return value;
+}
+
+static void ixp4xx_gpio_set_value(struct gpio_chip *chip, unsigned gpio,
+ int value)
+{
+gpio_line_set(gpio, value);
+}
+
+static struct gpio_chip ixp4xx_gpio_chip = {
+.label= "IXP4XX_GPIO_CHIP",
+.direction_input= ixp4xx_gpio_direction_input,
+.direction_output= ixp4xx_gpio_direction_output,
+.get= ixp4xx_gpio_get_value,
+.set= ixp4xx_gpio_set_value,
+.to_irq= ixp4xx_gpio_to_irq,
+.base= 0,
+.ngpio= 16,
+};
+
void __init ixp4xx_sys_init(void)
{
ixp4xx_exp_bus_size = SZ_16M;
platform_add_devices(ixp4xx_devices, ARRAY_SIZE(ixp4xx_devices));
+gpiochip_add(&ixp4xx_gpio_chip);
+
if (cpu_is_ixp46x()) {
int region;
diff --git a/arch/arm/mach-ixp4xx/include/mach/gpio.h b/arch/arm/mach-ixp4xx/include/mach/gpio.h
index 83d6b4e..ef37f26 100644
--- a/arch/arm/mach-ixp4xx/include/mach/gpio.h
+++ b/arch/arm/mach-ixp4xx/include/mach/gpio.h
< at >< at > -1,79 +1,2 < at >< at >
-/*
- * arch/arm/mach-ixp4xx/include/mach/gpio.h
- *
- * IXP4XX GPIO wrappers for arch-neutral GPIO calls
- *
- * Written by Milan Svoboda <msvoboda< at >ra.rockwell.com>
- * Based on PXA implementation by Philipp Zabel <philipp.zabel< at >gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- */
-
-#ifndef __ASM_ARCH_IXP4XX_GPIO_H
-#define __ASM_ARCH_IXP4XX_GPIO_H
-
-#include <linux/kernel.h>
-#include <mach/hardware.h>
-
-#define __ARM_GPIOLIB_COMPLEX
-
-static inline int gpio_request(unsigned gpio, const char *label)
-{
-return 0;
-}
-
-static inline void gpio_free(unsigned gpio)
-{
-might_sleep();
-
-return;
-}
-
-static inline int gpio_direction_input(unsigned gpio)
-{
-gpio_line_config(gpio, IXP4XX_GPIO_IN);
-return 0;
-}
-
-static inline int gpio_direction_output(unsigned gpio, int level)
-{
-gpio_line_set(gpio, level);
-gpio_line_config(gpio, IXP4XX_GPIO_OUT);
-return 0;
-}
-
-static inline int gpio_get_value(unsigned gpio)
-{
-int value;
-
-gpio_line_get(gpio, &value);
-
-return value;
-}
-
-static inline void gpio_set_value(unsigned gpio, int value)
-{
-gpio_line_set(gpio, value);
-}
-
-#include <asm-generic/gpio.h>/* cansleep wrappers */
-
-extern int gpio_to_irq(int gpio);
-#define gpio_to_irq gpio_to_irq
-extern int irq_to_gpio(unsigned int irq);
-
-#endif
+/* empty */
</pre>
Richard Cochran
2012-05-23T16:19:51
-
[PATCHv5 1/2] drivers: input: keypad: Add device tree support
http://comments.gmane.org/gmane.linux.ports.arm.kernel/169148
<pre>Update the Documentation with omap4 keypad device tree
binding information.
Add device tree support for omap4 keypad driver.
Tested on omap4430 sdp.
Cc: Benoit Cousson <b-cousson< at >ti.com>
Cc: Rob Herring <rob.herring< at >calxeda.com>
Cc: Grant Likely <grant.likely< at >secretlab.ca>
Cc: Felipe Balbi <balbi< at >ti.com>
Cc: Dmitry Torokhov <dtor< at >mail.ru>
Cc: Randy Dunlap <rdunlap< at >xenotime.net>
Signed-off-by: Sourav Poddar <sourav.poddar< at >ti.com>
---
changes since v4:
- Developed it on top of dmitry's 'next' branch due to
dependency on generic "matrix_keypad_build_keymap" api
patches queued in that branch
- Adapted the driver to fill "keymap" in device tree
using "matrix_keypad_build_keymap" api defined in
drivers/input/matrix-keymap.c
.../devicetree/bindings/input/omap-keypad.txt | 31 ++++++
drivers/input/keyboard/omap4-keypad.c | 108 +++++++++++++++-----
2 files changed, 111 insertions(+), 28 deletions(-)
create mode 100644 Documentation/devicetree/bindings/input/omap-keypad.txt
diff --git a/Documentation/devicetree/bindings/input/omap-keypad.txt b/Documentation/devicetree/bindings/input/omap-keypad.txt
new file mode 100644
index 0000000..722425b
--- /dev/null
+++ b/Documentation/devicetree/bindings/input/omap-keypad.txt
< at >< at > -0,0 +1,31 < at >< at >
+* TI's Keypad Controller device tree bindings
+
+TI's Keypad controller is used to interface a SoC with a matrix-type
+keypad device. The keypad controller supports multiple row and column lines.
+A key can be placed at each intersection of a unique row and a unique column.
+The keypad controller can sense a key-press and key-release and report the
+event using a interrupt to the cpu.
+
+Required SoC Specific Properties:
+- compatible: should be one of the following
+ - "ti,omap4-keypad": For controllers compatible with omap4 keypad
+ controller.
+
+Required Board Specific Properties, in addition to those specified by
+the shared matrix-keyboard bindings:
+- keypad,num-rows: Number of row lines connected to the keypad
+ controller.
+
+- keypad,num-columns: Number of column lines connected to the
+ keypad controller.
+
+Optional Properties specific to linux:
+- linux,keypad-no-autorepeat: do no enable autorepeat feature.
+
+Example:
+ keypad< at >4ae1c000{
+ compatible = "ti,omap4-keypad";
+ keypad,num-rows = <2>;
+ keypad,num-columns = <8>;
+linux,keypad-no-autorepeat;
+};
diff --git a/drivers/input/keyboard/omap4-keypad.c b/drivers/input/keyboard/omap4-keypad.c
index aed5f69..d5a2d1a 100644
--- a/drivers/input/keyboard/omap4-keypad.c
+++ b/drivers/input/keyboard/omap4-keypad.c
< at >< at > -27,6 +27,7 < at >< at >
#include <linux/platform_device.h>
#include <linux/errno.h>
#include <linux/io.h>
+#include <linux/of.h>
#include <linux/input.h>
#include <linux/slab.h>
#include <linux/pm_runtime.h>
< at >< at > -75,6 +76,7 < at >< at > enum {
struct omap4_keypad {
struct input_dev *input;
+struct matrix_keymap_data *keymap_data;
void __iomem *base;
unsigned int irq;
< at >< at > -84,6 +86,7 < at >< at > struct omap4_keypad {
u32 reg_offset;
u32 irqreg_offset;
unsigned int row_shift;
+bool no_autorepeat;
unsigned char key_state[8];
unsigned short keymap[];
};
< at >< at > -208,25 +211,74 < at >< at > static void omap4_keypad_close(struct input_dev *input)
pm_runtime_put_sync(input->dev.parent);
}
+static struct omap4_keypad *omap_keypad_parse_dt(struct device *dev,
+uint32_t rows, uint32_t cols,
+struct input_dev *input_dev)
+{
+struct device_node *np = dev->of_node;
+struct platform_device *pdev = to_platform_device(dev);
+struct omap4_keypad *keypad_data = platform_get_drvdata(pdev);
+int error;
+
+error = matrix_keypad_build_keymap(NULL, "linux,keymap",
+rows, cols, keypad_data->keymap, input_dev);
+if (error) {
+dev_err(&pdev->dev, "failed to build keymap\n");
+input_free_device(input_dev);
+}
+
+if (of_get_property(np, "linux,input-no-autorepeat", NULL))
+keypad_data->no_autorepeat = true;
+
+return keypad_data;
+}
+
static int __devinit omap4_keypad_probe(struct platform_device *pdev)
{
+struct device *dev = &pdev->dev;
+struct device_node *np = dev->of_node;
const struct omap4_keypad_platform_data *pdata;
struct omap4_keypad *keypad_data;
struct input_dev *input_dev;
struct resource *res;
resource_size_t size;
-unsigned int row_shift, max_keys;
+unsigned int row_shift = 0, max_keys = 0;
+uint32_t num_rows = 0, num_cols = 0;
int rev;
int irq;
int error;
/* platform data */
pdata = pdev->dev.platform_data;
-if (!pdata) {
+if (np) {
+of_property_read_u32(np, "keypad,num-rows", &num_rows);
+of_property_read_u32(np, "keypad,num-columns", &num_cols);
+if (!num_rows || !num_cols) {
+dev_err(&pdev->dev, "number of keypad rows/columns not specified\n");
+return -EINVAL;
+}
+} else if (pdata) {
+num_rows = pdata->rows;
+num_cols = pdata->cols;
+} else {
dev_err(&pdev->dev, "no platform data defined\n");
return -EINVAL;
}
+row_shift = get_count_order(num_cols);
+max_keys = num_rows << row_shift;
+
+keypad_data = devm_kzalloc(dev, sizeof(struct omap4_keypad) +
+max_keys * sizeof(keypad_data->keymap[0]),
+GFP_KERNEL);
+
+if (!keypad_data) {
+dev_err(&pdev->dev, "keypad_data memory allocation failed\n");
+return -ENOMEM;
+}
+
+platform_set_drvdata(pdev, keypad_data);
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(&pdev->dev, "no base address specified\n");
< at >< at > -239,22 +291,6 < at >< at > static int __devinit omap4_keypad_probe(struct platform_device *pdev)
return -EINVAL;
}
-if (!pdata->keymap_data) {
-dev_err(&pdev->dev, "no keymap data defined\n");
-return -EINVAL;
-}
-
-row_shift = get_count_order(pdata->cols);
-max_keys = pdata->rows << row_shift;
-
-keypad_data = kzalloc(sizeof(struct omap4_keypad) +
-max_keys * sizeof(keypad_data->keymap[0]),
- GFP_KERNEL);
-if (!keypad_data) {
-dev_err(&pdev->dev, "keypad_data memory allocation failed\n");
-return -ENOMEM;
-}
-
size = resource_size(res);
res = request_mem_region(res->start, size, pdev->name);
< at >< at > -271,10 +307,10 < at >< at > static int __devinit omap4_keypad_probe(struct platform_device *pdev)
goto err_release_mem;
}
+keypad_data->rows = num_rows;
+keypad_data->cols = num_cols;
keypad_data->irq = irq;
keypad_data->row_shift = row_shift;
-keypad_data->rows = pdata->rows;
-keypad_data->cols = pdata->cols;
/*
* Enable clocks for the keypad module so that we can read
< at >< at > -322,15 +358,25 < at >< at > static int __devinit omap4_keypad_probe(struct platform_device *pdev)
input_dev->open = omap4_keypad_open;
input_dev->close = omap4_keypad_close;
-error = matrix_keypad_build_keymap(pdata->keymap_data, NULL,
- pdata->rows, pdata->cols,
- keypad_data->keymap, input_dev);
-if (error) {
-dev_err(&pdev->dev, "failed to build keymap\n");
-goto err_free_input;
+if (np) {
+keypad_data = omap_keypad_parse_dt(&pdev->dev,
+keypad_data->rows, keypad_data->cols,
+input_dev);
+} else {
+keypad_data->keymap_data =
+(struct matrix_keymap_data *)pdata->keymap_data;
+error = matrix_keypad_build_keymap(keypad_data->keymap_data,
+NULL, keypad_data->rows, keypad_data->cols,
+keypad_data->keymap, input_dev);
+if (error) {
+dev_err(&pdev->dev, "failed to build keymap\n");
+goto err_free_input;
+}
}
-__set_bit(EV_REP, input_dev->evbit);
+if (!keypad_data->no_autorepeat)
+__set_bit(EV_REP, input_dev->evbit);
+
input_set_capability(input_dev, EV_MSC, MSC_SCAN);
input_set_drvdata(input_dev, keypad_data);
< at >< at > -351,7 +397,6 < at >< at > static int __devinit omap4_keypad_probe(struct platform_device *pdev)
goto err_pm_disable;
}
-platform_set_drvdata(pdev, keypad_data);
return 0;
err_pm_disable:
< at >< at > -392,12 +437,19 < at >< at > static int __devexit omap4_keypad_remove(struct platform_device *pdev)
return 0;
}
+static const struct of_device_id omap_keypad_dt_match[] = {
+{ .compatible = "ti,omap4-keypad" },
+{},
+};
+MODULE_DEVICE_TABLE(of, omap_keypad_dt_match);
+
static struct platform_driver omap4_keypad_driver = {
.probe= omap4_keypad_probe,
.remove= __devexit_p(omap4_keypad_remove),
.driver= {
.name= "omap4-keypad",
.owner= THIS_MODULE,
+.of_match_table = of_match_ptr(omap_keypad_dt_match),
},
};
module_platform_driver(omap4_keypad_driver);
</pre>
Sourav Poddar
2012-05-23T13:55:49
-
ARM: ETH PHY Micrel: KSZ8051MNL Driver?
http://comments.gmane.org/gmane.linux.ports.arm.kernel/169129
<pre>Hi Everyone,
Do you know if this newer chip is compatible with older Micrel devices (supported at mainline)?
Did anyone try using it? results?
Please advise,
Shmuel Yitzhaki
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel< at >lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
</pre>
Shmuel Yitzhaki
2012-05-22T21:08:39
-
[PATCH v8 0/3] Add PMECC support for at91 nand flash driver
http://comments.gmane.org/gmane.linux.ports.arm.kernel/169118
<pre>Code is based on 3.4-rc2
Changes since v7,
add time out for PMECC status reading.
modify the oobfree[0].offset to 2.
fix coding style.
Changes since v6,
split into 3 patches.
remove of_flat_dt_is_compatible() function. use additional dt parameter "has-pmecc".
refine the error handling code.
refine original atmel_nand_init_params() function.
Changes since v5,
add has_pmecc field to replace cpu_has_pmecc() function. Use compatible check in when proble.
simplify the pmecc_get_ecc_bytes() function.
Changes since v4,
fix typo and checkpatch warnings.
fix according to JC's suggestion. replace cpu_is_xxx() with DT
modify dt binding atmel nand document to add pmecc support.
tested in sam9263 without break hw ecc.
add ecc.strength.
Josh Wu (3):
MTD: at91: extract hw ecc initialization to one function
MTD: add dt parameters for PMECC
MTD: atmel_nand: Update driver to support Programmable Multibit ECC controller
.../devicetree/bindings/mtd/atmel-nand.txt | 7 +
drivers/mtd/nand/atmel_nand.c | 885 ++++++++++++++++++--
drivers/mtd/nand/atmel_nand_ecc.h | 123 ++-
3 files changed, 946 insertions(+), 69 deletions(-)
</pre>
Josh Wu
2012-05-23T07:47:51
-
[PATCH V2 1/2] ARM: tegra: config: enable TPS65910 drivers
http://comments.gmane.org/gmane.linux.ports.arm.kernel/169114
<pre>Enable TPS65910 mfd, gpio and regulator drivers.
This is the PMIC module for Tegra30 based cardhu
platform.
Signed-off-by: Laxman Dewangan <ldewangan< at >nvidia.com>
---
No change from V1.
arch/arm/configs/tegra_defconfig | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index 1198dd6..26ad2b4 100644
--- a/arch/arm/configs/tegra_defconfig
+++ b/arch/arm/configs/tegra_defconfig
< at >< at > -106,16 +106,19 < at >< at > CONFIG_I2C=y
CONFIG_I2C_TEGRA=y
CONFIG_SPI=y
CONFIG_SPI_TEGRA=y
+CONFIG_GPIO_TPS65910=y
CONFIG_POWER_SUPPLY=y
CONFIG_BATTERY_SBS=y
CONFIG_SENSORS_LM90=y
CONFIG_MFD_TPS6586X=y
+CONFIG_MFD_TPS65910=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
CONFIG_REGULATOR_GPIO=y
CONFIG_REGULATOR_TPS62360=y
CONFIG_REGULATOR_TPS6586X=y
+CONFIG_REGULATOR_TPS65910=y
CONFIG_SOUND=y
CONFIG_SND=y
# CONFIG_SND_SUPPORT_OLD_API is not set
</pre>
Laxman Dewangan
2012-05-23T06:12:53
-
[PATCH] PINCTRL: SiRF: add CSR SiRFprimaII GPIO driver depending on pinmux APIs
http://comments.gmane.org/gmane.linux.ports.arm.kernel/168981
<pre>From: Barry Song <Baohua.Song< at >csr.com>
In SiRFprimaII, Each GPIO pin can be configured as input or output
independently. If a GPIO is configured as input, it can also be
enabled as an interrupt source (either edge or level triggered).
These pins must be either MUXed as GPIO or other function pads. So
this drivers depend on pinctrl_request_gpio() API pinctrl-sirf.c
implements.
Signed-off-by: Yuping Luo <yuping.luo< at >csr.com>
Signed-off-by: Barry Song <Baohua.Song< at >csr.com>
---
arch/arm/boot/dts/prima2-cb.dts | 1 +
arch/arm/mach-prima2/include/mach/gpio.h | 1 +
drivers/pinctrl/Makefile | 2 +-
drivers/pinctrl/gpio-sirf.c | 458 ++++++++++++++++++++++++++++++
4 files changed, 461 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/mach-prima2/include/mach/gpio.h
create mode 100644 drivers/pinctrl/gpio-sirf.c
diff --git a/arch/arm/boot/dts/prima2-cb.dts b/arch/arm/boot/dts/prima2-cb.dts
index 34ae3a6..4245306 100644
--- a/arch/arm/boot/dts/prima2-cb.dts
+++ b/arch/arm/boot/dts/prima2-cb.dts
< at >< at > -284,6 +284,7 < at >< at >
#interrupt-cells = <2>;
compatible = "sirf,prima2-gpio-pinmux";
reg = <0xb0120000 0x10000>;
+interrupts = <43 44 45 46 47>;
gpio-controller;
interrupt-controller;
};
diff --git a/arch/arm/mach-prima2/include/mach/gpio.h b/arch/arm/mach-prima2/include/mach/gpio.h
new file mode 100644
index 0000000..40a8c17
--- /dev/null
+++ b/arch/arm/mach-prima2/include/mach/gpio.h
< at >< at > -0,0 +1 < at >< at >
+/* empty */
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 515e32f..90b699b 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
< at >< at > -20,7 +20,7 < at >< at > obj-$(CONFIG_PINCTRL_IMX23)+= pinctrl-imx23.o
obj-$(CONFIG_PINCTRL_IMX28)+= pinctrl-imx28.o
obj-$(CONFIG_PINCTRL_PXA168)+= pinctrl-pxa168.o
obj-$(CONFIG_PINCTRL_PXA910)+= pinctrl-pxa910.o
-obj-$(CONFIG_PINCTRL_SIRF)+= pinctrl-sirf.o
+obj-$(CONFIG_PINCTRL_SIRF)+= pinctrl-sirf.o gpio-sirf.o
obj-$(CONFIG_PINCTRL_TEGRA)+= pinctrl-tegra.o
obj-$(CONFIG_PINCTRL_TEGRA20)+= pinctrl-tegra20.o
obj-$(CONFIG_PINCTRL_TEGRA30)+= pinctrl-tegra30.o
diff --git a/drivers/pinctrl/gpio-sirf.c b/drivers/pinctrl/gpio-sirf.c
new file mode 100644
index 0000000..3cc696d
--- /dev/null
+++ b/drivers/pinctrl/gpio-sirf.c
< at >< at > -0,0 +1,458 < at >< at >
+/*
+ * GPIO controller driver for CSR SiRFprimaII
+ *
+ * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_address.h>
+#include <linux/gpio.h>
+#include <linux/of_gpio.h>
+#include <linux/pinctrl/consumer.h>
+
+#define SIRFSOC_GPIO_IRQ_START (SIRFSOC_INTENAL_IRQ_END + 1)
+
+#define SIRFSOC_GPIO_NO_OF_BANKS 5
+#define SIRFSOC_GPIO_BANK_SIZE 32
+
+#define SIRFSOC_GPIO_CTRL(g, i)((g)*0x100 + (i)*4)
+#define SIRFSOC_GPIO_DSP_EN0(0x80)
+#define SIRFSOC_GPIO_PAD_EN(g)((g)*0x100 + 0x84)
+#define SIRFSOC_GPIO_INT_STATUS(g)((g)*0x100 + 0x8C)
+
+#define SIRFSOC_GPIO_CTL_INTR_LOW_MASK0x1
+#define SIRFSOC_GPIO_CTL_INTR_HIGH_MASK0x2
+#define SIRFSOC_GPIO_CTL_INTR_TYPE_MASK0x4
+#define SIRFSOC_GPIO_CTL_INTR_EN_MASK0x8
+#define SIRFSOC_GPIO_CTL_INTR_STS_MASK0x10
+#define SIRFSOC_GPIO_CTL_OUT_EN_MASK0x20
+#define SIRFSOC_GPIO_CTL_DATAOUT_MASK0x40
+#define SIRFSOC_GPIO_CTL_DATAIN_MASK0x80
+#define SIRFSOC_GPIO_CTL_PULL_MASK0x100
+#define SIRFSOC_GPIO_CTL_PULL_HIGH0x200
+#define SIRFSOC_GPIO_CTL_DSP_INT0x400
+
+#define SIRFSOC_GPIO_NUM(bank, index)(((bank)*(32)) + (index))
+
+struct sirfsoc_gpio_bank {
+struct of_mm_gpio_chip chip;
+int id;
+int irq;
+spinlock_t lock;
+};
+
+static struct sirfsoc_gpio_bank sgpio_bank[SIRFSOC_GPIO_NO_OF_BANKS];
+
+static DEFINE_SPINLOCK(sgpio_lock);
+
+static inline struct sirfsoc_gpio_bank *sirfsoc_irq_to_bank(unsigned int irq)
+{
+return &sgpio_bank[(irq - SIRFSOC_GPIO_IRQ_START) / SIRFSOC_GPIO_BANK_SIZE];
+}
+
+static inline int sirfsoc_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+return SIRFSOC_GPIO_IRQ_START + (chip->base + offset);
+}
+
+static inline int sirfsoc_irq_to_offset(unsigned int irq)
+{
+return (irq - SIRFSOC_GPIO_IRQ_START) % SIRFSOC_GPIO_BANK_SIZE;
+}
+
+static inline int sirfsoc_gpio_to_offset(unsigned int gpio)
+{
+return gpio % SIRFSOC_GPIO_BANK_SIZE;
+}
+
+static inline struct sirfsoc_gpio_bank *sirfsoc_irqchip_to_bank(struct gpio_chip *chip)
+{
+return container_of(to_of_mm_gpio_chip(chip), struct sirfsoc_gpio_bank, chip);
+}
+
+static void sirfsoc_gpio_irq_ack(struct irq_data *d)
+{
+struct sirfsoc_gpio_bank *bank = sirfsoc_irq_to_bank(d->irq);
+int idx = sirfsoc_irq_to_offset(d->irq);
+u32 status, offset;
+unsigned long flags;
+
+offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
+
+spin_lock_irqsave(&sgpio_lock, flags);
+
+status = readl(bank->chip.regs + offset);
+
+writel(status, bank->chip.regs + offset);
+
+spin_unlock_irqrestore(&sgpio_lock, flags);
+}
+
+static void __sirfsoc_gpio_irq_mask(unsigned int irq)
+{
+struct sirfsoc_gpio_bank *bank = sirfsoc_irq_to_bank(irq);
+int idx = sirfsoc_irq_to_offset(irq);
+u32 status, offset;
+unsigned long flags;
+
+offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
+
+spin_lock_irqsave(&sgpio_lock, flags);
+
+status = readl(bank->chip.regs + offset);
+status &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK;
+status &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
+writel(status, bank->chip.regs + offset);
+
+spin_unlock_irqrestore(&sgpio_lock, flags);
+}
+
+static void sirfsoc_gpio_irq_mask(struct irq_data *d)
+{
+__sirfsoc_gpio_irq_mask(d->irq);
+}
+
+static void sirfsoc_gpio_irq_unmask(struct irq_data *d)
+{
+struct sirfsoc_gpio_bank *bank = sirfsoc_irq_to_bank(d->irq);
+int idx = sirfsoc_irq_to_offset(d->irq);
+u32 status, offset;
+unsigned long flags;
+
+offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
+
+spin_lock_irqsave(&sgpio_lock, flags);
+
+status = readl(bank->chip.regs + offset);
+status &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
+status |= SIRFSOC_GPIO_CTL_INTR_EN_MASK;
+writel(status, bank->chip.regs + offset);
+
+spin_unlock_irqrestore(&sgpio_lock, flags);
+}
+
+static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type)
+{
+struct sirfsoc_gpio_bank *bank = sirfsoc_irq_to_bank(d->irq);
+int idx = sirfsoc_irq_to_offset(d->irq);
+u32 status, offset;
+unsigned long flags;
+
+offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
+
+spin_lock_irqsave(&sgpio_lock, flags);
+
+status = readl(bank->chip.regs + offset);
+status &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
+
+switch (type) {
+case IRQ_TYPE_NONE:
+break;
+case IRQ_TYPE_EDGE_RISING:
+status |= (SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
+status &= ~SIRFSOC_GPIO_CTL_INTR_LOW_MASK;
+break;
+case IRQ_TYPE_EDGE_FALLING:
+status &= ~SIRFSOC_GPIO_CTL_INTR_HIGH_MASK;
+status |= (SIRFSOC_GPIO_CTL_INTR_LOW_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
+break;
+case IRQ_TYPE_EDGE_BOTH:
+status |=
+(SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_LOW_MASK |
+ SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
+break;
+case IRQ_TYPE_LEVEL_LOW:
+status &= ~(SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
+status |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK;
+break;
+case IRQ_TYPE_LEVEL_HIGH:
+status |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK;
+status &= ~(SIRFSOC_GPIO_CTL_INTR_LOW_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
+break;
+}
+
+writel(status, bank->chip.regs + offset);
+
+spin_unlock_irqrestore(&sgpio_lock, flags);
+
+return 0;
+}
+
+static struct irq_chip sirfsoc_irq_chip = {
+.name = "SiRF SoC GPIO IRQ",
+.irq_ack = sirfsoc_gpio_irq_ack,
+.irq_mask = sirfsoc_gpio_irq_mask,
+.irq_unmask = sirfsoc_gpio_irq_unmask,
+.irq_set_type = sirfsoc_gpio_irq_type,
+};
+
+static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc)
+{
+struct sirfsoc_gpio_bank *bank = NULL;
+u32 status, ctrl;
+int i, idx = 0;
+
+for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
+if (sgpio_bank[i].irq == irq) {
+bank = &sgpio_bank[i];
+break;
+}
+}
+
+status = readl(bank->chip.regs + SIRFSOC_GPIO_INT_STATUS(bank->id));
+if (!status) {
+printk(KERN_WARNING
+"%s: gpio id %d status %#x no interrupt is flaged\n",
+__func__, bank->id, status);
+handle_bad_irq(irq, desc);
+return;
+}
+
+while (status) {
+ctrl = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, idx));
+
+/*
+ * Here we must check whether the corresponding GPIO's interrupt
+ * has been enabled, otherwise just skip it
+ */
+if ((status & 0x1) && (ctrl & SIRFSOC_GPIO_CTL_INTR_EN_MASK)) {
+pr_debug("%s: gpio id %d idx %d happens\n",
+__func__, bank->id, idx);
+irq =
+(SIRFSOC_GPIO_IRQ_START +
+ (bank->id * SIRFSOC_GPIO_BANK_SIZE)) + idx;
+generic_handle_irq(irq);
+}
+
+idx++;
+status = status >> 1;
+}
+}
+
+static inline void sirfsoc_gpio_set_input(struct sirfsoc_gpio_bank *bank, unsigned ctrl_offset)
+{
+u32 status;
+unsigned long flags;
+
+spin_lock_irqsave(&bank->lock, flags);
+
+status = readl(bank->chip.regs + ctrl_offset);
+status &= ~SIRFSOC_GPIO_CTL_OUT_EN_MASK;
+writel(status, bank->chip.regs + ctrl_offset);
+
+spin_unlock_irqrestore(&bank->lock, flags);
+}
+
+static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset)
+{
+struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
+unsigned long flags;
+
+if (pinctrl_request_gpio(chip->base + offset))
+return -ENODEV;
+
+spin_lock_irqsave(&bank->lock, flags);
+
+/*
+ * default status:
+ * set direction as input and mask irq
+ */
+sirfsoc_gpio_set_input(bank, SIRFSOC_GPIO_CTRL(bank->id, offset));
+__sirfsoc_gpio_irq_mask(sirfsoc_gpio_to_irq(chip, offset));
+
+spin_unlock_irqrestore(&bank->lock, flags);
+
+return 0;
+}
+
+static void sirfsoc_gpio_free(struct gpio_chip *chip, unsigned offset)
+{
+struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
+unsigned long flags;
+
+spin_lock_irqsave(&bank->lock, flags);
+
+__sirfsoc_gpio_irq_mask(sirfsoc_gpio_to_irq(chip, offset));
+sirfsoc_gpio_set_input(bank, SIRFSOC_GPIO_CTRL(bank->id, offset));
+
+spin_unlock_irqrestore(&bank->lock, flags);
+
+pinctrl_free_gpio(chip->base + offset);
+}
+
+static int sirfsoc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
+{
+struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
+int idx = sirfsoc_gpio_to_offset(gpio);
+unsigned long flags;
+unsigned offset;
+
+offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
+
+spin_lock_irqsave(&bank->lock, flags);
+
+sirfsoc_gpio_set_input(bank, offset);
+
+spin_unlock_irqrestore(&bank->lock, flags);
+
+return 0;
+}
+
+static inline void sirfsoc_gpio_set_output(struct sirfsoc_gpio_bank *bank, unsigned offset,
+int value)
+{
+u32 status;
+unsigned long flags;
+
+spin_lock_irqsave(&bank->lock, flags);
+
+status = readl(bank->chip.regs + offset);
+if (value)
+status |= SIRFSOC_GPIO_CTL_DATAOUT_MASK;
+else
+status &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK;
+
+status &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK;
+status |= SIRFSOC_GPIO_CTL_OUT_EN_MASK;
+writel(status, bank->chip.regs + offset);
+
+spin_unlock_irqrestore(&bank->lock, flags);
+}
+
+static int sirfsoc_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
+{
+struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
+int idx = sirfsoc_gpio_to_offset(gpio);
+u32 offset;
+unsigned long flags;
+
+offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
+
+spin_lock_irqsave(&sgpio_lock, flags);
+
+sirfsoc_gpio_set_output(bank, offset, value);
+
+spin_unlock_irqrestore(&sgpio_lock, flags);
+
+return 0;
+}
+
+static int sirfsoc_gpio_get_value(struct gpio_chip *chip, unsigned offset)
+{
+struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
+u32 status;
+unsigned long flags;
+
+spin_lock_irqsave(&bank->lock, flags);
+
+status = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
+
+spin_unlock_irqrestore(&bank->lock, flags);
+
+return !!(status & SIRFSOC_GPIO_CTL_DATAIN_MASK);
+}
+
+static void sirfsoc_gpio_set_value(struct gpio_chip *chip, unsigned offset,
+int value)
+{
+struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
+u32 status;
+unsigned long flags;
+
+spin_lock_irqsave(&bank->lock, flags);
+
+status = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
+if (value)
+status |= SIRFSOC_GPIO_CTL_DATAOUT_MASK;
+else
+status &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK;
+writel(status, bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
+
+spin_unlock_irqrestore(&bank->lock, flags);
+}
+
+static int __devinit sirfsoc_gpio_probe(struct device_node *np)
+{
+int i, err = 0;
+struct sirfsoc_gpio_bank *bank;
+void *regs;
+struct platform_device *pdev;
+
+pdev = of_find_device_by_node(np);
+if (!pdev)
+return -ENODEV;
+
+regs = of_iomap(np, 0);
+if (!regs)
+return -ENOMEM;
+
+for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
+bank = &sgpio_bank[i];
+spin_lock_init(&bank->lock);
+bank->chip.gc.request = sirfsoc_gpio_request;
+bank->chip.gc.free = sirfsoc_gpio_free;
+bank->chip.gc.direction_input = sirfsoc_gpio_direction_input;
+bank->chip.gc.get = sirfsoc_gpio_get_value;
+bank->chip.gc.direction_output = sirfsoc_gpio_direction_output;
+bank->chip.gc.set = sirfsoc_gpio_set_value;
+bank->chip.gc.to_irq = sirfsoc_gpio_to_irq;
+bank->chip.gc.base = i * SIRFSOC_GPIO_BANK_SIZE;
+bank->chip.gc.ngpio = SIRFSOC_GPIO_BANK_SIZE;
+bank->chip.gc.label = kstrdup(np->full_name, GFP_KERNEL);
+bank->chip.gc.of_node = np;
+bank->chip.regs = regs;
+bank->id = i;
+bank->irq = platform_get_irq(pdev, i);
+if (bank->irq < 0) {
+err = bank->irq;
+goto out;
+}
+
+/* Call the OF gpio helper to setup and register the GPIO device */
+err = gpiochip_add(&bank->chip.gc);
+if (err) {
+pr_err("%s: error in probe function with status %d\n",
+np->full_name, err);
+goto out;
+}
+
+irq_set_chained_handler(bank->irq, sirfsoc_gpio_handle_irq);
+irq_set_chip(bank->irq, &sirfsoc_irq_chip);
+irq_set_handler(bank->irq, handle_level_irq);
+set_irq_flags(bank->irq, IRQF_VALID | IRQF_PROBE);
+}
+
+out:
+iounmap(regs);
+return err;
+}
+
+static const struct of_device_id sgpio_of_match[] __devinitconst = {
+{.compatible = "sirf,prima2-gpio-pinmux", },
+{},
+};
+
+static int __init sirfsoc_gpio_init(void)
+{
+
+struct device_node *np;
+
+np = of_find_matching_node(NULL, sgpio_of_match);
+
+if (!np)
+return -ENODEV;
+
+return sirfsoc_gpio_probe(np);
+}
+subsys_initcall(sirfsoc_gpio_init);
+
+MODULE_DESCRIPTION("SiRFSoC GPIO driver");
+MODULE_AUTHOR("Yuping Luo <yuping.luo< at >csr.com>, Barry Song <baohua.song< at >csr.com>");
+MODULE_LICENSE("GPL v2");
</pre>
Barry Song
2012-05-22T07:14:05
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