gmane.linux.kernel.pci

[PATCH v7 00/10] PCI, x86: update MMCFG information when hot-plugging PCI host bridges

Jiang Liu — 2012-05-26T09:53:53

This patchset enhance pci_root driver to update MMCFG information when
hot-plugging PCI root bridges. It applies to 
git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git pci/next-3.5

-v2: split into smaller patches and skip updating MMCFG information when
     MMCFG is disabled
-v3: add mmconf_added to simply free path, also make pci_mmconfig_insert()
     to process extra exist case --- By Yinghai
-v4: tune arch_acpi_pci_root_add() to handle a corner case raised by Kenji
-v5: address review comments from Bjorn and Taku, also better handle corner
     cases in arch_acpi_pci_root_add()
-v6: get rid of arch_acpi_pci_root_xxx() by using existing hooks
     add MCFG information for host bridges on demand
     more corner cases clear up
     correctly handle condition compilation
     fix section mismatch issues
     fix a issue reported by Taku about a BIOS bug
-v7: unify log messages
     remove redundant host bridge resource related log messages
     fix a issue reported by Taku which breaks pnp resource allocation

Jiang Liu (10):
  PCI, x86: split out pci_mmcfg_check_reserved() for code reuse
  PCI, x86: split out pci_mmconfig_alloc() for code reuse
  PCI, x86: use RCU list to protect mmconfig list
  PCI, x86: introduce pci_mmcfg_arch_map()/pci_mmcfg_arch_unmap()
  PCI, x86: introduce pci_mmconfig_insert()/delete() for PCI root
    bridge hotplug
  PCI, ACPI: provide MCFG address for PCI host bridges
  PCI, x86: update MMCFG information when hot-plugging PCI host bridges
  PCI, x86: add MMCFG information on demand
  PCI, x86: simplify pci_mmcfg_late_insert_resources()
  PCI, x86: get rid of redundant log messages

 arch/x86/include/asm/pci_x86.h |   12 ++
 arch/x86/pci/acpi.c            |   76 ++++++++-
 arch/x86/pci/legacy.c          |    1 +
 arch/x86/pci/mmconfig-shared.c |  364 +++++++++++++++++++++++++++++-----------
 arch/x86/pci/mmconfig_32.c     |   30 +++-
 arch/x86/pci/mmconfig_64.c     |   37 ++++-
 drivers/acpi/pci_root.c        |   12 ++
 drivers/pci/pci-acpi.c         |   34 ++++
 include/acpi/acnames.h         |    1 +
 include/acpi/acpi_bus.h        |    3 +
 include/linux/pci-acpi.h       |    5 +
 11 files changed, 465 insertions(+), 110 deletions(-)

warn_slowpath_common in drivers/pci/search.c:44 on linux-3.4.0

Antonio Quartulli — 2012-05-26T08:25:52

Hello,

I'm getting this warning with linux-3.4.0. My laptop is a DELL E5420.
Please tell me if you need further testing/debug.

Cheers,

[    1.054279] WARNING: at drivers/pci/search.c:44 pci_find_upstream_pcie_bridge+0x5e/0x70()
[    1.054385] Hardware name: Latitude E5420
[    1.054457] Modules linked in:
[    1.054568] Pid: 1, comm: swapper/0 Not tainted 3.4.0ordex+ #3
[    1.054643] Call Trace:
[    1.054716]  [<ffffffff81033d4a>] warn_slowpath_common+0x7a/0xb0
[    1.054793]  [<ffffffff81033d95>] warn_slowpath_null+0x15/0x20
[    1.054869]  [<ffffffff8123899e>] pci_find_upstream_pcie_bridge+0x5e/0x70
[    1.054949]  [<ffffffff813babe7>] intel_iommu_device_group+0x77/0x100
[    1.055027]  [<ffffffff813b52d5>] add_iommu_group+0x35/0x60
[    1.055113]  [<ffffffff813b52a0>] ? bus_set_iommu+0x50/0x50
[    1.055191]  [<ffffffff8132c586>] bus_for_each_dev+0x56/0x90
[    1.055267]  [<ffffffff813b528b>] bus_set_iommu+0x3b/0x50
[    1.055344]  [<ffffffff818c4920>] intel_iommu_init+0xab0/0xb3f
[    1.055421]  [<ffffffff81120b26>] ? sys_mkdirat+0x76/0xd0
[    1.055499]  [<ffffffff8189b0db>] ? memblock_find_dma_reserve+0x13d/0x13d
[    1.055578]  [<ffffffff8189b0ee>] pci_iommu_init+0x13/0x3e
[    1.055655]  [<ffffffff810001ca>] do_one_initcall+0x3a/0x170
[    1.055732]  [<ffffffff81897c35>] kernel_init+0x148/0x1cc
[    1.055807]  [<ffffffff81897588>] ? do_early_param+0x86/0x86
[    1.055884]  [<ffffffff814fc914>] kernel_thread_helper+0x4/0x10
[    1.055963]  [<ffffffff8105de60>] ? finish_task_switch+0x80/0x110
[    1.056040]  [<ffffffff814fafdd>] ? retint_restore_args+0xe/0xe
[    1.056126]  [<ffffffff81897aed>] ? start_kernel+0x30b/0x30b
[    1.056203]  [<ffffffff814fc910>] ? gs_change+0xb/0xb

(unknown)

robothroli company — 2012-05-25T13:45:54

 i am robothroli, Purchase manager from roli Merchant Ltd. We are
Import/export Company based in taiwan. We are interested in purchasing
your product and I would like to make an inquiry. Please inform me on:

Sample availability and price
Minimum order quantity
FOB Prices

Sincerely
Purchase Manager
robothroli

PCI: cardbus bridge

Zhi Yong Wu — 2012-05-24T08:26:14

HI, guys

Does anyone let me know what cardbus bridge is used for? What is the
difference between it and comon pci bridge?

By the way, someone usually mentioned pci host bridge, pci root
bridge. What the differences among them are?

Any comments are appreciated, thanks

[PATCH v3 0/2] archdata init in device_add() notifier

Bjorn Helgaas — 2012-05-23T22:36:55

Here's what I put in my "for-3.6" branch for now.  We can still change
it, so let me know if you see any problems.

I reworked the changelogs, changed the notification function name per
Jesse, folded the one-line pcibios_setup_bus_notifier() into the only
caller (on microblaze), and changed it from __devinit to __init (on
powerpc) since it now has nothing to do with hotplug.

Thank you very much for doing this work, Matsumoto-san.  I hope to
eventually get rid of pcibios_fixup_bus() altogether, and this is a
significant step in that direction.

Bjorn
---

Hiroo Matsumoto (2):
      powerpc/PCI: move DMA & IRQ init to device_add() notification path
      microblaze/PCI: move DMA & IRQ init to device_add() notification path


 arch/microblaze/include/asm/pci.h          |    1 
 arch/microblaze/pci/pci-common.c           |   62 +++++++++++---------
 arch/powerpc/include/asm/pci.h             |    2 -
 arch/powerpc/kernel/pci-common.c           |   87 ++++++++++++++--------------
 arch/powerpc/kernel/pci_32.c               |    2 +
 arch/powerpc/kernel/pci_64.c               |    2 +
 arch/powerpc/kernel/pci_of_scan.c          |    1 
 arch/powerpc/platforms/pseries/pci_dlpar.c |    1 
 drivers/pci/pci.c                          |    5 --
 drivers/pcmcia/cardbus.c                   |    3 -
 include/linux/pci.h                        |    3 -
 11 files changed, 83 insertions(+), 86 deletions(-)

[PATCH] dca: check against empty dca_domains list before unregisterprovider

Maciej Sosnowski — 2012-05-23T15:27:07

When providers get blocked unregister_dca_providers() is called ending up
with dca_providers and dca_domain lists emptied. Dca should be prevented from
trying to unregister any provider if dca_domain list is found empty.

Reported-by: Jiang Liu <jiang.liu< at >huawei.com>
Tested-by: Gaohuai Han <hangaohuai< at >huawei.com>
Signed-off-by: Maciej Sosnowski <maciej.sosnowski< at >intel.com>
---

 drivers/dca/dca-core.c |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/drivers/dca/dca-core.c b/drivers/dca/dca-core.c
index bc6f5fa..819dfda 100644
--- a/drivers/dca/dca-core.c
+++ b/drivers/dca/dca-core.c
< at >< at > -420,6 +420,11 < at >< at > void unregister_dca_provider(struct dca_
 
 raw_spin_lock_irqsave(&dca_lock, flags);
 
+if (list_empty(&dca_domains)) {
+raw_spin_unlock_irqrestore(&dca_lock, flags);
+return;
+}
+
 list_del(&dca->node);
 
 pci_rc = dca_pci_rc_from_dev(dev);

[PATCH 00/11] PCI: resource allocation related

Yinghai Lu — 2012-05-23T06:34:26

From: Yinghai Lu <ying6hai< at >kernel.org>

This patchset will try to make allocation to find suitable assignement.
1. will try to assign 64 bit resource above 4g at first.
2. will find space that is matched with needed size
3. will put resource in right location to leave more big alignment with left blank resource
4. will try option rom BAR as optional resources.

Could be found:
git://git.kernel.org/pub/scm/linux/kernel/git/yinghai/linux-yinghai.git for-pci-res-alloc

and it is based on pci for-3.6 branch.

Thanks

Yinghai Lu

Yinghai Lu (11):
  PCI: Should add children device res to fail list
  PCI: Try to allocate mem64 above 4G at first
  intel-gtt: Read 64bit for gmar_bus_addr
  PCI: Make sure assign same align with large size resource at first
  resources: Split out __allocate_resource()
  resource: make find_resource could return just fit resource
  PCI: Don't allocate small resource in big empty space.
  resource: only return range with needed align
  PCI: Add is_pci_iov_resource_idx()
  PCI: Sort unassigned resources with correct alignment
  PCI: Treat ROM resource as optional during assigning.

 drivers/char/agp/intel-gtt.c |   14 ++++--
 drivers/pci/bus.c            |   38 +++++++++++---
 drivers/pci/setup-bus.c      |   78 ++++++++++++++++++-----------
 drivers/pci/setup-res.c      |   28 +++++++----
 include/linux/ioport.h       |    8 +++
 include/linux/pci.h          |   23 ++++++++
 kernel/resource.c            |  114 ++++++++++++++++++++++++++++++++++++++---
 7 files changed, 243 insertions(+), 60 deletions(-)

[PATCH v6 0/2] PCI: acpiphp: remove multifunction devices

Bjorn Helgaas — 2012-05-23T04:35:01

Here's my proposal for fixing this problem.

I split out the pci_dev_put() for function 0 because it looks to me
like that is actually a separate issue -- it looks like we leaked
that reference even for single-function devices.

I restructured the iteration over bus->devices to make it read a bit
more naturally, and also to remove it from inside the slot->funcs
loop.  It didn't make sense to me to have a nested loop there.

The cleanup_p2p_bridge() stuff is mostly just fiddling with notify
handlers and other ACPI-specific stuff.  I don't think there's
actually a dependency there on the PCI device removal, so I think
it's safe to do that separately.

Does this make sense to you?  If so, can you test it and make sure
it actually works?

Thanks,
  Bjorn

---

Amos Kong (2):
      PCI: acpiphp: fix function 0 leak when disabling a slot
      PCI: acpiphp: remove all functions in slot, even without ACPI _EJx


 drivers/pci/hotplug/acpiphp_glue.c |   40 +++++++++++++++++++++++++++---------
 1 files changed, 30 insertions(+), 10 deletions(-)

[PATCH v6 0/9] PCI, x86: update MMCFG information when hot-plugging PCI host bridges

Jiang Liu — 2012-05-23T03:50:17

From: Jiang Liu <liuj97< at >gmail.com>

From: Jiang Liu <jiang.liu< at >huawei.com>

This patchset enhance pci_root driver to update MMCFG information when
hot-plugging PCI root bridges. It applies to 
git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git pci/next-3.5

-v2: split into smaller patches and skip updating MMCFG information when
     MMCFG is disabled
-v3: add mmconf_added to simply free path, also make pci_mmconfig_insert()
     to process extra exist case --- By Yinghai
-v4: tune arch_acpi_pci_root_add() to handle a corner case raised by Kenji
-v5: address review comments from Bjorn and Taku, also better handle corner
     cases in arch_acpi_pci_root_add()
-v6: get rid of arch_acpi_pci_root_xxx() by using existing hooks
     add MCFG information for host bridges on demand
     more corner cases clear up
     correctly handle condition compilation
     fix section mismatch issues
     fix a issue reported by Taku about a BIOS bug

The first 4 patches in series is the same with v5.

On a test platform with four SandyBridge processors, MMCFG resources from
/proc/iomem are as below.
With original implementation:
bf000000-cfffffff : reserved
  c0000000-cfffffff : PCI MMCONFIG 0000 [bus 00-ff]

With patch set applied:
bf000000-cfffffff : reserved
  c0000000-c3efffff : PCI MMCONFIG 0000 [bus 00-3e]
  c3f00000-c3ffffff : PCI MMCONFIG 0000 [bus 3f-3f]
  c4000000-c7efffff : PCI MMCONFIG 0000 [bus 40-7e]
  c7f00000-c7ffffff : PCI MMCONFIG 0000 [bus 7f-7f]
  c8000000-cbefffff : PCI MMCONFIG 0000 [bus 80-be]
  cbf00000-cbffffff : PCI MMCONFIG 0000 [bus bf-bf]
  cc000000-cfefffff : PCI MMCONFIG 0000 [bus c0-fe]
  cff00000-cfffffff : PCI MMCONFIG 0000 [bus ff-ff]

After removing a host bridge:
bf000000-cfffffff : reserved
  c0000000-c3efffff : PCI MMCONFIG 0000 [bus 00-3e]
  c3f00000-c3ffffff : PCI MMCONFIG 0000 [bus 3f-3f]
  c4000000-c7efffff : PCI MMCONFIG 0000 [bus 40-7e]
  c7f00000-c7ffffff : PCI MMCONFIG 0000 [bus 7f-7f]
  c8000000-cbefffff : PCI MMCONFIG 0000 [bus 80-be]
  cbf00000-cbffffff : PCI MMCONFIG 0000 [bus bf-bf]
  cc000000-cfefffff : PCI MMCONFIG 0000 [bus c0-fe]
  cff00000-cfffffff : PCI MMCONFIG 0000 [bus ff-ff]

After adding the host bridge back
bf000000-cfffffff : reserved
  c0000000-c3efffff : PCI MMCONFIG 0000 [bus 00-3e]
  c3f00000-c3ffffff : PCI MMCONFIG 0000 [bus 3f-3f]
  c4000000-c7efffff : PCI MMCONFIG 0000 [bus 40-7e]
  c7f00000-c7ffffff : PCI MMCONFIG 0000 [bus 7f-7f]
  c8000000-cbefffff : PCI MMCONFIG 0000 [bus 80-be]
  cbf00000-cbffffff : PCI MMCONFIG 0000 [bus bf-bf]
  cc000000-cfefffff : PCI MMCONFIG 0000 [bus c0-fe]
  cff00000-cfffffff : PCI MMCONFIG 0000 [bus ff-ff]

Jiang Liu (9):
  PCI, x86: split out pci_mmcfg_check_reserved() for code reuse
  PCI, x86: split out pci_mmconfig_alloc() for code reuse
  PCI, x86: use RCU list to protect mmconfig list
  PCI, x86: introduce pci_mmcfg_arch_map()/pci_mmcfg_arch_unmap()
  PCI, x86: introduce pci_mmconfig_insert()/delete() for PCI root
    bridge hotplug
  PCI, ACPI: provide MCFG address for PCI host bridges
  PCI, x86: update MMCFG information when hot-plugging PCI host bridges
  PCI, x86: add MMCFG information on demand
  PCI, x86: simplify pci_mmcfg_late_insert_resources()

 arch/x86/include/asm/pci_x86.h |   11 ++
 arch/x86/pci/acpi.c            |   71 ++++++++++
 arch/x86/pci/legacy.c          |    1 +
 arch/x86/pci/mmconfig-shared.c |  280 ++++++++++++++++++++++++++++++----------
 arch/x86/pci/mmconfig_32.c     |   30 ++++-
 arch/x86/pci/mmconfig_64.c     |   37 +++++-
 drivers/acpi/pci_root.c        |   12 ++
 drivers/pci/pci-acpi.c         |   34 +++++
 include/acpi/acnames.h         |    1 +
 include/acpi/acpi_bus.h        |    3 +
 include/linux/pci-acpi.h       |    5 +
 11 files changed, 412 insertions(+), 73 deletions(-)

[PATCH v2 2/2] microblaze/PCI: Add pcibios_device_change_notifier for microblaze

Hiroo Matsumoto — 2012-05-23T02:34:03

pcibios_setup_bus_devices which sets DMA and IRQs of PCI device is called
only when boot, so DMA and IRQs of PCI device will not set when hotplug.
This patch adds pcibios_device_change_notifier which sets DMA and IRQs of
PCI device when PCI device adds, so DMA and IRQs of PCI device will be set
when boot and hotplug.

Signed-off-by: Hiroo MATSUMOTO <matsumoto.hiroo< at >jp.fujitsu.com>
---
 arch/microblaze/include/asm/pci.h |    2 +-
 arch/microblaze/pci/pci-common.c  |   67 +++++++++++++++++++++---------------
 2 files changed, 40 insertions(+), 29 deletions(-)

diff --git a/arch/microblaze/include/asm/pci.h b/arch/microblaze/include/asm/pci.h
index 0331376..8d11277 100644
--- a/arch/microblaze/include/asm/pci.h
+++ b/arch/microblaze/include/asm/pci.h
< at >< at > -149,8 +149,8 < at >< at > extern void pci_resource_to_user(const struct pci_dev *dev, int bar,
  const struct resource *rsrc,
  resource_size_t *start, resource_size_t *end);

-extern void pcibios_setup_bus_devices(struct pci_bus *bus);
 extern void pcibios_setup_bus_self(struct pci_bus *bus);
+extern void pcibios_setup_bus_notifier(void);

 /* This part of code was originally in xilinx-pci.h */
 #ifdef CONFIG_PCI_XILINX
diff --git a/arch/microblaze/pci/pci-common.c b/arch/microblaze/pci/pci-common.c
index 85f2ac1..bb28ede 100644
--- a/arch/microblaze/pci/pci-common.c
+++ b/arch/microblaze/pci/pci-common.c
< at >< at > -1063,31 +1063,6 < at >< at > void __devinit pcibios_setup_bus_self(struct pci_bus *bus)
 pcibios_fixup_bridge(bus);
 }

-void __devinit pcibios_setup_bus_devices(struct pci_bus *bus)
-{
-struct pci_dev *dev;
-
-pr_debug("PCI: Fixup bus devices %d (%s)\n",
- bus->number, bus->self ? pci_name(bus->self) : "PHB");
-
-list_for_each_entry(dev, &bus->devices, bus_list) {
-/* Setup OF node pointer in archdata */
-dev->dev.of_node = pci_device_to_OF_node(dev);
-
-/* Fixup NUMA node as it may not be setup yet by the generic
- * code and is needed by the DMA init
- */
-set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
-
-/* Hook up default DMA ops */
-set_dma_ops(&dev->dev, pci_dma_ops);
-dev->dev.archdata.dma_data = (void *)PCI_DRAM_OFFSET;
-
-/* Read default IRQs and fixup if necessary */
-pci_read_irq_line(dev);
-}
-}
-
 void __devinit pcibios_fixup_bus(struct pci_bus *bus)
 {
 /* When called from the generic PCI probe, read PCI<->PCI bridge
< at >< at > -1099,9 +1074,6 < at >< at > void __devinit pcibios_fixup_bus(struct pci_bus *bus)

 /* Now fixup the bus bus */
 pcibios_setup_bus_self(bus);
-
-/* Now fixup devices on that bus */
-pcibios_setup_bus_devices(bus);
 }
 EXPORT_SYMBOL(pcibios_fixup_bus);

< at >< at > -1604,6 +1576,43 < at >< at > static void __devinit pcibios_scan_phb(struct pci_controller *hose)
 hose->last_busno = bus->subordinate;
 }

+static int pcibios_device_change_notifier(struct notifier_block *nb,
+  unsigned long action, void *data)
+{
+struct pci_dev *dev = to_pci_dev(data);
+
+switch (action) {
+case BUS_NOTIFY_ADD_DEVICE:
+/* Setup OF node pointer in archdata */
+dev->dev.of_node = pci_device_to_OF_node(dev);
+
+/* Fixup NUMA node as it may not be setup yet by the generic
+ * code and is needed by the DMA init
+ */
+set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
+
+/* Hook up default DMA ops */
+set_dma_ops(&dev->dev, pci_dma_ops);
+dev->dev.archdata.dma_data = (void *)PCI_DRAM_OFFSET;
+
+/* Read default IRQs and fixup if necessary */
+pci_read_irq_line(dev);
+
+break;
+}
+
+return 0;
+}
+
+static struct notifier_block device_nb = {
+.notifier_call = pcibios_device_change_notifier,
+};
+
+void __devinit pcibios_setup_bus_notifier(void)
+{
+bus_register_notifier(&pci_bus_type, &device_nb);
+}
+
 static int __init pcibios_init(void)
 {
 struct pci_controller *hose, *tmp;
< at >< at > -1611,6 +1620,8 < at >< at > static int __init pcibios_init(void)

 printk(KERN_INFO "PCI: Probing PCI hardware\n");

+pcibios_setup_bus_notifier();
+
 /* Scan all of the recorded PCI controllers.  */
 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
 hose->last_busno = 0xff;

[PATCH v2 1/2] powerpc/PCI: Add pcibios_device_change_notifier for powerpc

Hiroo Matsumoto — 2012-05-23T02:33:54

pcibios_setup_bus_devices which sets DMA and IRQs of PCI device is called
only when boot, so DMA and IRQs of PCI device will not set when hotplug.
This patch adds pcibios_device_change_notifier which sets DMA and IRQs of
PCI device when PCI device adds, so DMA and IRQs of PCI device will be set
when boot and hotplug.

* Not patched pciehp message on powerpc platform
# echo 1 > /sys/bus/pci/slots/1/power
<snip>
pcieport 0000:02:01.0: PCI bridge to [bus 03-03]
pcieport 0000:02:01.0:   bridge window [io  0xff7ee000-0xff7eefff]
pcieport 0000:02:01.0:   bridge window [mem 0xa0100000-0xa01fffff]
pcieport 0000:02:01.0: bridge window [mem 0xa0200000-0xa02fffff 64bit pref]
pci 0000:03:00.0: no hotplug settings from platform
e1000e 0000:03:00.0: Disabling ASPM  L1
e1000e 0000:03:00.0: enabling device (0000 -> 0002)
e1000e 0000:03:00.0: No usable DMA configuration, aborting
e1000e: probe of 0000:03:00.0 failed with error -5

* Patched pciehp message on powerpc platform
# echo 1 > /sys/bus/pci/slots/1/power
<snip>
pcieport 0000:02:01.0: PCI bridge to [bus 03-03]
pcieport 0000:02:01.0:   bridge window [io  0xff7ee000-0xff7eefff]
pcieport 0000:02:01.0:   bridge window [mem 0xa0100000-0xa01fffff]
pcieport 0000:02:01.0: bridge window [mem 0xa0200000-0xa02fffff 64bit pref]
pci 0000:03:00.0: no hotplug settings from platform
e1000e 0000:03:00.0: Disabling ASPM  L1
e1000e 0000:03:00.0: enabling device (0000 -> 0002)
irq: irq 6 on host /soc< at >ffe00000/msi< at >41600 mapped to virtual irq 27
e1000e 0000:03:00.0: eth0: (PCI Express:2.5GT/s:Width x1) 00:15:17:bf:c0:c9
e1000e 0000:03:00.0: eth0: Intel(R) PRO/1000 Network Connection
e1000e 0000:03:00.0: eth0: MAC: 1, PHY: 4, PBA No: D50861-003

Signed-off-by: Hiroo MATSUMOTO <matsumoto.hiroo< at >jp.fujitsu.com>
---
 arch/powerpc/include/asm/pci.h             |    2 +-
 arch/powerpc/kernel/pci-common.c           |   87 ++++++++++++++--------------
 arch/powerpc/kernel/pci_32.c               |    2 +
 arch/powerpc/kernel/pci_64.c               |    2 +
 arch/powerpc/kernel/pci_of_scan.c          |    1 -
 arch/powerpc/platforms/pseries/pci_dlpar.c |    1 -
 drivers/pci/pci.c                          |    5 --
 drivers/pcmcia/cardbus.c                   |    3 +-
 include/linux/pci.h                        |    3 -
 9 files changed, 49 insertions(+), 57 deletions(-)

diff --git a/arch/powerpc/include/asm/pci.h b/arch/powerpc/include/asm/pci.h
index f54b3d2..7b4ca5a 100644
--- a/arch/powerpc/include/asm/pci.h
+++ b/arch/powerpc/include/asm/pci.h
< at >< at > -190,10 +190,10 < at >< at > extern void pci_resource_to_user(const struct pci_dev *dev, int bar,
  const struct resource *rsrc,
  resource_size_t *start, resource_size_t *end);

-extern void pcibios_setup_bus_devices(struct pci_bus *bus);
 extern void pcibios_setup_bus_self(struct pci_bus *bus);
 extern void pcibios_setup_phb_io_space(struct pci_controller *hose);
 extern void pcibios_scan_phb(struct pci_controller *hose);
+extern void pcibios_setup_bus_notifier(void);

 #endif/* __KERNEL__ */
 #endif /* __ASM_POWERPC_PCI_H */
diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c
index cce98d7..42a00b5 100644
--- a/arch/powerpc/kernel/pci-common.c
+++ b/arch/powerpc/kernel/pci-common.c
< at >< at > -1097,40 +1097,6 < at >< at > void __devinit pcibios_setup_bus_self(struct pci_bus *bus)
 ppc_md.pci_dma_bus_setup(bus);
 }

-void __devinit pcibios_setup_bus_devices(struct pci_bus *bus)
-{
-struct pci_dev *dev;
-
-pr_debug("PCI: Fixup bus devices %d (%s)\n",
- bus->number, bus->self ? pci_name(bus->self) : "PHB");
-
-list_for_each_entry(dev, &bus->devices, bus_list) {
-/* Cardbus can call us to add new devices to a bus, so ignore
- * those who are already fully discovered
- */
-if (dev->is_added)
-continue;
-
-/* Fixup NUMA node as it may not be setup yet by the generic
- * code and is needed by the DMA init
- */
-set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
-
-/* Hook up default DMA ops */
-set_dma_ops(&dev->dev, pci_dma_ops);
-set_dma_offset(&dev->dev, PCI_DRAM_OFFSET);
-
-/* Additional platform DMA/iommu setup */
-if (ppc_md.pci_dma_dev_setup)
-ppc_md.pci_dma_dev_setup(dev);
-
-/* Read default IRQs and fixup if necessary */
-pci_read_irq_line(dev);
-if (ppc_md.pci_irq_fixup)
-ppc_md.pci_irq_fixup(dev);
-}
-}
-
 void pcibios_set_master(struct pci_dev *dev)
 {
 /* No special bus mastering setup handling */
< at >< at > -1147,19 +1113,9 < at >< at > void __devinit pcibios_fixup_bus(struct pci_bus *bus)

 /* Now fixup the bus bus */
 pcibios_setup_bus_self(bus);
-
-/* Now fixup devices on that bus */
-pcibios_setup_bus_devices(bus);
 }
 EXPORT_SYMBOL(pcibios_fixup_bus);

-void __devinit pci_fixup_cardbus(struct pci_bus *bus)
-{
-/* Now fixup devices on that bus */
-pcibios_setup_bus_devices(bus);
-}
-
-
 static int skip_isa_ioresource_align(struct pci_dev *dev)
 {
 if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) &&
< at >< at > -1763,6 +1719,49 < at >< at > void __devinit pcibios_scan_phb(struct pci_controller *hose)
 }
 }

+static int pcibios_device_change_notifier(struct notifier_block *nb,
+  unsigned long action, void *data)
+{
+struct pci_dev *dev = to_pci_dev(data);
+
+switch (action) {
+case BUS_NOTIFY_ADD_DEVICE:
+/* Setup OF node pointer in the device */
+dev->dev.of_node = pci_device_to_OF_node(dev);
+
+/* Fixup NUMA node as it may not be setup yet by the generic
+ * code and is needed by the DMA init
+ */
+set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
+
+/* Hook up default DMA ops */
+set_dma_ops(&dev->dev, pci_dma_ops);
+set_dma_offset(&dev->dev, PCI_DRAM_OFFSET);
+
+/* Additional platform DMA/iommu setup */
+if (ppc_md.pci_dma_dev_setup)
+ppc_md.pci_dma_dev_setup(dev);
+
+/* Read default IRQs and fixup if necessary */
+pci_read_irq_line(dev);
+if (ppc_md.pci_irq_fixup)
+ppc_md.pci_irq_fixup(dev);
+
+break;
+}
+
+return 0;
+}
+
+static struct notifier_block device_nb = {
+.notifier_call = pcibios_device_change_notifier,
+};
+
+void __devinit pcibios_setup_bus_notifier(void)
+{
+bus_register_notifier(&pci_bus_type, &device_nb);
+}
+
 static void fixup_hide_host_resource_fsl(struct pci_dev *dev)
 {
 int i, class = dev->class >> 8;
diff --git a/arch/powerpc/kernel/pci_32.c b/arch/powerpc/kernel/pci_32.c
index fdd1a3d..5a30cec 100644
--- a/arch/powerpc/kernel/pci_32.c
+++ b/arch/powerpc/kernel/pci_32.c
< at >< at > -231,6 +231,8 < at >< at > static int __init pcibios_init(void)

 printk(KERN_INFO "PCI: Probing PCI hardware\n");

+pcibios_setup_bus_notifier();
+
 if (pci_has_flag(PCI_REASSIGN_ALL_BUS))
 pci_assign_all_buses = 1;

diff --git a/arch/powerpc/kernel/pci_64.c b/arch/powerpc/kernel/pci_64.c
index 3318d39..d66c9dc 100644
--- a/arch/powerpc/kernel/pci_64.c
+++ b/arch/powerpc/kernel/pci_64.c
< at >< at > -50,6 +50,8 < at >< at > static int __init pcibios_init(void)

 printk(KERN_INFO "PCI: Probing PCI hardware\n");

+pcibios_setup_bus_notifier();
+
 /* For now, override phys_mem_access_prot. If we need it,g
  * later, we may move that initialization to each ppc_md
  */
diff --git a/arch/powerpc/kernel/pci_of_scan.c b/arch/powerpc/kernel/pci_of_scan.c
index b37d0b5..1e29642 100644
--- a/arch/powerpc/kernel/pci_of_scan.c
+++ b/arch/powerpc/kernel/pci_of_scan.c
< at >< at > -329,7 +329,6 < at >< at > static void __devinit __of_scan_bus(struct device_node *node,
  */
 if (!rescan_existing)
 pcibios_setup_bus_self(bus);
-pcibios_setup_bus_devices(bus);

 /* Now scan child busses */
 list_for_each_entry(dev, &bus->devices, bus_list) {
diff --git a/arch/powerpc/platforms/pseries/pci_dlpar.c b/arch/powerpc/platforms/pseries/pci_dlpar.c
index 55d4ec1..fdb8b64 100644
--- a/arch/powerpc/platforms/pseries/pci_dlpar.c
+++ b/arch/powerpc/platforms/pseries/pci_dlpar.c
< at >< at > -120,7 +120,6 < at >< at > void pcibios_add_pci_devices(struct pci_bus * bus)
 num = pci_scan_slot(bus, PCI_DEVFN(slotno, 0));
 if (!num)
 return;
-pcibios_setup_bus_devices(bus);
 max = bus->secondary;
 for (pass=0; pass < 2; pass++)
 list_for_each_entry(dev, &bus->devices, bus_list) {
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index af295bb..f363b5d 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
< at >< at > -3698,11 +3698,6 < at >< at > int __attribute__ ((weak)) pci_ext_cfg_avail(struct pci_dev *dev)
 return 1;
 }

-void __weak pci_fixup_cardbus(struct pci_bus *bus)
-{
-}
-EXPORT_SYMBOL(pci_fixup_cardbus);
-
 static int __init pci_setup(char *str)
 {
 while (str) {
diff --git a/drivers/pcmcia/cardbus.c b/drivers/pcmcia/cardbus.c
index 9a58862..8f7baa6 100644
--- a/drivers/pcmcia/cardbus.c
+++ b/drivers/pcmcia/cardbus.c
< at >< at > -71,7 +71,6 < at >< at > int __ref cb_alloc(struct pcmcia_socket *s)
 unsigned int max, pass;

 s->functions = pci_scan_slot(bus, PCI_DEVFN(0, 0));
-pci_fixup_cardbus(bus);

 max = bus->secondary;
 for (pass = 0; pass < 2; pass++)
< at >< at > -85,7 +84,6 < at >< at > int __ref cb_alloc(struct pcmcia_socket *s)
  */
 pci_bus_size_bridges(bus);
 pci_bus_assign_resources(bus);
-cardbus_config_irq_and_cls(bus, s->pci_irq);

 /* socket specific tune function */
 if (s->tune_bridge)
< at >< at > -93,6 +91,7 < at >< at > int __ref cb_alloc(struct pcmcia_socket *s)

 pci_enable_bridges(bus);
 pci_bus_add_devices(bus);
+cardbus_config_irq_and_cls(bus, s->pci_irq);

 return 0;
 }
diff --git a/include/linux/pci.h b/include/linux/pci.h
index a16b1df..56f50fd 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
< at >< at > -651,9 +651,6 < at >< at > resource_size_t pcibios_align_resource(void *, const struct resource *,
 resource_size_t);
 void pcibios_update_irq(struct pci_dev *, int irq);

-/* Weak but can be overriden by arch */
-void pci_fixup_cardbus(struct pci_bus *);
-
 /* Generic PCI functions used internally */

 void pcibios_scan_specific_bus(int busn);

[PATCH v2 0/2] Add pcibios_device_change_notifier

Hiroo Matsumoto — 2012-05-23T02:33:42

This patchset is for PCI hotplug.


pcibios_setup_bus_devices which sets DMA and IRQs of PCI device is called
only when boot. DMA setting in probe for PCI driver, like dma_set_mask,
does not work on powerpc platform. So it is need to set DMA and IRQs of
PCI device when hotplug.

1. Moving pcibios_setup_bus_devices code to pcibios_device_change_notifier
   which is registered to bus notifier in pcibios_init.
2. Removing caller and callee of pcibios_setup_bus_devices bus notifier
   works instead of pcibios_setup_bus_devices.
3. Using this bus notifier for microblaze because microblaze/PCI is similer
   with powerpc/PCI.

[PATCH v2 1/2] powerpc/PCI: Add pcibios_device_change_notifier for powerpc
[PATCH v2 2/2] microblaze/PCI: Add pcibios_device_change_notifier for microblaze


Regards.

Hiroo MATSUMOTO

[PATCH] pci hotplug: rescan bridge after device hotplug

Jason Baron — 2012-05-22T20:11:38

I'm tyring to support bridge hotplug and devices below it in qemu via acpi
hotplug. Currently only 1 level or 32 slots are supported. By allowing for a
second level, we will be able to support 32^2 devices.

If I first hotplug the bridge with no devices intially below it, the hotplug
code sets the bridge memory window to 0 and does not increase it when
subsequent devices are added below it.

Fix this, by calling pci_rescan_bus_bridge_resize(), on the bridge directly
below the root to re-size all the birdge windows that may have changed.

Signed-off-by: Jason Baron <jbaron< at >redhat.com>
---
 drivers/pci/hotplug/acpiphp_glue.c |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/drivers/pci/hotplug/acpiphp_glue.c b/drivers/pci/hotplug/acpiphp_glue.c
index 806c44f..8960c1e 100644
--- a/drivers/pci/hotplug/acpiphp_glue.c
+++ b/drivers/pci/hotplug/acpiphp_glue.c
< at >< at > -792,6 +792,7 < at >< at > static int __ref enable_device(struct acpiphp_slot *slot)
 {
 struct pci_dev *dev;
 struct pci_bus *bus = slot->bridge->pci_bus;
+struct pci_bus *rescan_bus;
 struct acpiphp_func *func;
 int retval = 0;
 int num, max, pass;
< at >< at > -821,6 +822,13 < at >< at > static int __ref enable_device(struct acpiphp_slot *slot)
 }
 }
 
+/* Ensure we rescan/setup a bridge for new devs hanging off of it */
+rescan_bus = bus;
+while (rescan_bus->parent && rescan_bus->parent->self)
+rescan_bus = rescan_bus->parent;
+if (rescan_bus->self)
+pci_rescan_bus_bridge_resize(rescan_bus->self);
+
 list_for_each_entry(func, &slot->funcs, sibling)
 acpiphp_bus_add(func);

Order Enquiry

Mcckoy Robertson — 2012-05-20T14:54:02

Hello Sales
     I went over your contact online and found some items which we have interest in purchasing to our store in Spain for urgent supply. I will like to know the prices per each items plus the shipping cost. I also want to know if Letter of Credit or T/T is acceptable for payment. I await your quick response asap so i can proceed with my needed items and quantity.

Thank you
mcckoy robertson


N.B.M Global Supply Inc
Address: Autovía A-5,
salidas 22 y 26.
Arroyomolinos,
28939 Madrid Spain
Tel: +34 902 26 77 26
Email: nbmglobalsupply< at >gmail.com
Website : http://www.brplastics.com

PCIe Hotpluggable Systems

LinuxDrvDev — 2012-05-18T01:09:57

I am looking for a reliable PCIe hot pluggable system. I am not able to find reliable information on workstations from usual vendors like Dell and HP. Their servers supports this feature but they are kind of pricey for us to verify hotpluggability of our device. I had a system with one slot which supported hot plug but the bios didn't enabled it(and there was no way for user to enable it). So if anyone is using any mother board which has reliable hot plug feature, please recommend it. 
Thanks.

[PATCH] pci, Add AER_panic sysfs file

Prarit Bhargava — 2012-05-17T17:04:30

Consider the following case

[ RP ]
  |
  |
+---------+-----------+
|  |      |
       [H1]      [H2]        [X1]

where RP is a PCIE Root Port, H1 and H2 are devices with drivers that support
PCIE AER driver error handling (ie, they have pci_error_handlers defined in
the driver), and X1 is a device with a driver that does not support PCIE
AER driver error handling.

If the Root Port takes an error what currently happens is that the
bus resets and H1 & H2 call their slot_reset functions.  X1 does nothing.

In some cases a user may not wish the system to continue because X1 is
an unhardened driver.  In these cases, the system should not do a bus reset,
but rather the system should panic to avoid any further possible data
corruption.

This patch implements an AER_panic sysfs entry for each root port which
a user can modify.  AER_panic = 1, means the system will panic on a
PCIE error which would have normally resulted in a secondary bus reset.

Signed-off-by: Prarit Bhargava <prarit< at >redhat.com>
Cc: Bjorn Helgaas <bhelgaas< at >google.com>
---
 drivers/pci/pci-sysfs.c       |   42 ++++++++++++++++++++++++++++++++++++++++-
 drivers/pci/pcie/aer/aerdrv.c |    3 ++
 include/linux/pci.h           |    1 +
 3 files changed, 45 insertions(+), 1 deletions(-)

diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c
index a55e248..8c6d525 100644
--- a/drivers/pci/pci-sysfs.c
+++ b/drivers/pci/pci-sysfs.c
< at >< at > -1135,6 +1135,35 < at >< at > static ssize_t reset_store(struct device *dev,
 
 static struct device_attribute reset_attr = __ATTR(reset, 0200, NULL, reset_store);
 
+static ssize_t AER_panic_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+struct pci_dev *pdev = to_pci_dev(dev);
+
+return sprintf(buf, "%d\n", pdev->rp_AER_panic);
+}
+
+static ssize_t AER_panic_store(struct device *dev,
+  struct device_attribute *attr,
+  const char *buf, size_t count)
+{
+struct pci_dev *pdev = to_pci_dev(dev);
+unsigned long val;
+
+if (kstrtoul(buf, 0, &val) < 0)
+return -EINVAL;
+
+if ((val > 1) || (val < 0))
+return -EINVAL;
+
+pdev->rp_AER_panic = val;
+
+return count;
+}
+
+static struct device_attribute rp_AER_panic_attr =
+      __ATTR(AER_panic, 0600, AER_panic_show, AER_panic_store);
+
 static int pci_create_capabilities_sysfs(struct pci_dev *dev)
 {
 int retval;
< at >< at > -1169,8 +1198,16 < at >< at > static int pci_create_capabilities_sysfs(struct pci_dev *dev)
 goto error;
 dev->reset_fn = 1;
 }
-return 0;
 
+/* PCIE Root Port panic-on-AER allows a user to configure each root
+ * port to panic on an AER error instead of issuing a bus reset.
+ */
+if (dev->pcie_type == PCI_EXP_TYPE_ROOT_PORT) {
+retval = device_create_file(&dev->dev, &rp_AER_panic_attr);
+if (retval)
+goto error;
+}
+return 0;
 error:
 pcie_aspm_remove_sysfs_dev_files(dev);
 if (dev->vpd && dev->vpd->attr) {
< at >< at > -1279,6 +1316,9 < at >< at > static void pci_remove_capabilities_sysfs(struct pci_dev *dev)
 device_remove_file(&dev->dev, &reset_attr);
 dev->reset_fn = 0;
 }
+
+if (dev->pcie_type == PCI_EXP_TYPE_ROOT_PORT)
+device_remove_file(&dev->dev, &rp_AER_panic_attr);
 }
 
 /**
diff --git a/drivers/pci/pcie/aer/aerdrv.c b/drivers/pci/pcie/aer/aerdrv.c
index 58ad791..dd6b352 100644
--- a/drivers/pci/pcie/aer/aerdrv.c
+++ b/drivers/pci/pcie/aer/aerdrv.c
< at >< at > -346,6 +346,9 < at >< at > static pci_ers_result_t aer_root_reset(struct pci_dev *dev)
 u32 reg32;
 int pos;
 
+if (dev->rp_AER_panic)
+panic("%s: AER detected on Root Port", pci_name(dev));
+
 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
 
 /* Disable Root's interrupt in response to error messages */
diff --git a/include/linux/pci.h b/include/linux/pci.h
index e444f5b..a4e6a5a 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
< at >< at > -324,6 +324,7 < at >< at > struct pci_dev {
 unsigned int    is_hotplug_bridge:1;
 unsigned int    __aer_firmware_first_valid:1;
 unsigned int__aer_firmware_first:1;
+unsigned intrp_AER_panic:1; /* if 1, panic on AER bus reset */
 pci_dev_flags_t dev_flags;
 atomic_tenable_cnt;/* pci_enable_device has been called */

[Bug 43192] various ExpressCards are not recognized

Bjorn Helgaas — 2012-05-17T16:16:56

https://bugzilla.kernel.org/show_bug.cgi?id=43192

Hi Elmar, can you attach a complete dmesg log and "lspci -vv" output
to the bugzilla?  Let's start with the system with native ExpressCard
interface, with an ExpressCard plugged in before booting the system.

[PATCH] Only decode defined fields of PCI Express Link Control 2

Ben Hutchings — 2012-05-17T14:14:16

On a PCI Express multi-function device associated with an upstream
port, all bits of the Link Control 2 register are currently reserved
on functions > 0.

The Selectable De-emphasis field is reserved on all but downstream
ports.

Signed-off-by: Ben Hutchings <bhutchings< at >solarflare.com>
---
 ls-caps.c |   20 +++++++++++++-------
 1 files changed, 13 insertions(+), 7 deletions(-)

diff --git a/ls-caps.c b/ls-caps.c
index 9645e5a..4a75ce7 100644
--- a/ls-caps.c
+++ b/ls-caps.c
< at >< at > -991,22 +991,28 < at >< at > static const char *cap_express_link2_transmargin(int type)
     }
 }
 
-static void cap_express_link2(struct device *d, int where, int type UNUSED)
+static void cap_express_link2(struct device *d, int where, int type)
 {
   u16 w;
 
-  w = get_conf_word(d, where + PCI_EXP_LNKCTL2);
-  printf("\t\tLnkCtl2: Target Link Speed: %s, EnterCompliance%c SpeedDis%c, Selectable De-emphasis: %s\n"
-"\t\t\t Transmit Margin: %s, EnterModifiedCompliance%c ComplianceSOS%c\n"
-"\t\t\t Compliance De-emphasis: %s\n",
+  if (!((type == PCI_EXP_TYPE_ENDPOINT || type == PCI_EXP_TYPE_LEG_END) &&
+(d->dev->dev != 0 || d->dev->func != 0))) {
+    w = get_conf_word(d, where + PCI_EXP_LNKCTL2);
+    printf("\t\tLnkCtl2: Target Link Speed: %s, EnterCompliance%c SpeedDis%c",
 cap_express_link2_speed(PCI_EXP_LNKCTL2_SPEED(w)),
 FLAG(w, PCI_EXP_LNKCTL2_CMPLNC),
-FLAG(w, PCI_EXP_LNKCTL2_SPEED_DIS),
-cap_express_link2_deemphasis(PCI_EXP_LNKCTL2_DEEMPHASIS(w)),
+FLAG(w, PCI_EXP_LNKCTL2_SPEED_DIS));
+    if (type == PCI_EXP_TYPE_DOWNSTREAM)
+      printf(", Selectable De-emphasis: %s",
+cap_express_link2_deemphasis(PCI_EXP_LNKCTL2_DEEMPHASIS(w)));
+    printf("\n"
+"\t\t\t Transmit Margin: %s, EnterModifiedCompliance%c ComplianceSOS%c\n"
+"\t\t\t Compliance De-emphasis: %s\n",
 cap_express_link2_transmargin(PCI_EXP_LNKCTL2_MARGIN(w)),
 FLAG(w, PCI_EXP_LNKCTL2_MOD_CMPLNC),
 FLAG(w, PCI_EXP_LNKCTL2_CMPLNC_SOS),
 cap_express_link2_deemphasis(PCI_EXP_LNKCTL2_COM_DEEMPHASIS(w)));
+  }
 
   w = get_conf_word(d, where + PCI_EXP_LNKSTA2);
   printf("\t\tLnkSta2: Current De-emphasis Level: %s, EqualizationComplete%c, EqualizationPhase1%c\n"

BUSINESS PROPOSAL!!

WONG HUI — 2012-05-16T10:50:44

[PATCH] PCI: allow acpiphp to handle PCIe ports without native PCIe hotplug capability

Jiang Liu — 2012-05-17T03:40:12

From: Jiang Liu <jiang.liu< at >huawei.com>

Commit 0d52f54e2ef64c189dedc332e680b2eb4a34590a (PCI / ACPI: Make acpiphp
ignore root bridges using PCIe native hotplug) added code that made the
acpiphp driver completely ignore PCIe root complexes for which the kernel
had been granted control of the native PCIe hotplug feature by the BIOS
through _OSC. Later commit 619a5182d1f38a3d629ee48e04fa182ef9170052
"PCI hotplug: Always allow acpiphp to handle non-PCIe bridges" relaxed
the constraints to allow acpiphp driver handle non-PCIe bridges under
such a complex. The constraint needs to be relaxed further to allow
acpiphp driver to hanlde PCIe ports without native PCIe hotplug capability.

Some MR-IOV switch chipsets, such PLX8696, support multiple virtual PCIe
switches and may migrate downstream ports among virtual switches.
To migrate a downstream port from the source virtual switch to the target,
the port needs to be hot-removed from the source and hot-added into the
target. pciehp driver can't be used here because there's no slots within
the virtual PCIe switch. So acpiphp driver is used to support downstream
port migration. A typical configuration is as below:
[Root w/o native PCIe HP]
[Upstream port of vswitch w/o native PCIe HP]
[Downstream port of vswitch w/ native PCIe HP]
[PCIe enpoint]

Here acpiphp driver will be used to handle root ports and upstream port
in the virtual switch, and pciehp driver will be used to handle downstream
ports in the virtual switch.

Signed-off-by: Jiang Liu <liuj97< at >gmail.com>
---
 drivers/pci/hotplug/acpiphp_glue.c |   49 ++++++++++++++++++++++++++++-------
 1 files changed, 39 insertions(+), 10 deletions(-)

diff --git a/drivers/pci/hotplug/acpiphp_glue.c b/drivers/pci/hotplug/acpiphp_glue.c
index 806c44f..4889448 100644
--- a/drivers/pci/hotplug/acpiphp_glue.c
+++ b/drivers/pci/hotplug/acpiphp_glue.c
< at >< at > -115,6 +115,43 < at >< at > static const struct acpi_dock_ops acpiphp_dock_ops = {
 .handler = handle_hotplug_event_func,
 };
 
+/* Check whether device is managed by native PCIe hotplug driver */
+static bool device_is_managed_by_native_pciehp(struct pci_dev *pdev)
+{
+int pos;
+u16 reg16;
+u32 reg32;
+acpi_handle tmp;
+struct acpi_pci_root *root;
+
+if (!pci_is_pcie(pdev))
+return false;
+
+/* Check whether PCIe port supports native PCIe hotplug */
+pos = pci_pcie_cap(pdev);
+pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
+if (!(reg16 & PCI_EXP_FLAGS_SLOT))
+return false;
+pci_read_config_dword(pdev, pos + PCI_EXP_SLTCAP, &reg32);
+if (!(reg32 & PCI_EXP_SLTCAP_HPC))
+return false;
+
+/*
+ * Check whether native PCIe hotplug has been enabled for
+ * this PCIe hierarchy.
+ */
+tmp = acpi_find_root_bridge_handle(pdev);
+if (!tmp)
+return false;
+root = acpi_pci_find_root(tmp);
+if (!root)
+return false;
+if (!(root->osc_control_set & OSC_PCI_EXPRESS_NATIVE_HP_CONTROL))
+return false;
+
+return true;
+}
+
 /* callback routine to register each ACPI PCI slot object */
 static acpi_status
 register_slot(acpi_handle handle, u32 lvl, void *context, void **rv)
< at >< at > -133,16 +170,8 < at >< at > register_slot(acpi_handle handle, u32 lvl, void *context, void **rv)
 return AE_OK;
 
 pdev = pbus->self;
-if (pdev && pci_is_pcie(pdev)) {
-tmp = acpi_find_root_bridge_handle(pdev);
-if (tmp) {
-struct acpi_pci_root *root = acpi_pci_find_root(tmp);
-
-if (root && (root->osc_control_set &
-OSC_PCI_EXPRESS_NATIVE_HP_CONTROL))
-return AE_OK;
-}
-}
+if (pdev && device_is_managed_by_native_pciehp(pdev))
+return AE_OK;
 
 acpi_evaluate_integer(handle, "_ADR", NULL, &adr);
 device = (adr >> 16) & 0xffff;

Hotplug Debugging

LinuxDrvDev — 2012-05-16T02:51:26

Hi,

I have a Gigabyte Motherboard and I am trying to hot remove and hot add a Marvell's PCI SATA controller card, but it doesn't work. I am using 3.2.17 kernel with hotplug configured. Also, I turned the debug messages by using pciehp_debug=1 and am forcibly loading the module by using pciehp_force=1. However I don't see any debug messages from the pciehp driver, besides the following - 

pciehp: PCI Express Hot Plug Controller Driver version: 0.4
I don't see any other message suggesting that the absence of hotplug controller. 

I have basic questions -
1. How do I find out, for sure, if the board has hot plug controller? Also, is there a way to find out if a particular slot is hotpluggable?
2. The lspci -vv output of the root port and the device shows that "ASPM  disabled". Is this the indication that it doesn't support hotplug?
3. Also in some of the posts it talks about /sys/bus/pci/slots/<device>/power, however, on my system the slots directory is empty!? Does it mean I don't have the hotpluggable system?

regards,
Ushma.