gmane.linux.kernel.firewire.devel

[PATCH libraw1394 0/3] Copy firewire-cdev headers into libraw1394sources

Stefan Richter — 2012-05-25T22:18:02

The following patches are available in the "testing" branch at

    git://git.kernel.org/pub/scm/libs/ieee1394/libraw1394.git testing

and will also be posted right away for review.  If there are no complaints,
I will fetch it into the master branch and cut a 2.0.9 release from this
soon.

Motives for the changes are explained in patch 2/3.  I don't recommend to
do something like this in each and every firewire-cdev based program; I
just felt that this is preferable for the case of a base library that
libraw1394 is, especially after an incident in which obscure problems with
audio devices were caused by a libraw1394 which was built with outdated
kernel headers.

Stefan Richter (3):
      Add firewire-{cdev,constants}.h from Linux v3.4
      Include local firewire-*.h instead of system-wide <linux/firewire-*.h>
      Remove unused code

 configure.ac             |    7 -
 src/Makefile.am          |   11 +-
 src/firewire-cdev.h      | 1038 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 src/firewire-constants.h |   92 ++++++
 src/fw-iso.c             |    9 -
 src/fw.c                 |   64 +---
 src/fw.h                 |    4 +-
 7 files changed, 1143 insertions(+), 82 deletions(-)

Changes to the FireWire kernel drivers in Linux 3.4

Stefan Richter — 2012-05-24T20:44:47

Hi all,

Linux kernel 3.4 has been released last Sunday.  These are the IEEE 1394
related changes:

<linux/firewire-cdev.h> API:
  - Added FW_CDEV_IOC_FLUSH_ISO ioctl which lets an application get any
    currently completed isochronous packets reported.  A corresponding
    libraw1394 update to use this ioctl in raw1394_iso_recv_flush() has
    been committed to libraw1394.git too and will show up in the next
    libraw1394 release.

firewire-core, -net, -ohci, -sbp2:
  - All messages to the kernel log are now consistently prefixed by driver
    name and device name or number.

firewire-ohci:
  - Fix premature completion of multichannel isochronous reception DMA.
    Also fixed in kernel 3.3.1, 3.2.14, 3.0.27.
  - Fix missing completion notification in isochronous I/O in case of big
    intervals between interrupt packets or with big packet headers.

firewire-sbp2:
  - If the target's unit directory contains a Unit_Unique_ID entry, use it
    instead of the node unique ID as the target's GUID in the ieee1394_id
    sysfs attribute and consequently in udev's /dev/disk/by-id symbolic
    links.
  - Do not try to log into targets on the local node. I/O to such targets
    is not yet implemented, and local targets are probably meant to be
    accessed by remote initiators anyway.
  - Fix handling of SCSI sense data (deferred errors, Valid, Filemark,
    EOM, ILI).

[git pull] FireWire updates post v3.4

Stefan Richter — 2012-05-24T19:14:55

Linus,

please pull from the tag "firewire-updates" at

    git://git.kernel.org/pub/scm/linux/kernel/git/ieee1394/linux1394.git firewire-updates

to receive the following IEEE 1394 (FireWire) subsystem updates:

  - Fix mismatch between DMA mapping direction (was wrong) and DMA synchronization
    direction (was correct) of isochronous reception buffers of userspace drivers
    if vma-mapped for R/W access.  For example, libdc1394 was affected.

  - more consistent retry stategy in device discovery/ rediscovery, and improved
    failure diagnostics

  - various small cleanups, e.g. use SCSI layer's DMA mapping API in firewire-sbp2

The last few commits happened rather late for this pull request but I feel comfortable
with them.  ALSA firewire-lib changes were written by Clemens, hence are implicitly ACKed.

Axel Lin (1):
      firewire: use module_pci_driver

Clemens Ladisch (10):
      firewire: core: wait for inaccessible devices after bus reset
      firewire: core: improve reread_config_rom() interface
      firewire: move rcode_string() to core
      firewire: core: log error in case of failed bus manager lock
      firewire: core: log config rom reading errors
      firewire: core: fw_device_refresh(): clean up error handling
      firewire: sbp2: give correct DMA device to scsi framework
      firewire: sbp2: use scsi_dma_(un)map
      firewire: sbp2: remove superfluous blk_queue_max_segment_size() call
      firewire: sbp2: document the absence of alignment requirements

Stefan Richter (4):
      firewire: core: fix DMA mapping direction
      firewire: ohci: correct signedness of a local variable
      firewire: ohci: omit spinlock IRQ flags where possible
      Merge tag 'v3.4' with SCSI updates, needed for subsequent firewire-sbp2 changes

 drivers/firewire/core-card.c        |    4 +-
 drivers/firewire/core-cdev.c        |   51 ++++++++++++---
 drivers/firewire/core-device.c      |  116 +++++++++++++++++------------------
 drivers/firewire/core-iso.c         |   80 +++++++++++++++---------
 drivers/firewire/core-transaction.c |   26 ++++++++
 drivers/firewire/core.h             |    7 ++-
 drivers/firewire/nosy.c             |   20 ++----
 drivers/firewire/ohci.c             |   42 +++++--------
 drivers/firewire/sbp2.c             |   28 ++++-----
 include/linux/firewire.h            |    2 +
 sound/firewire/cmp.c                |    2 +-
 sound/firewire/lib.c                |   28 +--------
 sound/firewire/lib.h                |    1 -
 13 files changed, 218 insertions(+), 189 deletions(-)

Thanks,

[PATCH 1/2] firewire: core: make address handler length 64 bits

Clemens Ladisch — 2012-05-24T17:28:17

The type of the length field of the fw_address_handler structure was
size_t, which restricted it to 32 bits on 32-bit architectures.

While making it u32 would match the userspace API, all calculations on
this field use 64 bits anyway, and the ability to use 4 GB or larger
address ranges is useful in the kernel.

Signed-off-by: Clemens Ladisch <clemens< at >ladisch.de>
---
 include/linux/firewire.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

--- a/include/linux/firewire.h
+++ b/include/linux/firewire.h
< at >< at > -307,7 +307,7 < at >< at > struct fw_transaction {

 struct fw_address_handler {
 u64 offset;
-size_t length;
+u64 length;
 fw_address_callback_t address_callback;
 void *callback_data;
 struct list_head link;

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[PATCH 0/4] various SBP-2 DMA cleanups

Clemens Ladisch — 2012-05-18T16:38:20

 drivers/firewire/sbp2.c |   26 ++++++++------------------
 1 file changed, 8 insertions(+), 18 deletions(-)

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libraw1394 plans

Stefan Richter — 2012-05-11T18:44:34

Hi all,

at the moment I would like to proceed with libraw1394 like this:

1. Add a copy of linux/firewire-{constants,cdev}.h to the libraw1394
sources in order to ensure that all features which a particular libraw1394
version supports are actually built, rather than silently disabled at
build time if older kernel headers are present.

2. Release libraw1394 v2.0.9.

3. Add an API to add a descriptor to the local Config ROM:
http://thread.gmane.org/gmane.linux.kernel.firewire.devel/14878/focus=14881

  - Do we want the remove-descriptor counterpart too, or would
    applications be satisfied with exit() or raw1394_destroy_handle() to
    do so?

4. Add an API which does the same as raw1394_read_cycle_timer() but lets
the user select a clock other than CLOCK_REALTIME (e.g. the monotonic
clock which is never reset by ntpd or other means to set the clock).
http://subversion.ffado.org/ticket/242

  - Should that new API stay with u_int64_t *local_time (microseconds,
    i.e. a like the struct timeval *tv argument of gettimeofday() but
    rolled out to tv_sec * 1000000 + tv_usec), or should we make use of
    the nanoseconds resolution that the underlying ioctl would offer, e.g.
    as struct timespec *tp like the respective argument of clock_gettime()?
    Even if nanoseconds resolution is not required by the application, the
    application might want to use clock_gettime() along with this new
    libraw1394 API too.

  - Does anybody have a suggestion for a name?  I would tastelessly call it
    raw1394_read_cycle_timer2().  Or raw1394_read_cycle_timer_and_clock()
    perhaps?

3.a. Add a unit test of the add-descriptor API to testlibraw.

4.a  Add a unit test of the new read-cycle-timer API to testlibraw.

5. Release libraw1394 v2.1.0.

These are rather simple and straightforward steps, so I should just do them
rather than talk about them...  Meanwhile, opinions on the questions above
are appreciated.

6./7. Get the bus topology change related bugs sorted out; implement
multichannel reception.

ieee1394.wiki.kernel.org fully functional again

Stefan Richter — 2012-05-02T21:02:13

Hi all,

today, editing functionality of the wikis at kernel.org has been restored.
I will slowly update the ieee1394.wiki with current release notes, to-do
items etc. but everyone else is of course welcome to do so as well.

Fw: [Bug 10935] fw-ohci: ALi M52xx unsupported

Stefan Richter — 2012-05-01T11:14:25

For the list to know:

Date: Tue, 1 May 2012 11:09:12 GMT
From: bugzilla-daemon< at >bugzilla.kernel.org
To: stefanr< at >s5r6.in-berlin.de
Subject: [Bug 10935] fw-ohci: ALi M52xx unsupported


https://bugzilla.kernel.org/show_bug.cgi?id=10935


Stefan Richter <stefanr< at >s5r6.in-berlin.de> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|NEW                         |RESOLVED
         Resolution|                            |INVALID




--- Comment #15 from Stefan Richter <stefanr< at >s5r6.in-berlin.de>
2012-05-01 11:09:12 --- After a long while of using the PCI slots for
other cards, I put the Belkin F50508 back in yesterday in order to get
back to this bug again.

-------------------------------------------------------------------------
boot
-------------------------------------------------------------------------

Apr 30 20:38:16 stein kernel: pci 0000:0c:07.0: [10b9:5237] type 00 class 0x0c0310
Apr 30 20:38:16 stein kernel: pci 0000:0c:07.0: reg 10: [mem 0xfb7ff000-0xfb7fffff]
Apr 30 20:38:16 stein kernel: pci 0000:0c:07.0: PME# supported from D0 D1 D3hot D3cold
Apr 30 20:38:16 stein kernel: pci 0000:0c:07.1: [10b9:5237] type 00 class 0x0c0310
Apr 30 20:38:16 stein kernel: pci 0000:0c:07.1: reg 10: [mem 0xfb7fe000-0xfb7fefff]
Apr 30 20:38:16 stein kernel: pci 0000:0c:07.1: PME# supported from D0 D1 D3hot D3cold
Apr 30 20:38:16 stein kernel: pci 0000:0c:07.3: [10b9:5239] type 00 class 0x0c0320
Apr 30 20:38:16 stein kernel: pci 0000:0c:07.3: reg 10: [mem 0xfb7fdc00-0xfb7fdcff]
Apr 30 20:38:16 stein kernel: pci 0000:0c:07.3: PME# supported from D0 D3hot D3cold
Apr 30 20:38:16 stein kernel: pci 0000:0c:07.4: [10b9:5253] type 00 class 0x0c0010
Apr 30 20:38:16 stein kernel: pci 0000:0c:07.4: reg 10: [mem 0xfb7fd000-0xfb7fd7ff]
Apr 30 20:38:16 stein kernel: pci 0000:0c:07.4: reg 30: [mem 0xfb7e0000-0xfb7effff pref]
Apr 30 20:38:16 stein kernel: pci 0000:0c:07.4: supports D1 D2
Apr 30 20:38:16 stein kernel: pci 0000:0c:07.4: PME# supported from D1 D2 D3hot
Apr 30 20:38:16 stein kernel: ehci_hcd 0000:0c:07.3: EHCI Host Controller
Apr 30 20:38:16 stein kernel: ehci_hcd 0000:0c:07.3: new USB bus registered, assigned bus number 3
Apr 30 20:38:16 stein kernel: ehci_hcd 0000:0c:07.3: debug port 1
Apr 30 20:38:16 stein kernel: ehci_hcd 0000:0c:07.3: irq 21, io mem 0xfb7fdc00
Apr 30 20:38:16 stein kernel: ehci_hcd 0000:0c:07.3: USB 2.0 started, EHCI 1.00
Apr 30 20:38:16 stein kernel: ohci_hcd 0000:0c:07.0: OHCI Host Controller
Apr 30 20:38:16 stein kernel: ohci_hcd 0000:0c:07.0: new USB bus registered, assigned bus number 9
Apr 30 20:38:16 stein kernel: ohci_hcd 0000:0c:07.0: irq 22, io mem 0xfb7ff000
Apr 30 20:38:16 stein kernel: ohci_hcd 0000:0c:07.1: OHCI Host Controller
Apr 30 20:38:16 stein kernel: ohci_hcd 0000:0c:07.1: new USB bus registered, assigned bus number 10
Apr 30 20:38:16 stein kernel: ohci_hcd 0000:0c:07.1: irq 22, io mem 0xfb7fe000

-------------------------------------------------------------------------
modprobe firewire-ohci debug=2
-------------------------------------------------------------------------

Apr 30 20:51:49 stein kernel: firewire_ohci 0000:0c:07.4: added OHCI v1.10 device as card 4, 4 IR + 8 IT contexts, quirks 0x1
Apr 30 20:51:49 stein kernel: firewire_ohci 0000:0c:07.4: 1 selfIDs, generation 1, local node ID ffc0
Apr 30 20:51:49 stein kernel: firewire_ohci 0000:0c:07.4: selfID 0: 807f8c56, phy 0 [---] S400 gc=63 -3W Lci
Apr 30 20:51:50 stein kernel: firewire_core 0000:0c:07.4: created device fw7: GUID 0030bd051800064f, S400

-------------------------------------------------------------------------
plug in a bus-powered camera
-------------------------------------------------------------------------

May  1 12:40:41 stein kernel: ohci_hcd 0000:0c:07.1: HC died; cleaning up

-------------------------------------------------------------------------
plug the camera out again
-------------------------------------------------------------------------

results in bus reset on two other FireWire controllers (on the same PSU
power rail), and the video screen goes off, showing just black + vertical
stripes

-------------------------------------------------------------------------

So this card is evidently seriously buggy or defective at least WRT bus
power supply.  I now removed it from my PC and do not intend to experiment
with it further.

Read Now

Sgt Larry Wayne — 2012-04-28T08:40:15

Hello,

My name is Staff Sergeant Larry Wayne with a desperate need for an mutual business proposal that will benefit both of us, please get back to me if you are interested to hear
Sgt Larry Wayne

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[PATCH 0/6] error handling improvements

Clemens Ladisch — 2012-04-11T15:35:39

... I just got annoyed that the "BM lock failed" and "giving up" messages
did not show the actual error; and fixed other things along the way.

 drivers/firewire/core-card.c        |    4
 drivers/firewire/core-device.c      |  124 +++++++++++++---------------
 drivers/firewire/core-transaction.c |   26 +++++
 include/linux/firewire.h            |    1
 sound/firewire/lib.c                |   28 ------
 sound/firewire/lib.h                |    1
 6 files changed, 91 insertions(+), 93 deletions(-)

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[PATCH 1/2] firewire: ohci: correct signedness of a local variable

Stefan Richter — 2012-04-09T19:39:53

bus_reset_work's reg is a bitfield.

Signed-off-by: Stefan Richter <stefanr< at >s5r6.in-berlin.de>
---
 drivers/firewire/ohci.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

--- a/drivers/firewire/ohci.c
+++ b/drivers/firewire/ohci.c
< at >< at > -1822,8 +1822,8 < at >< at > static void bus_reset_work(struct work_s
 {
 struct fw_ohci *ohci =
 container_of(work, struct fw_ohci, bus_reset_work);
-int self_id_count, i, j, reg;
-int generation, new_generation;
+int self_id_count, generation, new_generation, i, j;
+u32 reg;
 unsigned long flags;
 void *free_rom = NULL;
 dma_addr_t free_rom_bus = 0;

firewire-cdev: DMA synchronization mismatch

Stefan Richter — 2012-04-09T16:26:23

fw_device_op_mmap()'s decision for a DMA direction can go wrong.  I just got
this after a libdc1394 update on a PC with DMA mapping API debugging turned on:

Apr  9 17:56:14 mini WARNING: at lib/dma-debug.c:989 check_sync+0x2e4/0x508()
Apr  9 17:56:14 mini Hardware name: Macmini1,1
Apr  9 17:56:14 mini firewire_ohci 0000:03:03.0: DMA-API: device driver syncs DMA memory with different direction [device address=0x00000000316e3000] [size=4096 bytes] [mapped with DMA_TO_DEVICE] [synced with DMA_FROM_DEVICE]
Apr  9 17:56:14 mini Modules linked in: firewire_ohci firewire_core netconsole nfs lockd sunrpc rtc sr_mod cdrom sg applesmc snd_hda_codec_idt input_polldev coretemp i2c_i801 snd_hda_intel snd_hda_codec snd_pcm snd_timer sky2 snd snd_page_alloc
Apr  9 17:56:14 mini Pid: 12837, comm: coriander Not tainted 3.4.0-rc2 #3
Apr  9 17:56:14 mini Call Trace:
Apr  9 17:56:14 mini [<c10219e4>] warn_slowpath_common+0x65/0x7a
Apr  9 17:56:14 mini [<c1111b32>] ? check_sync+0x2e4/0x508
Apr  9 17:56:14 mini [<c1021a5d>] warn_slowpath_fmt+0x26/0x2a
Apr  9 17:56:14 mini [<c1111b32>] check_sync+0x2e4/0x508
Apr  9 17:56:14 mini [<c1286c83>] ? _raw_spin_lock_irqsave+0x35/0x3e
Apr  9 17:56:14 mini [<c1111d9d>] debug_dma_sync_single_range_for_device+0x47/0x49
Apr  9 17:56:14 mini [<c1286c83>] ? _raw_spin_lock_irqsave+0x35/0x3e
Apr  9 17:56:14 mini [<f8aa83c9>] ohci_queue_iso+0x3af/0x59c [firewire_ohci]
Apr  9 17:56:14 mini [<c1006b28>] ? text_poke_smp_batch+0x37/0x37
Apr  9 17:56:14 mini [<f82f0089>] fw_iso_context_queue+0xe/0x13 [firewire_core]
Apr  9 17:56:14 mini [<f82ede19>] ioctl_queue_iso+0x269/0x2ef
Apr  9 17:56:14 mini [<c10549df>] ? lock_release_non_nested+0x88/0x245
Apr  9 17:56:14 mini [<c107faf6>] ? might_fault+0x42/0x7c
Apr  9 17:56:14 mini [<c107faf6>] ? might_fault+0x42/0x7c
Apr  9 17:56:14 mini [<c110703e>] ? _copy_from_user+0x39/0x4d
Apr  9 17:56:14 mini [<f82ee6d5>] fw_device_op_ioctl+0xa1/0xcc [firewire_core]
Apr  9 17:56:14 mini [<f82ee634>] ? ioctl_get_info+0x186/0x186 [firewire_core]
Apr  9 17:56:14 mini [<c109f025>] do_vfs_ioctl+0x47d/0x4b3
Apr  9 17:56:14 mini [<c10939fc>] ? fget_light+0x4c/0xd0
Apr  9 17:56:14 mini [<c109f089>] sys_ioctl+0x2e/0x49
Apr  9 17:56:14 mini [<c1287b90>] sysenter_do_call+0x12/0x36
Apr  9 17:56:14 mini ---[ end trace 09babbb7695bf21b ]---
Apr  9 17:56:14 mini Mapped at:
Apr  9 17:56:14 mini [<c11127cb>] debug_dma_map_page+0x4e/0x106
Apr  9 17:56:14 mini [<f82f050b>] fw_iso_buffer_init+0xbf/0x1e8 [firewire_core]
Apr  9 17:56:14 mini [<f82ed0d2>] fw_device_op_mmap+0x80/0xaf [firewire_core]
Apr  9 17:56:14 mini [<c1085201>] mmap_region+0x1c9/0x37b
Apr  9 17:56:14 mini [<c10855e7>] do_mmap_pgoff+0x234/0x27a

This code in fw_device_op_mmap...

if (vma->vm_flags & VM_WRITE)
direction = DMA_TO_DEVICE;
else
direction = DMA_FROM_DEVICE;

...is of course bogus.  Looks like we need to split fw_iso_buffer_init
into an allocation part (to be called in fw_device_op_mmap) and a DMA
mapping part (to be called in fw_device_op_mmap or in
ioctl_create_iso_context, whichever of the two is called last, so
that it is known whether the buffer is going to be used for reception
or transmission).

firewire_ohci : Register access failure - please notifylinux1394-devel< at >lists.sf.net

Anael — 2012-04-03T10:14:12

Hello,

I use Ubuntu 10.10 on a laptop dell latitude e5520.
When I take to hibernate the computer, and then I reboot it, appears an 
error :


uname -a  :

I attach to the email a cat of the syslog on the reboot time of the 
machine (going out of hibernation).

What could I do in order to help you to debug this problem ?

Regards,
Anael
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[PATCH] firewire: use module_pci_driver

Axel Lin — 2012-04-03T02:07:01

This patch converts the drivers in drivers/firewire/* to use module_pci_driver()
macro which makes the code smaller and a bit simpler.

Signed-off-by: Axel Lin <axel.lin< at >gmail.com>
Cc: Kristian Hoegsberg <krh< at >bitplanet.net>
---
 drivers/firewire/nosy.c |   20 ++++----------------
 drivers/firewire/ohci.c |   15 ++-------------
 2 files changed, 6 insertions(+), 29 deletions(-)

diff --git a/drivers/firewire/nosy.c b/drivers/firewire/nosy.c
index a7c4422..4ebfb22 100644
--- a/drivers/firewire/nosy.c
+++ b/drivers/firewire/nosy.c
< at >< at > -693,6 +693,8 < at >< at > static struct pci_device_id pci_table[] __devinitdata = {
 { }/* Terminating entry */
 };
 
+MODULE_DEVICE_TABLE(pci, pci_table);
+
 static struct pci_driver lynx_pci_driver = {
 .name =driver_name,
 .id_table =pci_table,
< at >< at > -700,22 +702,8 < at >< at > static struct pci_driver lynx_pci_driver = {
 .remove =remove_card,
 };
 
+module_pci_driver(lynx_pci_driver);
+
 MODULE_AUTHOR("Kristian Hoegsberg");
 MODULE_DESCRIPTION("Snoop mode driver for TI pcilynx 1394 controllers");
 MODULE_LICENSE("GPL");
-MODULE_DEVICE_TABLE(pci, pci_table);
-
-static int __init nosy_init(void)
-{
-return pci_register_driver(&lynx_pci_driver);
-}
-
-static void __exit nosy_cleanup(void)
-{
-pci_unregister_driver(&lynx_pci_driver);
-
-pr_info("Unloaded %s\n", driver_name);
-}
-
-module_init(nosy_init);
-module_exit(nosy_cleanup);
diff --git a/drivers/firewire/ohci.c b/drivers/firewire/ohci.c
index 2b54600..67c8d27 100644
--- a/drivers/firewire/ohci.c
+++ b/drivers/firewire/ohci.c
< at >< at > -3789,6 +3789,8 < at >< at > static struct pci_driver fw_ohci_pci_driver = {
 #endif
 };
 
+module_pci_driver(fw_ohci_pci_driver);
+
 MODULE_AUTHOR("Kristian Hoegsberg <krh< at >bitplanet.net>");
 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
 MODULE_LICENSE("GPL");
< at >< at > -3797,16 +3799,3 < at >< at > MODULE_LICENSE("GPL");
 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
 MODULE_ALIAS("ohci1394");
 #endif
-
-static int __init fw_ohci_init(void)
-{
-return pci_register_driver(&fw_ohci_pci_driver);
-}
-
-static void __exit fw_ohci_cleanup(void)
-{
-pci_unregister_driver(&fw_ohci_pci_driver);
-}
-
-module_init(fw_ohci_init);
-module_exit(fw_ohci_cleanup);

[PATCH] firewire: ohci: handle register access failure in SClk domain

Stefan Richter — 2012-04-01T22:57:47

One of the changes from OHCI-1394 v1.0 to v1.1 is that the PHY's SClk
signal may sometimes not be present during normal operation, and
accesses to certain registers fail then.  See OHCI-1394 v1.1 sections
1.4.1, 4., and 6.1.

The specification does not tell us though how to recover from this
condition.

This patch adds a check for this condition at each and every register
access within the SClk domain.  If the access failure is encountered,
the access is retried 20 times in a busy loop in atomic contexts, or
with 50 ms period (i.e. 1 second total retry time) in process contexts.
If the failure persists, the error is passed up to higher layers.  For
example, if loss of SClk persists when the controller is initialized or
is woken up in PM resume, the controller is not enabled and the
pci_probe or resume fails.

Since some of the accesses are in performance sensitive paths, notably
cycleTimer access in the interrupt handler, this patch should perhaps
be followed up by an optimization for OHCI 1.0 controllers and maybe
some known good OHCI 1.1 controllers which don't need the regAccessFail
check, to skip the expensive MMIOs on them.

regAccessFail has been seen with the following devices:

Texas Instruments PCIxx21 FireWire + CardBus + flash memory card
controller in a Toshiba Satellite:
https://bugzilla.redhat.com/show_bug.cgi?id=608544

O2 Micro FireWire + flash memory card controller in various Dell
laptops:
https://bugs.launchpad.net/ubuntu/+source/linux/+bug/801719
https://bugs.launchpad.net/ubuntu/+source/linux/+bug/881688
http://marc.info/?l=linux1394-devel&m=132309283531423
http://marc.info/?l=linux1394-devel&m=132368567907469
and several more reports.

Pinnacle MovieBoard:
http://git.kernel.org/?p=linux/kernel/git/torvalds/linux.git;a=commit;h=7f7e37115a8b
http://marc.info/?l=linux1394-devel&m=130714243325962

I don't have access to TI PCIxx21 and O2 Micro, hence tested this only
on several good controllers which never raise regAccessFail and on the
MovieBoard.  In case of the latter, the driver now detects the condition
as intended but still end up in a lock-up due to an interrupt storm or
even in a panic when SClk loss happens; so we need to keep the MovieBoard
disabled for now.

Tests on an affected Toshiba or Dell laptop would be much appreciated.
My hope is that their PM resume problem is fixed by the access retries
with pauses until SClk is on in ohci_enable.

Cc: Ming Lei <ming.lei< at >canonical.com>
Reported-by: Bjørn Forbord <bforbord< at >broadpark.no>
Reported-by: Joel Bourrigaud <joel< at >bourrigaud.info>
Reported-by: Klaus Pedersen <projectu< at >gmail.com>
Reported-by: Marc Legris <marc.legris< at >canonical.com>
Reported-by: Michael Heutzwer
Reported-by: Nikita Kitaev <nikitakit< at >gmail.com>
Reported-by: Nils Cant <nils< at >krash.be>
Reported-by: Robrecht Dewaele <robrecht.dewaele< at >gmail.com>
Reported-by: Steve Kroon <kroon< at >sun.ac.za>
Reported-by: Vianney <vidac2000< at >yahoo.fr>
Signed-off-by: Stefan Richter <stefanr< at >s5r6.in-berlin.de>
---
 drivers/firewire/core-card.c        |   13 -
 drivers/firewire/core-cdev.c        |    4 
 drivers/firewire/core-iso.c         |    4 
 drivers/firewire/core-transaction.c |   26 +-
 drivers/firewire/core.h             |    6 
 drivers/firewire/net.c              |    4 
 drivers/firewire/ohci.c             |  459 ++++++++++++++++++++--------
 drivers/firewire/ohci.h             |   47 ++-
 include/linux/firewire.h            |    2 
 9 files changed, 385 insertions(+), 180 deletions(-)

--- a/drivers/firewire/core-card.c
+++ b/drivers/firewire/core-card.c
< at >< at > -607,10 +607,7 < at >< at > static void dummy_send_request(struct fw
 packet->callback(packet, card, RCODE_CANCELLED);
 }
 
-static void dummy_send_response(struct fw_card *card, struct fw_packet *packet)
-{
-packet->callback(packet, card, RCODE_CANCELLED);
-}
+#define dummy_send_response dummy_send_request
 
 static int dummy_cancel_packet(struct fw_card *card, struct fw_packet *packet)
 {
< at >< at > -646,15 +643,13 < at >< at > static int dummy_queue_iso(struct fw_iso
 return -ENODEV;
 }
 
-static void dummy_flush_queue_iso(struct fw_iso_context *ctx)
-{
-}
-
-static int dummy_flush_iso_completions(struct fw_iso_context *ctx)
+static int dummy_flush_queue_iso(struct fw_iso_context *ctx)
 {
 return -ENODEV;
 }
 
+#define dummy_flush_iso_completions dummy_flush_queue_iso
+
 static const struct fw_card_driver dummy_driver_template = {
 .read_phy_reg= dummy_read_phy_reg,
 .update_phy_reg= dummy_update_phy_reg,
--- a/drivers/firewire/core-cdev.c
+++ b/drivers/firewire/core-cdev.c
< at >< at > -1185,11 +1185,11 < at >< at > static int ioctl_get_cycle_timer2(struct
 struct fw_card *card = client->device->card;
 struct timespec ts = {0, 0};
 u32 cycle_time;
-int ret = 0;
+int ret;
 
 local_irq_disable();
 
-cycle_time = card->driver->read_csr(card, CSR_CYCLE_TIME);
+ret = card->driver->read_csr(card, CSR_CYCLE_TIME, &cycle_time);
 
 switch (a->clk_id) {
 case CLOCK_REALTIME:      getnstimeofday(&ts);                   break;
--- a/drivers/firewire/core-iso.c
+++ b/drivers/firewire/core-iso.c
< at >< at > -186,9 +186,9 < at >< at > int fw_iso_context_queue(struct fw_iso_c
 }
 EXPORT_SYMBOL(fw_iso_context_queue);
 
-void fw_iso_context_queue_flush(struct fw_iso_context *ctx)
+int fw_iso_context_queue_flush(struct fw_iso_context *ctx)
 {
-ctx->card->driver->flush_queue_iso(ctx);
+return ctx->card->driver->flush_queue_iso(ctx);
 }
 EXPORT_SYMBOL(fw_iso_context_queue_flush);
 
--- a/drivers/firewire/core-transaction.c
+++ b/drivers/firewire/core-transaction.c
< at >< at > -1073,20 +1073,28 < at >< at > static void handle_registers(struct fw_c
 case CSR_CYCLE_TIME:
 case CSR_BUS_TIME:
 case CSR_BUSY_TIMEOUT:
-if (tcode == TCODE_READ_QUADLET_REQUEST)
-*data = cpu_to_be32(card->driver->read_csr(card, reg));
-else if (tcode == TCODE_WRITE_QUADLET_REQUEST)
-card->driver->write_csr(card, reg, be32_to_cpu(*data));
-else
+if (tcode == TCODE_READ_QUADLET_REQUEST) {
+if (card->driver->read_csr(card, reg, payload) < 0)
+rcode = RCODE_CONFLICT_ERROR;
+else
+cpu_to_be32s(payload);
+} else if (tcode == TCODE_WRITE_QUADLET_REQUEST) {
+if (card->driver->write_csr(card, reg,
+    be32_to_cpu(*data)) < 0)
+rcode = RCODE_CONFLICT_ERROR;
+} else {
 rcode = RCODE_TYPE_ERROR;
+}
 break;
 
 case CSR_RESET_START:
-if (tcode == TCODE_WRITE_QUADLET_REQUEST)
-card->driver->write_csr(card, CSR_STATE_CLEAR,
-CSR_STATE_BIT_ABDICATE);
-else
+if (tcode == TCODE_WRITE_QUADLET_REQUEST) {
+if (card->driver->write_csr(card, CSR_STATE_CLEAR,
+    CSR_STATE_BIT_ABDICATE) < 0)
+rcode = RCODE_CONFLICT_ERROR;
+} else {
 rcode = RCODE_TYPE_ERROR;
+}
 break;
 
 case CSR_SPLIT_TIMEOUT_HI:
--- a/drivers/firewire/core.h
+++ b/drivers/firewire/core.h
< at >< at > -86,8 +86,8 < at >< at > struct fw_card_driver {
 int (*enable_phys_dma)(struct fw_card *card,
        int node_id, int generation);
 
-u32 (*read_csr)(struct fw_card *card, int csr_offset);
-void (*write_csr)(struct fw_card *card, int csr_offset, u32 value);
+int (*read_csr)(struct fw_card *card, int csr_offset, u32 *value);
+int (*write_csr)(struct fw_card *card, int csr_offset, u32 value);
 
 struct fw_iso_context *
 (*allocate_iso_context)(struct fw_card *card,
< at >< at > -104,7 +104,7 < at >< at > struct fw_card_driver {
  struct fw_iso_buffer *buffer,
  unsigned long payload);
 
-void (*flush_queue_iso)(struct fw_iso_context *ctx);
+int (*flush_queue_iso)(struct fw_iso_context *ctx);
 
 int (*flush_iso_completions)(struct fw_iso_context *ctx);
 
--- a/drivers/firewire/net.c
+++ b/drivers/firewire/net.c
< at >< at > -880,8 +880,8 < at >< at > static void fwnet_receive_broadcast(stru
 spin_unlock_irqrestore(&dev->lock, flags);
 
 if (retval >= 0)
-fw_iso_context_queue_flush(dev->broadcast_rcv_context);
-else
+retval = fw_iso_context_queue_flush(dev->broadcast_rcv_context);
+if (retval < 0)
 dev_err(&dev->netdev->dev, "requeue failed\n");
 }
 
--- a/drivers/firewire/ohci.c
+++ b/drivers/firewire/ohci.c
< at >< at > -202,6 +202,7 < at >< at > struct fw_ohci {
  */
 spinlock_t lock;
 
+spinlock_t sclk_domain_reg_lock;
 struct mutex phy_reg_mutex;
 
 void *misc_buffer;
< at >< at > -360,7 +361,7 < at >< at > static void log_irqs(struct fw_ohci *ohc
 return;
 
 dev_notice(ohci->card.device,
-    "IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
+    "IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
     evt & OHCI1394_selfIDComplete? " selfID": "",
     evt & OHCI1394_RQPkt? " AR_req": "",
     evt & OHCI1394_RSPkt? " AR_resp": "",
< at >< at > -372,7 +373,6 < at >< at > static void log_irqs(struct fw_ohci *ohc
     evt & OHCI1394_cycleTooLong? " cycleTooLong": "",
     evt & OHCI1394_cycle64Seconds? " cycle64Seconds": "",
     evt & OHCI1394_cycleInconsistent? " cycleInconsistent": "",
-    evt & OHCI1394_regAccessFail? " regAccessFail": "",
     evt & OHCI1394_unrecoverableError? " unrecoverableError": "",
     evt & OHCI1394_busReset? " busReset": "",
     evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
< at >< at > -380,8 +380,7 < at >< at > static void log_irqs(struct fw_ohci *ohc
     OHCI1394_respTxComplete | OHCI1394_isochRx |
     OHCI1394_isochTx | OHCI1394_postedWriteErr |
     OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
-    OHCI1394_cycleInconsistent |
-    OHCI1394_regAccessFail | OHCI1394_busReset)
+    OHCI1394_cycleInconsistent | OHCI1394_busReset)
 ? " ?": "");
 }
 
< at >< at > -520,14 +519,14 < at >< at > static void log_ar_at_event(struct fw_oh
 }
 }
 
-static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
+static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
 {
-writel(data, ohci->registers + offset);
+return readl(ohci->registers + offset);
 }
 
-static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
+static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
 {
-return readl(ohci->registers + offset);
+writel(data, ohci->registers + offset);
 }
 
 static inline void flush_writes(const struct fw_ohci *ohci)
< at >< at > -536,6 +535,82 < at >< at > static inline void flush_writes(const st
 reg_read(ohci, OHCI1394_Version);
 }
 
+/* caller must hold sclk_domain_reg_lock */
+static int check_reg_access_fail(const struct fw_ohci *ohci)
+{
+u32 reg = reg_read(ohci, OHCI1394_IntEventSet);
+
+if (!~reg)
+return -ENODEV; /* Card was ejected. */
+
+if (reg & OHCI1394_regAccessFail) {
+reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_regAccessFail);
+/* Clear the bit before any other reg_write in SCLK domain. */
+mmiowb();
+return -EAGAIN;
+}
+
+return 0;
+}
+
+static int reg_rw_sclk(struct fw_ohci *ohci, int offset, u32 *data,
+       bool can_sleep, bool read)
+{
+unsigned long flags;
+int i, ret;
+
+for (i = 0; ; i++) {
+spin_lock_irqsave(&ohci->sclk_domain_reg_lock, flags);
+if (read)
+*data = reg_read(ohci, offset);
+else
+reg_write(ohci, offset, *data);
+ret = check_reg_access_fail(ohci);
+spin_unlock_irqrestore(&ohci->sclk_domain_reg_lock, flags);
+
+if (ret != -EAGAIN)
+return ret;
+if (i == 20)
+break;
+if (can_sleep)
+msleep(50);
+}
+dev_err(ohci->card.device, "SClk is off, cannot %s register 0x%03x\n",
+read ? "read" : "write", offset);
+
+return ret;
+}
+
+/* accessors for registers in SCLK domain, for use in atomic contexts */
+
+static int reg_read_sclk(struct fw_ohci *ohci, int offset, u32 *data)
+{
+return reg_rw_sclk(ohci, offset, data, false, true);
+}
+
+static int reg_write_sclk(struct fw_ohci *ohci, int offset, u32 data)
+{
+return reg_rw_sclk(ohci, offset, &data, false, false);
+}
+
+static int reg_write_sclk_flush(struct fw_ohci *ohci, int offset, u32 data)
+{
+/* Just for documentation. reg_rw_sclk() implies flush_write(). */
+return reg_rw_sclk(ohci, offset, &data, false, false);
+}
+
+/* accessors for registers in SCLK domain, for use in process contexts */
+
+static int reg_read_sclk_wait(struct fw_ohci *ohci, int offset, u32 *data)
+{
+return reg_rw_sclk(ohci, offset, data, true, true);
+}
+
+static int reg_write_sclk_wait(struct fw_ohci *ohci, int offset, u32 data)
+{
+return reg_rw_sclk(ohci, offset, &data, true, false);
+}
+
 /*
  * Beware!  read_phy_reg(), write_phy_reg(), update_phy_reg(), and
  * read_paged_phy_reg() require the caller to hold ohci->phy_reg_mutex.
< at >< at > -545,13 +620,16 < at >< at > static inline void flush_writes(const st
 static int read_phy_reg(struct fw_ohci *ohci, int addr)
 {
 u32 val;
-int i;
+int i, ret;
 
-reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
+ret = reg_write_sclk_wait(ohci, OHCI1394_PhyControl,
+  OHCI1394_PhyControl_Read(addr));
+if (ret < 0)
+return ret;
 for (i = 0; i < 3 + 100; i++) {
-val = reg_read(ohci, OHCI1394_PhyControl);
-if (!~val)
-return -ENODEV; /* Card was ejected. */
+ret = reg_read_sclk_wait(ohci, OHCI1394_PhyControl, &val);
+if (ret < 0)
+return ret;
 
 if (val & OHCI1394_PhyControl_ReadDone)
 return OHCI1394_PhyControl_ReadData(val);
< at >< at > -568,16 +646,18 < at >< at > static int read_phy_reg(struct fw_ohci *
 return -EBUSY;
 }
 
-static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
+static int write_phy_reg(struct fw_ohci *ohci, int addr, u32 val)
 {
-int i;
+int i, ret;
 
-reg_write(ohci, OHCI1394_PhyControl,
-  OHCI1394_PhyControl_Write(addr, val));
+ret = reg_write_sclk_wait(ohci, OHCI1394_PhyControl,
+  OHCI1394_PhyControl_Write(addr, val));
+if (ret < 0)
+return ret;
 for (i = 0; i < 3 + 100; i++) {
-val = reg_read(ohci, OHCI1394_PhyControl);
-if (!~val)
-return -ENODEV; /* Card was ejected. */
+ret = reg_read_sclk_wait(ohci, OHCI1394_PhyControl, &val);
+if (ret < 0)
+return ret;
 
 if (!(val & OHCI1394_PhyControl_WritePending))
 return 0;
< at >< at > -1207,13 +1287,22 < at >< at > static struct descriptor *context_get_de
 static void context_run(struct context *ctx, u32 extra)
 {
 struct fw_ohci *ohci = ctx->ohci;
+int regs_base = ctx->regs;
 
-reg_write(ohci, COMMAND_PTR(ctx->regs),
+reg_write(ohci, COMMAND_PTR(regs_base),
   le32_to_cpu(ctx->last->branch_address));
-reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
-reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
+
+if (regs_base < OHCI1394_IsoRcvContextBase(0)) {
+reg_write(ohci, CONTROL_CLEAR(regs_base), ~0);
+reg_write(ohci, CONTROL_SET(regs_base), CONTEXT_RUN | extra);
+flush_writes(ohci);
+} else {
+if (reg_write_sclk(ohci, CONTROL_CLEAR(regs_base), ~0) == 0)
+reg_write_sclk_flush(ohci, CONTROL_SET(regs_base),
+     CONTEXT_RUN | extra);
+/* FIXME handle regAccessFail? */
+}
 ctx->running = true;
-flush_writes(ohci);
 }
 
 static void context_append(struct context *ctx,
< at >< at > -1234,17 +1323,30 < at >< at > static void context_append(struct contex
 static void context_stop(struct context *ctx)
 {
 struct fw_ohci *ohci = ctx->ohci;
+int i, ret, regs_base = ctx->regs;
 u32 reg;
-int i;
 
-reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
+if (regs_base < OHCI1394_IsoRcvContextBase(0))
+reg_write(ohci, CONTROL_CLEAR(regs_base), CONTEXT_RUN);
+else
+reg_write_sclk(ohci, CONTROL_CLEAR(regs_base), CONTEXT_RUN);
 ctx->running = false;
 
 for (i = 0; i < 1000; i++) {
-reg = reg_read(ohci, CONTROL_SET(ctx->regs));
+if (regs_base < OHCI1394_IsoRcvContextBase(0)) {
+reg = reg_read(ohci, CONTROL_SET(regs_base));
+if (!~reg)
+return;
+} else {
+ret = reg_read_sclk(ohci, CONTROL_SET(regs_base), &reg);
+if (ret == -ENODEV)
+return;
+if (ret < 0)
+reg = ~0;
+}
+
 if ((reg & CONTEXT_ACTIVE) == 0)
 return;
-
 if (i)
 udelay(10);
 }
< at >< at > -1522,7 +1624,8 < at >< at > static void handle_local_lock(struct fw_
 struct fw_packet response;
 int tcode, length, ext_tcode, sel, try;
 __be32 *payload, lock_old;
-u32 lock_arg, lock_data;
+u32 lock_arg, lock_data, reg;
+unsigned long flags;
 
 tcode = HEADER_GET_TCODE(packet->header[0]);
 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
< at >< at > -1542,24 +1645,35 < at >< at > static void handle_local_lock(struct fw_
 goto out;
 }
 
+spin_lock_irqsave(&ohci->sclk_domain_reg_lock, flags);
+
 sel = (csr - CSR_BUS_MANAGER_ID) / 4;
 reg_write(ohci, OHCI1394_CSRData, lock_data);
 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
 reg_write(ohci, OHCI1394_CSRControl, sel);
 
-for (try = 0; try < 20; try++)
-if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
-lock_old = cpu_to_be32(reg_read(ohci,
-OHCI1394_CSRData));
+for (try = 0; try < 20; try++) {
+reg = reg_read(ohci, OHCI1394_CSRControl);
+if (check_reg_access_fail(ohci))
+break;
+
+if (reg & OHCI1394_CSRControl_csrDone) {
+lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData));
+if (check_reg_access_fail(ohci))
+break;
+
 fw_fill_response(&response, packet->header,
  RCODE_COMPLETE,
  &lock_old, sizeof(lock_old));
-goto out;
+goto out_unlock;
 }
+}
 
 dev_err(ohci->card.device, "swap not done (CSR lock timeout)\n");
 fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
 
+ out_unlock:
+spin_unlock_irqrestore(&ohci->sclk_domain_reg_lock, flags);
  out:
 fw_core_handle_response(&ohci->card, &response);
 }
< at >< at > -1630,7 +1744,10 < at >< at > static void detect_dead_context(struct f
 {
 u32 ctl;
 
-ctl = reg_read(ohci, CONTROL_SET(regs));
+if (regs < OHCI1394_IsoRcvContextBase(0))
+ctl = reg_read(ohci, CONTROL_SET(regs));
+else if (reg_read_sclk(ohci, CONTROL_SET(regs), &ctl) < 0)
+ctl = 0;
 if (ctl & CONTEXT_DEAD)
 dev_err(ohci->card.device,
 "DMA context %s has stopped, error code: %s\n",
< at >< at > -1687,7 +1804,7 < at >< at > static u32 cycle_timer_ticks(u32 cycle_t
  * error.  (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
  * execute, so we have enough precision to compute the ratio of the differences.)
  */
-static u32 get_cycle_time(struct fw_ohci *ohci)
+static u32 __get_cycle_time(struct fw_ohci *ohci)
 {
 u32 c0, c1, c2;
 u32 t0, t1, t2;
< at >< at > -1717,20 +1834,47 < at >< at > static u32 get_cycle_time(struct fw_ohci
 return c2;
 }
 
+static int get_cycle_time(struct fw_ohci *ohci, u32 *value)
+{
+unsigned long flags;
+int i, ret;
+
+for (i = 0; i < 20; i++) {
+spin_lock_irqsave(&ohci->sclk_domain_reg_lock, flags);
+*value = __get_cycle_time(ohci);
+ret = check_reg_access_fail(ohci);
+spin_unlock_irqrestore(&ohci->sclk_domain_reg_lock, flags);
+
+if (ret != -EAGAIN)
+return ret;
+}
+dev_err(ohci->card.device, "SClk is off, cannot read cycle timer\n");
+
+return ret;
+}
+
 /*
  * This function has to be called at least every 64 seconds.  The bus_time
  * field stores not only the upper 25 bits of the BUS_TIME register but also
  * the most significant bit of the cycle timer in bit 6 so that we can detect
  * changes in this bit.
  */
-static u32 update_bus_time(struct fw_ohci *ohci)
+static int update_bus_time(struct fw_ohci *ohci, u32 *value)
 {
-u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
+u32 cycle_time, cycle_time_seconds;
+int ret;
+
+ret = get_cycle_time(ohci, &cycle_time);
+if (ret < 0)
+return ret;
 
+cycle_time_seconds = cycle_time >> 25;
 if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
 ohci->bus_time += 0x40;
+if (value)
+*value = ohci->bus_time | cycle_time_seconds;
 
-return ohci->bus_time | cycle_time_seconds;
+return 0;
 }
 
 static int get_status_for_port(struct fw_ohci *ohci, int port_index)
< at >< at > -1778,11 +1922,13 < at >< at > static int get_self_id_pos(struct fw_ohc
  */
 static int find_and_insert_self_id(struct fw_ohci *ohci, int self_id_count)
 {
-int reg, i, pos, status;
+int ret, i, pos, status;
 /* link active 1, speed 3, bridge 0, contender 1, more packets 0 */
-u32 self_id = 0x8040c800;
+u32 reg, self_id = 0x8040c800;
 
-reg = reg_read(ohci, OHCI1394_NodeID);
+ret = reg_read_sclk_wait(ohci, OHCI1394_NodeID, &reg);
+if (ret < 0)
+return ret;
 if (!(reg & OHCI1394_NodeID_idValid)) {
 dev_notice(ohci->card.device,
    "node ID not valid, new bus reset in progress\n");
< at >< at > -1829,7 +1975,8 < at >< at > static void bus_reset_work(struct work_s
 dma_addr_t free_rom_bus = 0;
 bool is_new_root;
 
-reg = reg_read(ohci, OHCI1394_NodeID);
+if (reg_read_sclk_wait(ohci, OHCI1394_NodeID, &reg) < 0)
+return;
 if (!(reg & OHCI1394_NodeID_idValid)) {
 dev_notice(ohci->card.device,
    "node ID not valid, new bus reset in progress\n");
< at >< at > -1844,8 +1991,8 < at >< at > static void bus_reset_work(struct work_s
 
 is_new_root = (reg & OHCI1394_NodeID_root) != 0;
 if (!(ohci->is_root && is_new_root))
-reg_write(ohci, OHCI1394_LinkControlSet,
-  OHCI1394_LinkControl_cycleMaster);
+reg_write_sclk_wait(ohci, OHCI1394_LinkControlSet,
+    OHCI1394_LinkControl_cycleMaster);
 ohci->is_root = is_new_root;
 
 reg = reg_read(ohci, OHCI1394_SelfIDCount);
< at >< at > -1987,8 +2134,8 < at >< at > static void bus_reset_work(struct work_s
 }
 
 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
-reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
-reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
+reg_write_sclk(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
+reg_write_sclk(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
 #endif
 
 spin_unlock_irqrestore(&ohci->lock, flags);
< at >< at > -2063,9 +2210,6 < at >< at > static irqreturn_t irq_handler(int irq,
 }
 }
 
-if (unlikely(event & OHCI1394_regAccessFail))
-dev_err(ohci->card.device, "register access failure\n");
-
 if (unlikely(event & OHCI1394_postedWriteErr)) {
 reg_read(ohci, OHCI1394_PostedWriteAddressHi);
 reg_read(ohci, OHCI1394_PostedWriteAddressLo);
< at >< at > -2079,8 +2223,8 < at >< at > static irqreturn_t irq_handler(int irq,
 if (printk_ratelimit())
 dev_notice(ohci->card.device,
    "isochronous cycle too long\n");
-reg_write(ohci, OHCI1394_LinkControlSet,
-  OHCI1394_LinkControl_cycleMaster);
+reg_write_sclk(ohci, OHCI1394_LinkControlSet,
+       OHCI1394_LinkControl_cycleMaster);
 }
 
 if (unlikely(event & OHCI1394_cycleInconsistent)) {
< at >< at > -2100,7 +2244,7 < at >< at > static irqreturn_t irq_handler(int irq,
 
 if (event & OHCI1394_cycle64Seconds) {
 spin_lock(&ohci->lock);
-update_bus_time(ohci);
+update_bus_time(ohci, NULL);
 spin_unlock(&ohci->lock);
 } else
 flush_writes(ohci);
< at >< at > -2215,7 +2359,7 < at >< at > static int ohci_enable(struct fw_card *c
 {
 struct fw_ohci *ohci = fw_ohci(card);
 struct pci_dev *dev = to_pci_dev(card->device);
-u32 lps, seconds, version, irqs;
+u32 lps, seconds, version, irqs, reg;
 int i, ret;
 
 if (software_reset(ohci)) {
< at >< at > -2246,6 +2390,7 < at >< at > static int ohci_enable(struct fw_card *c
 dev_err(card->device, "failed to set Link Power Status\n");
 return -EIO;
 }
+reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_regAccessFail);
 
 if (ohci->quirks & QUIRK_TI_SLLZ059) {
 ret = probe_tsb41ba3d(ohci);
< at >< at > -2261,9 +2406,11 < at >< at > static int ohci_enable(struct fw_card *c
   OHCI1394_HCControl_noByteSwapData);
 
 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
-reg_write(ohci, OHCI1394_LinkControlSet,
-  OHCI1394_LinkControl_cycleTimerEnable |
-  OHCI1394_LinkControl_cycleMaster);
+ret = reg_write_sclk_wait(ohci, OHCI1394_LinkControlSet,
+  OHCI1394_LinkControl_cycleTimerEnable |
+  OHCI1394_LinkControl_cycleMaster);
+if (ret < 0)
+return ret;
 
 reg_write(ohci, OHCI1394_ATRetries,
   OHCI1394_MAX_AT_REQ_RETRIES |
< at >< at > -2272,8 +2419,11 < at >< at > static int ohci_enable(struct fw_card *c
   (200 << 16));
 
 seconds = lower_32_bits(get_seconds());
-reg_write(ohci, OHCI1394_IsochronousCycleTimer, seconds << 25);
 ohci->bus_time = seconds & ~0x3f;
+ret = reg_write_sclk_wait(ohci, OHCI1394_IsochronousCycleTimer,
+  seconds << 25);
+if (ret < 0)
+return ret;
 
 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
 if (version >= OHCI_VERSION_1_1) {
< at >< at > -2283,9 +2433,16 < at >< at > static int ohci_enable(struct fw_card *c
 }
 
 /* Get implemented bits of the priority arbitration request counter. */
-reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
-ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
-reg_write(ohci, OHCI1394_FairnessControl, 0);
+ret = reg_write_sclk_wait(ohci, OHCI1394_FairnessControl, 0x3f);
+if (ret < 0)
+return ret;
+ret = reg_read_sclk_wait(ohci, OHCI1394_FairnessControl, &reg);
+if (ret < 0)
+return ret;
+ret = reg_write_sclk_wait(ohci, OHCI1394_FairnessControl, 0);
+if (ret < 0)
+return ret;
+ohci->pri_req_max = reg & 0x3f;
 card->priority_budget_implemented = ohci->pri_req_max != 0;
 
 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
< at >< at > -2345,24 +2502,20 < at >< at > static int ohci_enable(struct fw_card *c
   be32_to_cpu(ohci->next_config_rom[2]));
 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
 
-reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
+ret = reg_write_sclk_wait(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
+if (ret < 0)
+goto out;
 
 if (!(ohci->quirks & QUIRK_NO_MSI))
 pci_enable_msi(dev);
-if (request_irq(dev->irq, irq_handler,
-pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
-ohci_driver_name, ohci)) {
+ret = request_irq(dev->irq, irq_handler,
+  pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
+  ohci_driver_name, ohci);
+if (ret < 0) {
 dev_err(card->device, "failed to allocate interrupt %d\n",
 dev->irq);
 pci_disable_msi(dev);
-
-if (config_rom) {
-dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
-  ohci->next_config_rom,
-  ohci->next_config_rom_bus);
-ohci->next_config_rom = NULL;
-}
-return -EIO;
+goto out;
 }
 
 irqs =OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
< at >< at > -2370,7 +2523,6 < at >< at > static int ohci_enable(struct fw_card *c
 OHCI1394_isochTx | OHCI1394_isochRx |
 OHCI1394_postedWriteErr |
 OHCI1394_selfIDComplete |
-OHCI1394_regAccessFail |
 OHCI1394_cycle64Seconds |
 OHCI1394_cycleInconsistent |
 OHCI1394_unrecoverableError |
< at >< at > -2384,9 +2536,11 < at >< at > static int ohci_enable(struct fw_card *c
   OHCI1394_HCControl_linkEnable |
   OHCI1394_HCControl_BIBimageValid);
 
-reg_write(ohci, OHCI1394_LinkControlSet,
-  OHCI1394_LinkControl_rcvSelfID |
-  OHCI1394_LinkControl_rcvPhyPkt);
+ret = reg_write_sclk_wait(ohci, OHCI1394_LinkControlSet,
+  OHCI1394_LinkControl_rcvSelfID |
+  OHCI1394_LinkControl_rcvPhyPkt);
+if (ret < 0)
+goto out;
 
 ar_context_run(&ohci->ar_request_ctx);
 ar_context_run(&ohci->ar_response_ctx);
< at >< at > -2397,6 +2551,14 < at >< at > static int ohci_enable(struct fw_card *c
 fw_schedule_bus_reset(&ohci->card, false, true);
 
 return 0;
+ out:
+if (config_rom) {
+dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
+  ohci->next_config_rom,
+  ohci->next_config_rom_bus);
+ohci->next_config_rom = NULL;
+}
+return ret;
 }
 
 static int ohci_set_config_rom(struct fw_card *card,
< at >< at > -2537,7 +2699,7 < at >< at > static int ohci_enable_phys_dma(struct f
 #else
 struct fw_ohci *ohci = fw_ohci(card);
 unsigned long flags;
-int n, ret = 0;
+int n, ret;
 
 /*
  * FIXME:  Make sure this bitmask is cleared when we clear the busReset
< at >< at > -2558,11 +2720,11 < at >< at > static int ohci_enable_phys_dma(struct f
 
 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
 if (n < 32)
-reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
+ret = reg_write_sclk_flush(ohci, OHCI1394_PhyReqFilterLoSet,
+   1 << n);
 else
-reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
-
-flush_writes(ohci);
+ret = reg_write_sclk_flush(ohci, OHCI1394_PhyReqFilterHiSet,
+   1 << (n - 32));
  out:
 spin_unlock_irqrestore(&ohci->lock, flags);
 
< at >< at > -2570,31 +2732,37 < at >< at > static int ohci_enable_phys_dma(struct f
 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
 }
 
-static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
+static int ohci_read_csr(struct fw_card *card, int csr_offset, u32 *value)
 {
 struct fw_ohci *ohci = fw_ohci(card);
 unsigned long flags;
-u32 value;
+u32 tmp;
+int ret;
 
 switch (csr_offset) {
 case CSR_STATE_CLEAR:
 case CSR_STATE_SET:
-if (ohci->is_root &&
-    (reg_read(ohci, OHCI1394_LinkControlSet) &
-     OHCI1394_LinkControl_cycleMaster))
-value = CSR_STATE_BIT_CMSTR;
-else
-value = 0;
+if (ohci->is_root) {
+ret = reg_read_sclk(ohci, OHCI1394_LinkControlSet, &tmp);
+*value = tmp & OHCI1394_LinkControl_cycleMaster ?
+ CSR_STATE_BIT_CMSTR : 0;
+} else {
+ret = 0;
+*value = 0;
+}
 if (ohci->csr_state_setclear_abdicate)
-value |= CSR_STATE_BIT_ABDICATE;
-
-return value;
+*value |= CSR_STATE_BIT_ABDICATE;
+break;
 
 case CSR_NODE_IDS:
-return reg_read(ohci, OHCI1394_NodeID) << 16;
+ret = reg_read_sclk(ohci, OHCI1394_NodeID, &tmp);
+*value = tmp << 16;
+ret = 0;
+break;
 
 case CSR_CYCLE_TIME:
-return get_cycle_time(ohci);
+ret = get_cycle_time(ohci, value);
+break;
 
 case CSR_BUS_TIME:
 /*
< at >< at > -2603,66 +2771,75 < at >< at > static u32 ohci_read_csr(struct fw_card
  * better check here, too, if the bus time needs to be updated.
  */
 spin_lock_irqsave(&ohci->lock, flags);
-value = update_bus_time(ohci);
+ret = update_bus_time(ohci, value);
 spin_unlock_irqrestore(&ohci->lock, flags);
-return value;
+break;
 
 case CSR_BUSY_TIMEOUT:
-value = reg_read(ohci, OHCI1394_ATRetries);
-return (value >> 4) & 0x0ffff00f;
+*value = (reg_read(ohci, OHCI1394_ATRetries) >> 4) & 0x0ffff00f;
+ret = 0;
+break;
 
 case CSR_PRIORITY_BUDGET:
-return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
-(ohci->pri_req_max << 8);
+ret = reg_read_sclk(ohci, OHCI1394_FairnessControl, &tmp);
+*value = (tmp & 0x3f) | (ohci->pri_req_max << 8);
+break;
 
 default:
 WARN_ON(1);
-return 0;
+ret = -EINVAL;
+break;
 }
+
+return ret;
 }
 
-static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
+static int ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
 {
 struct fw_ohci *ohci = fw_ohci(card);
 unsigned long flags;
+int ret;
 
 switch (csr_offset) {
 case CSR_STATE_CLEAR:
-if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
-reg_write(ohci, OHCI1394_LinkControlClear,
-  OHCI1394_LinkControl_cycleMaster);
-flush_writes(ohci);
-}
-if (value & CSR_STATE_BIT_ABDICATE)
+if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root)
+ret = reg_write_sclk_flush(ohci,
+OHCI1394_LinkControlClear,
+OHCI1394_LinkControl_cycleMaster);
+else
+ret = 0;
+if (value & CSR_STATE_BIT_ABDICATE && ret == 0)
 ohci->csr_state_setclear_abdicate = false;
 break;
 
 case CSR_STATE_SET:
-if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
-reg_write(ohci, OHCI1394_LinkControlSet,
-  OHCI1394_LinkControl_cycleMaster);
-flush_writes(ohci);
-}
-if (value & CSR_STATE_BIT_ABDICATE)
+if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root)
+ret = reg_write_sclk_flush(ohci,
+OHCI1394_LinkControlSet,
+OHCI1394_LinkControl_cycleMaster);
+else
+ret = 0;
+if (value & CSR_STATE_BIT_ABDICATE && ret == 0)
 ohci->csr_state_setclear_abdicate = true;
 break;
 
 case CSR_NODE_IDS:
-reg_write(ohci, OHCI1394_NodeID, value >> 16);
-flush_writes(ohci);
+ret = reg_write_sclk_flush(ohci, OHCI1394_NodeID, value >> 16);
 break;
 
 case CSR_CYCLE_TIME:
-reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
-reg_write(ohci, OHCI1394_IntEventSet,
-  OHCI1394_cycleInconsistent);
-flush_writes(ohci);
+ret = reg_write_sclk_flush(ohci,
+OHCI1394_IsochronousCycleTimer, value);
+if (ret == 0)
+reg_write(ohci, OHCI1394_IntEventSet,
+  OHCI1394_cycleInconsistent);
 break;
 
 case CSR_BUS_TIME:
 spin_lock_irqsave(&ohci->lock, flags);
 ohci->bus_time = (ohci->bus_time & 0x7f) | (value & ~0x7f);
 spin_unlock_irqrestore(&ohci->lock, flags);
+ret = 0;
 break;
 
 case CSR_BUSY_TIMEOUT:
< at >< at > -2670,17 +2847,21 < at >< at > static void ohci_write_csr(struct fw_car
 ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
 reg_write(ohci, OHCI1394_ATRetries, value);
 flush_writes(ohci);
+ret = 0;
 break;
 
 case CSR_PRIORITY_BUDGET:
-reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
-flush_writes(ohci);
+ret = reg_write_sclk_flush(ohci, OHCI1394_FairnessControl,
+   value & 0x3f);
 break;
 
 default:
 WARN_ON(1);
+ret = -EINVAL;
 break;
 }
+
+return ret;
 }
 
 static void flush_iso_completions(struct iso_context *ctx)
< at >< at > -2872,16 +3053,23 < at >< at > static int handle_it_packet(struct conte
 return 1;
 }
 
-static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
+static int set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
 {
 u32 hi = channels >> 32, lo = channels;
+unsigned long flags;
+int ret;
 
+spin_lock_irqsave(&ohci->sclk_domain_reg_lock, flags);
 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
 reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
 reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
-mmiowb();
-ohci->mc_channels = channels;
+ret = check_reg_access_fail(ohci);
+if (ret == 0)
+ohci->mc_channels = channels;
+spin_unlock_irqrestore(&ohci->sclk_domain_reg_lock, flags);
+
+return ret;
 }
 
 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
< at >< at > -2956,12 +3144,16 < at >< at > static struct fw_iso_context *ohci_alloc
 goto out_with_header;
 
 if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL) {
-set_multichannel_mask(ohci, 0);
 ctx->mc_completed = 0;
+ret = set_multichannel_mask(ohci, 0);
+if (ret < 0)
+goto out_with_context;
 }
 
 return &ctx->base;
 
+ out_with_context:
+context_release(&ctx->context);
  out_with_header:
 free_page((unsigned long)ctx->header);
  out:
< at >< at > -3412,12 +3604,20 < at >< at > static int ohci_queue_iso(struct fw_iso_
 return ret;
 }
 
-static void ohci_flush_queue_iso(struct fw_iso_context *base)
+static int ohci_flush_queue_iso(struct fw_iso_context *base)
 {
 struct context *ctx =
 &container_of(base, struct iso_context, base)->context;
+int ret, regs_base = ctx->regs;
 
-reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
+if (regs_base < OHCI1394_IsoRcvContextBase(0)) {
+ret = 0;
+reg_write(ctx->ohci, CONTROL_SET(regs_base), CONTEXT_WAKE);
+} else {
+ret = reg_write_sclk(ctx->ohci, CONTROL_SET(regs_base),
+     CONTEXT_WAKE);
+}
+return ret;
 }
 
 static int ohci_flush_iso_completions(struct fw_iso_context *base)
< at >< at > -3539,6 +3739,7 < at >< at > static int __devinit pci_probe(struct pc
 pci_set_drvdata(dev, ohci);
 
 spin_lock_init(&ohci->lock);
+spin_lock_init(&ohci->sclk_domain_reg_lock);
 mutex_init(&ohci->phy_reg_mutex);
 
 INIT_WORK(&ohci->bus_reset_work, bus_reset_work);
--- a/drivers/firewire/ohci.h
+++ b/drivers/firewire/ohci.h
< at >< at > -6,9 +6,10 < at >< at >
 #define OHCI1394_Version                      0x000
 #define OHCI1394_GUID_ROM                     0x004
 #define OHCI1394_ATRetries                    0x008
-#define OHCI1394_CSRData                      0x00C
-#define OHCI1394_CSRCompareData               0x010
-#define OHCI1394_CSRControl                   0x014
+#define OHCI1394_CSRData                      0x00C/* SCLK domain */
+#define OHCI1394_CSRCompareData               0x010/* SCLK domain */
+#define OHCI1394_CSRControl                   0x014/* SCLK domain */
+#define  OHCI1394_CSRControl_csrDone0x80000000
 #define OHCI1394_ConfigROMhdr                 0x018
 #define OHCI1394_BusID                        0x01C
 #define OHCI1394_BusOptions                   0x020
< at >< at > -31,10 +32,10 < at >< at >
 #define OHCI1394_SelfIDBuffer                 0x064
 #define OHCI1394_SelfIDCount                  0x068
 #define  OHCI1394_SelfIDCount_selfIDError0x80000000
-#define OHCI1394_IRMultiChanMaskHiSet         0x070
-#define OHCI1394_IRMultiChanMaskHiClear       0x074
-#define OHCI1394_IRMultiChanMaskLoSet         0x078
-#define OHCI1394_IRMultiChanMaskLoClear       0x07C
+#define OHCI1394_IRMultiChanMaskHiSet         0x070/* SCLK domain */
+#define OHCI1394_IRMultiChanMaskHiClear       0x074/* SCLK domain */
+#define OHCI1394_IRMultiChanMaskLoSet         0x078/* SCLK domain */
+#define OHCI1394_IRMultiChanMaskLoClear       0x07C/* SCLK domain */
 #define OHCI1394_IntEventSet                  0x080
 #define OHCI1394_IntEventClear                0x084
 #define OHCI1394_IntMaskSet                   0x088
< at >< at > -50,34 +51,34 < at >< at >
 #define OHCI1394_InitialBandwidthAvailable    0x0B0
 #define OHCI1394_InitialChannelsAvailableHi   0x0B4
 #define OHCI1394_InitialChannelsAvailableLo   0x0B8
-#define OHCI1394_FairnessControl              0x0DC
-#define OHCI1394_LinkControlSet               0x0E0
-#define OHCI1394_LinkControlClear             0x0E4
+#define OHCI1394_FairnessControl              0x0DC/* SCLK domain */
+#define OHCI1394_LinkControlSet               0x0E0/* SCLK domain */
+#define OHCI1394_LinkControlClear             0x0E4/* SCLK domain */
 #define   OHCI1394_LinkControl_rcvSelfID(1 << 9)
 #define   OHCI1394_LinkControl_rcvPhyPkt(1 << 10)
 #define   OHCI1394_LinkControl_cycleTimerEnable(1 << 20)
 #define   OHCI1394_LinkControl_cycleMaster(1 << 21)
 #define   OHCI1394_LinkControl_cycleSource(1 << 22)
-#define OHCI1394_NodeID                       0x0E8
+#define OHCI1394_NodeID                       0x0E8/* SCLK domain */
 #define   OHCI1394_NodeID_idValid             0x80000000
 #define   OHCI1394_NodeID_root                0x40000000
 #define   OHCI1394_NodeID_nodeNumber          0x0000003f
 #define   OHCI1394_NodeID_busNumber           0x0000ffc0
-#define OHCI1394_PhyControl                   0x0EC
+#define OHCI1394_PhyControl                   0x0EC/* SCLK domain */
 #define   OHCI1394_PhyControl_Read(addr)(((addr) << 8) | 0x00008000)
 #define   OHCI1394_PhyControl_ReadDone0x80000000
 #define   OHCI1394_PhyControl_ReadData(r)(((r) & 0x00ff0000) >> 16)
 #define   OHCI1394_PhyControl_Write(addr, data)(((addr) << 8) | (data) | 0x00004000)
 #define   OHCI1394_PhyControl_WritePending0x00004000
-#define OHCI1394_IsochronousCycleTimer        0x0F0
-#define OHCI1394_AsReqFilterHiSet             0x100
-#define OHCI1394_AsReqFilterHiClear           0x104
-#define OHCI1394_AsReqFilterLoSet             0x108
-#define OHCI1394_AsReqFilterLoClear           0x10C
-#define OHCI1394_PhyReqFilterHiSet            0x110
-#define OHCI1394_PhyReqFilterHiClear          0x114
-#define OHCI1394_PhyReqFilterLoSet            0x118
-#define OHCI1394_PhyReqFilterLoClear          0x11C
+#define OHCI1394_IsochronousCycleTimer        0x0F0/* SCLK domain */
+#define OHCI1394_AsReqFilterHiSet             0x100/* SCLK domain */
+#define OHCI1394_AsReqFilterHiClear           0x104/* SCLK domain */
+#define OHCI1394_AsReqFilterLoSet             0x108/* SCLK domain */
+#define OHCI1394_AsReqFilterLoClear           0x10C/* SCLK domain */
+#define OHCI1394_PhyReqFilterHiSet            0x110/* SCLK domain */
+#define OHCI1394_PhyReqFilterHiClear          0x114/* SCLK domain */
+#define OHCI1394_PhyReqFilterLoSet            0x118/* SCLK domain */
+#define OHCI1394_PhyReqFilterLoClear          0x11C/* SCLK domain */
 #define OHCI1394_PhyUpperBound                0x120
 
 #define OHCI1394_AsReqTrContextBase           0x180
< at >< at > -108,8 +109,8 < at >< at >
 
 /* Isochronous receive registers */
 #define OHCI1394_IsoRcvContextBase(n)         (0x400 + 32 * (n))
-#define OHCI1394_IsoRcvContextControlSet(n)   (0x400 + 32 * (n))
-#define OHCI1394_IsoRcvContextControlClear(n) (0x404 + 32 * (n))
+#define OHCI1394_IsoRcvContextControlSet(n)   (0x400 + 32 * (n)) /* SCLK domain */
+#define OHCI1394_IsoRcvContextControlClear(n) (0x404 + 32 * (n)) /* SCLK domain */
 #define OHCI1394_IsoRcvCommandPtr(n)          (0x40C + 32 * (n))
 #define OHCI1394_IsoRcvContextMatch(n)        (0x410 + 32 * (n))
 
--- a/include/linux/firewire.h
+++ b/include/linux/firewire.h
< at >< at > -425,7 +425,7 < at >< at > int fw_iso_context_queue(struct fw_iso_c
  struct fw_iso_packet *packet,
  struct fw_iso_buffer *buffer,
  unsigned long payload);
-void fw_iso_context_queue_flush(struct fw_iso_context *ctx);
+int fw_iso_context_queue_flush(struct fw_iso_context *ctx);
 int fw_iso_context_flush_completions(struct fw_iso_context *ctx);
 int fw_iso_context_start(struct fw_iso_context *ctx,
  int cycle, int sync, int tags);

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Register access failure - please notify linux1394-devel< at >lists.sf.net

Robrecht Dewaele — 2012-03-24T11:41:21

Dear maintainers,

During boot I saw the following message, so I complied

[    8.654566] firewire_ohci: Register access failure - please notify 
linux1394-devel< at >lists.sf.net
[    8.654756] firewire_ohci: Added fw-ohci device 0000:09:00.0, OHCI 
v1.10, 8 IR + 8 IT contexts, quirks 0x10
[    8.654932] initcall fw_ohci_init+0x0/0x20 [firewire_ohci] returned 0 
after 50723 usecs

In attachment you can find the full dmesg log, the output of lspci -vv, 
and the output of lsmod.

I have a Dell Latitude 5420 laptop running arch linux, 64-bit:
Linux gerbil 3.2.12-1-ARCH #1 SMP PREEMPT Mon Mar 19 17:50:01 CET 2012 
x86_64 Intel(R) Core(TM) i3-2330M CPU < at > 2.20GHz GenuineIntel GNU/Linux


hth,
Robrecht Dewaele
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[PATCH 1/2] firewire: ohci: fix too-early completion of IRmultichannel buffers

Clemens Ladisch — 2012-03-12T20:45:47

handle_ir_buffer_fill() assumed that a completed descriptor would be
indicated by a non-zero transfer_status (as in most other descriptors).
However, this field is written by the controller as soon as (the end of)
the first packet has been written into the buffer.  As a consequence, if
we happen to run into such a descriptor when the interrupt handler is
executed after such a packet has completed, the descriptor would be
taken out of the list of active descriptors as soon as the buffer had
been partially filled, so the event for the buffer being completely
filled would never be sent.

To fix this, handle descriptors only when they have been completely
filled, i.e., when res_count == 0.  (This also matches the condition
that is reported by the controller with an interrupt.)

Signed-off-by: Clemens Ladisch <clemens< at >ladisch.de>
Cc: 2.6.36+ <stable< at >vger.kernel.org>
---
 drivers/firewire/ohci.c |    5 ++---
 1 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/firewire/ohci.c b/drivers/firewire/ohci.c
index 313d2fd..d39382c 100644
--- a/drivers/firewire/ohci.c
+++ b/drivers/firewire/ohci.c
< at >< at > -2806,7 +2806,7 < at >< at > static int handle_ir_buffer_fill(struct context *context,
 container_of(context, struct iso_context, context);
 u32 buffer_dma;

-if (!last->transfer_status)
+if (last->res_count != 0)
 /* Descriptor(s) not done yet, stop iteration */
 return 0;

< at >< at > -2820,8 +2820,7 < at >< at > static int handle_ir_buffer_fill(struct context *context,
 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
 ctx->base.callback.mc(&ctx->base,
       le32_to_cpu(last->data_address) +
-      le16_to_cpu(last->req_count) -
-      le16_to_cpu(last->res_count),
+      le16_to_cpu(last->req_count),
       ctx->base.callback_data);

 return 1;

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[PATCH]

Stefan Richter — 2012-03-04T20:34:21

CONFIG_FIREWIRE_OHCI_DEBUG could have been exposed to kernel tweakers
if CONFIG_EXPERT was set.  But in hindsight, this stuff is far too
useful to omit it.  So get rid of two #else branches that are only
going to bitrot otherwise.

Signed-off-by: Stefan Richter <stefanr< at >s5r6.in-berlin.de>
---
 drivers/firewire/Kconfig |    5 -----
 drivers/firewire/ohci.c  |   20 +-------------------
 2 files changed, 1 insertion(+), 24 deletions(-)

--- a/drivers/firewire/Kconfig
+++ b/drivers/firewire/Kconfig
< at >< at > -28,11 +28,6 < at >< at > config FIREWIRE_OHCI
   To compile this driver as a module, say M here:  The module will be
   called firewire-ohci.
 
-config FIREWIRE_OHCI_DEBUG
-bool
-depends on FIREWIRE_OHCI
-default y
-
 config FIREWIRE_SBP2
 tristate "Storage devices (SBP-2 protocol)"
 depends on FIREWIRE && SCSI
--- a/drivers/firewire/ohci.c
+++ b/drivers/firewire/ohci.c
< at >< at > -338,8 +338,6 < at >< at > MODULE_PARM_DESC(quirks, "Chip quirks (d
 #define OHCI_PARAM_DEBUG_IRQS4
 #define OHCI_PARAM_DEBUG_BUSRESETS8 /* only effective before chip init */
 
-#ifdef CONFIG_FIREWIRE_OHCI_DEBUG
-
 static int param_debug;
 module_param_named(debug, param_debug, int, 0644);
 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
< at >< at > -520,15 +518,6 < at >< at > static void log_ar_at_event(struct fw_oh
 }
 }
 
-#else
-
-#define param_debug 0
-static inline void log_irqs(struct fw_ohci *ohci, u32 evt) {}
-static inline void log_selfids(struct fw_ohci *ohci, int generation, int self_id_count) {}
-static inline void log_ar_at_event(struct fw_ohci *ohci, char dir, int speed, u32 *header, int evt) {}
-
-#endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
-
 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
 {
 writel(data, ohci->registers + offset);
< at >< at > -1640,17 +1629,10 < at >< at > static void detect_dead_context(struct f
 u32 ctl;
 
 ctl = reg_read(ohci, CONTROL_SET(regs));
-if (ctl & CONTEXT_DEAD) {
-#ifdef CONFIG_FIREWIRE_OHCI_DEBUG
+if (ctl & CONTEXT_DEAD)
 dev_err(ohci->card.device,
 "DMA context %s has stopped, error code: %s\n",
 name, evts[ctl & 0x1f]);
-#else
-dev_err(ohci->card.device,
-"DMA context %s has stopped, error code: %#x\n",
-name, ctl & 0x1f);
-#endif
-}
 }
 
 static void handle_dead_contexts(struct fw_ohci *ohci)

[work in progress] firewire: ohci: handle register access failurein SCLK domain

Stefan Richter — 2012-03-04T19:45:28

So here is about half of the necessary implementation for SCLK loss handling.
The "fixme" comments in the ohci.h diff at the end of this patch indicate
which registers are not yet checked against regAccessFail in some or all of
their accesses.  In terms of functions that need to be modified yet, this
means:
ohci_read_csr()
ohci_write_csr()
get_cycle_time()
context_run()
context_stop()
detect_dead_context()
ohci_flush_iso()
and possibly some of their callers.

The latter four functions may encounter regAccessFail only together with IR
contexts, not with AT, AR, or IT contexts.

ohci_read_csr() and ohci_write_csr() will need to have their function
prototypes changed to return 0 or -ERRNO.  This change needs to bubble up to
core.h::struct fw_card_driver and to firewire-core's call sites.

A thorough reader of the diff will notice that a great deal of failure
handling merely serves to limit the damage somewhat; recovery is hardly
possible anywhere.  Sometimes an error message in the log is still the only
effect.  However, my hope is that the whole regAccessFail affair will in
practice be limited to having to wait a bit in ohci_enable() for the SClk
signal to appear after LPS was switched on.

References: OHCI-1394 v1.1, sections 1.4.1, 4., and 6.1.

Oh, perhaps we should add optimizations for OHCI 1.0 chips because these
supposedly do not exhibit a regAccessFail flag.

This patch was only compile-tested so far.  I won't be applying anything
like this until each and every affected register access is converted.
Or we scale this down to a minimal change to ohci_enable() only and keep
the current irq_handler part for the rest of potential failures.
---
 drivers/firewire/ohci.c |  259 +++++++++++++++++++++++++++++-----------
 drivers/firewire/ohci.h |   47 ++++---
 2 files changed, 215 insertions(+), 91 deletions(-)

--- a/drivers/firewire/ohci.c
+++ b/drivers/firewire/ohci.c
< at >< at > -200,6 +200,7 < at >< at > struct fw_ohci {
  */
 spinlock_t lock;
 
+spinlock_t sclk_domain_reg_lock;
 struct mutex phy_reg_mutex;
 
 void *misc_buffer;
< at >< at > -360,7 +361,7 < at >< at > static void log_irqs(struct fw_ohci *ohc
 return;
 
 dev_notice(ohci->card.device,
-    "IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
+    "IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
     evt & OHCI1394_selfIDComplete? " selfID": "",
     evt & OHCI1394_RQPkt? " AR_req": "",
     evt & OHCI1394_RSPkt? " AR_resp": "",
< at >< at > -372,7 +373,6 < at >< at > static void log_irqs(struct fw_ohci *ohc
     evt & OHCI1394_cycleTooLong? " cycleTooLong": "",
     evt & OHCI1394_cycle64Seconds? " cycle64Seconds": "",
     evt & OHCI1394_cycleInconsistent? " cycleInconsistent": "",
-    evt & OHCI1394_regAccessFail? " regAccessFail": "",
     evt & OHCI1394_unrecoverableError? " unrecoverableError": "",
     evt & OHCI1394_busReset? " busReset": "",
     evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
< at >< at > -380,8 +380,7 < at >< at > static void log_irqs(struct fw_ohci *ohc
     OHCI1394_respTxComplete | OHCI1394_isochRx |
     OHCI1394_isochTx | OHCI1394_postedWriteErr |
     OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
-    OHCI1394_cycleInconsistent |
-    OHCI1394_regAccessFail | OHCI1394_busReset)
+    OHCI1394_cycleInconsistent | OHCI1394_busReset)
 ? " ?": "");
 }
 
< at >< at > -545,6 +544,84 < at >< at > static inline void flush_writes(const st
 reg_read(ohci, OHCI1394_Version);
 }
 
+/* caller must hold sclk_domain_reg_lock */
+static int check_reg_access_fail(const struct fw_ohci *ohci)
+{
+u32 reg = reg_read(ohci, OHCI1394_IntEventSet);
+
+if (!~reg)
+return -ENODEV; /* Card was ejected. */
+
+if (reg & OHCI1394_regAccessFail) {
+reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_regAccessFail);
+/* Clear the bit before any other reg_write in SCLK domain. */
+mmiowb();
+return -EAGAIN;
+}
+
+return 0;
+}
+
+static int __reg_rw_sclk(struct fw_ohci *ohci, int offset, u32 *data, bool read)
+{
+unsigned long flags;
+int ret;
+
+spin_lock_irqsave(&ohci->sclk_domain_reg_lock, flags);
+if (read)
+*data = reg_read(ohci, offset);
+else
+reg_write(ohci, offset, *data);
+ret = check_reg_access_fail(ohci);
+spin_unlock_irqrestore(&ohci->sclk_domain_reg_lock, flags);
+
+return ret;
+}
+
+static int reg_rw_sclk(struct fw_ohci *ohci, int offset, u32 *data,
+       bool can_sleep, bool read)
+{
+int i, ret;
+
+for (i = 0; ; i++) {
+ret = __reg_rw_sclk(ohci, offset, data, read);
+if (ret != -EAGAIN)
+return ret;
+if (i == 20)
+break;
+if (can_sleep)
+msleep(50);
+}
+dev_err(ohci->card.device, "SClk off while %sing at 0x%03x\n",
+read ? "read" : "writ", offset);
+
+return ret;
+}
+
+/* accessors for registers in SCLK domain, for use in atomic contexts */
+
+static int reg_write_sclk(struct fw_ohci *ohci, int offset, u32 data)
+{
+return reg_rw_sclk(ohci, offset, &data, false, false);
+}
+
+static int reg_read_sclk(struct fw_ohci *ohci, int offset, u32 *data)
+{
+return reg_rw_sclk(ohci, offset, data, false, true);
+}
+
+/* accessors for registers in SCLK domain, for use in process contexts */
+
+static int reg_write_sclk_wait(struct fw_ohci *ohci, int offset, u32 data)
+{
+return reg_rw_sclk(ohci, offset, &data, true, false);
+}
+
+static int reg_read_sclk_wait(struct fw_ohci *ohci, int offset, u32 *data)
+{
+return reg_rw_sclk(ohci, offset, data, true, true);
+}
+
 /*
  * Beware!  read_phy_reg(), write_phy_reg(), update_phy_reg(), and
  * read_paged_phy_reg() require the caller to hold ohci->phy_reg_mutex.
< at >< at > -554,13 +631,16 < at >< at > static inline void flush_writes(const st
 static int read_phy_reg(struct fw_ohci *ohci, int addr)
 {
 u32 val;
-int i;
+int i, ret;
 
-reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
+ret = reg_write_sclk_wait(ohci, OHCI1394_PhyControl,
+  OHCI1394_PhyControl_Read(addr));
+if (ret < 0)
+return ret;
 for (i = 0; i < 3 + 100; i++) {
-val = reg_read(ohci, OHCI1394_PhyControl);
-if (!~val)
-return -ENODEV; /* Card was ejected. */
+ret = reg_read_sclk_wait(ohci, OHCI1394_PhyControl, &val);
+if (ret < 0)
+return ret;
 
 if (val & OHCI1394_PhyControl_ReadDone)
 return OHCI1394_PhyControl_ReadData(val);
< at >< at > -577,16 +657,18 < at >< at > static int read_phy_reg(struct fw_ohci *
 return -EBUSY;
 }
 
-static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
+static int write_phy_reg(struct fw_ohci *ohci, int addr, u32 val)
 {
-int i;
+int i, ret;
 
-reg_write(ohci, OHCI1394_PhyControl,
-  OHCI1394_PhyControl_Write(addr, val));
+ret = reg_write_sclk_wait(ohci, OHCI1394_PhyControl,
+  OHCI1394_PhyControl_Write(addr, val));
+if (ret < 0)
+return ret;
 for (i = 0; i < 3 + 100; i++) {
-val = reg_read(ohci, OHCI1394_PhyControl);
-if (!~val)
-return -ENODEV; /* Card was ejected. */
+ret = reg_read_sclk_wait(ohci, OHCI1394_PhyControl, &val);
+if (ret < 0)
+return ret;
 
 if (!(val & OHCI1394_PhyControl_WritePending))
 return 0;
< at >< at > -1531,7 +1613,8 < at >< at > static void handle_local_lock(struct fw_
 struct fw_packet response;
 int tcode, length, ext_tcode, sel, try;
 __be32 *payload, lock_old;
-u32 lock_arg, lock_data;
+u32 lock_arg, lock_data, reg;
+unsigned long flags;
 
 tcode = HEADER_GET_TCODE(packet->header[0]);
 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
< at >< at > -1551,24 +1634,35 < at >< at > static void handle_local_lock(struct fw_
 goto out;
 }
 
+spin_lock_irqsave(&ohci->sclk_domain_reg_lock, flags);
+
 sel = (csr - CSR_BUS_MANAGER_ID) / 4;
 reg_write(ohci, OHCI1394_CSRData, lock_data);
 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
 reg_write(ohci, OHCI1394_CSRControl, sel);
 
-for (try = 0; try < 20; try++)
-if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
-lock_old = cpu_to_be32(reg_read(ohci,
-OHCI1394_CSRData));
+for (try = 0; try < 20; try++) {
+reg = reg_read(ohci, OHCI1394_CSRControl);
+if (check_reg_access_fail(ohci))
+break;
+
+if (reg & OHCI1394_CSRControl_csrDone) {
+lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData));
+if (check_reg_access_fail(ohci))
+break;
+
 fw_fill_response(&response, packet->header,
  RCODE_COMPLETE,
  &lock_old, sizeof(lock_old));
-goto out;
+goto out_unlock;
 }
+}
 
 dev_err(ohci->card.device, "swap not done (CSR lock timeout)\n");
 fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
 
+ out_unlock:
+spin_unlock_irqrestore(&ohci->sclk_domain_reg_lock, flags);
  out:
 fw_core_handle_response(&ohci->card, &response);
 }
< at >< at > -1794,11 +1888,13 < at >< at > static int get_self_id_pos(struct fw_ohc
  */
 static int find_and_insert_self_id(struct fw_ohci *ohci, int self_id_count)
 {
-int reg, i, pos, status;
+int ret, i, pos, status;
 /* link active 1, speed 3, bridge 0, contender 1, more packets 0 */
-u32 self_id = 0x8040c800;
+u32 reg, self_id = 0x8040c800;
 
-reg = reg_read(ohci, OHCI1394_NodeID);
+ret = reg_read_sclk_wait(ohci, OHCI1394_NodeID, &reg);
+if (ret < 0)
+return ret;
 if (!(reg & OHCI1394_NodeID_idValid)) {
 dev_notice(ohci->card.device,
    "node ID not valid, new bus reset in progress\n");
< at >< at > -1845,7 +1941,8 < at >< at > static void bus_reset_work(struct work_s
 dma_addr_t free_rom_bus = 0;
 bool is_new_root;
 
-reg = reg_read(ohci, OHCI1394_NodeID);
+if (reg_read_sclk_wait(ohci, OHCI1394_NodeID, &reg) < 0)
+return;
 if (!(reg & OHCI1394_NodeID_idValid)) {
 dev_notice(ohci->card.device,
    "node ID not valid, new bus reset in progress\n");
< at >< at > -1860,8 +1957,8 < at >< at > static void bus_reset_work(struct work_s
 
 is_new_root = (reg & OHCI1394_NodeID_root) != 0;
 if (!(ohci->is_root && is_new_root))
-reg_write(ohci, OHCI1394_LinkControlSet,
-  OHCI1394_LinkControl_cycleMaster);
+reg_write_sclk_wait(ohci, OHCI1394_LinkControlSet,
+    OHCI1394_LinkControl_cycleMaster);
 ohci->is_root = is_new_root;
 
 reg = reg_read(ohci, OHCI1394_SelfIDCount);
< at >< at > -2003,8 +2100,8 < at >< at > static void bus_reset_work(struct work_s
 }
 
 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
-reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
-reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
+reg_write_sclk(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
+reg_write_sclk(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
 #endif
 
 spin_unlock_irqrestore(&ohci->lock, flags);
< at >< at > -2079,9 +2176,6 < at >< at > static irqreturn_t irq_handler(int irq,
 }
 }
 
-if (unlikely(event & OHCI1394_regAccessFail))
-dev_err(ohci->card.device, "register access failure\n");
-
 if (unlikely(event & OHCI1394_postedWriteErr)) {
 reg_read(ohci, OHCI1394_PostedWriteAddressHi);
 reg_read(ohci, OHCI1394_PostedWriteAddressLo);
< at >< at > -2095,8 +2189,8 < at >< at > static irqreturn_t irq_handler(int irq,
 if (printk_ratelimit())
 dev_notice(ohci->card.device,
    "isochronous cycle too long\n");
-reg_write(ohci, OHCI1394_LinkControlSet,
-  OHCI1394_LinkControl_cycleMaster);
+reg_write_sclk(ohci, OHCI1394_LinkControlSet,
+       OHCI1394_LinkControl_cycleMaster);
 }
 
 if (unlikely(event & OHCI1394_cycleInconsistent)) {
< at >< at > -2231,7 +2325,7 < at >< at > static int ohci_enable(struct fw_card *c
 {
 struct fw_ohci *ohci = fw_ohci(card);
 struct pci_dev *dev = to_pci_dev(card->device);
-u32 lps, seconds, version, irqs;
+u32 lps, seconds, version, irqs, reg;
 int i, ret;
 
 if (software_reset(ohci)) {
< at >< at > -2262,6 +2356,7 < at >< at > static int ohci_enable(struct fw_card *c
 dev_err(card->device, "failed to set Link Power Status\n");
 return -EIO;
 }
+reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_regAccessFail);
 
 if (ohci->quirks & QUIRK_TI_SLLZ059) {
 ret = probe_tsb41ba3d(ohci);
< at >< at > -2277,9 +2372,11 < at >< at > static int ohci_enable(struct fw_card *c
   OHCI1394_HCControl_noByteSwapData);
 
 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
-reg_write(ohci, OHCI1394_LinkControlSet,
-  OHCI1394_LinkControl_cycleTimerEnable |
-  OHCI1394_LinkControl_cycleMaster);
+ret = reg_write_sclk_wait(ohci, OHCI1394_LinkControlSet,
+  OHCI1394_LinkControl_cycleTimerEnable |
+  OHCI1394_LinkControl_cycleMaster);
+if (ret < 0)
+return ret;
 
 reg_write(ohci, OHCI1394_ATRetries,
   OHCI1394_MAX_AT_REQ_RETRIES |
< at >< at > -2288,8 +2385,11 < at >< at > static int ohci_enable(struct fw_card *c
   (200 << 16));
 
 seconds = lower_32_bits(get_seconds());
-reg_write(ohci, OHCI1394_IsochronousCycleTimer, seconds << 25);
 ohci->bus_time = seconds & ~0x3f;
+ret = reg_write_sclk_wait(ohci, OHCI1394_IsochronousCycleTimer,
+  seconds << 25);
+if (ret < 0)
+return ret;
 
 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
 if (version >= OHCI_VERSION_1_1) {
< at >< at > -2299,9 +2399,16 < at >< at > static int ohci_enable(struct fw_card *c
 }
 
 /* Get implemented bits of the priority arbitration request counter. */
-reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
-ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
-reg_write(ohci, OHCI1394_FairnessControl, 0);
+ret = reg_write_sclk_wait(ohci, OHCI1394_FairnessControl, 0x3f);
+if (ret < 0)
+return ret;
+ret = reg_read_sclk_wait(ohci, OHCI1394_FairnessControl, &reg);
+if (ret < 0)
+return ret;
+ret = reg_write_sclk_wait(ohci, OHCI1394_FairnessControl, 0);
+if (ret < 0)
+return ret;
+ohci->pri_req_max = reg & 0x3f;
 card->priority_budget_implemented = ohci->pri_req_max != 0;
 
 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
< at >< at > -2361,24 +2468,20 < at >< at > static int ohci_enable(struct fw_card *c
   be32_to_cpu(ohci->next_config_rom[2]));
 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
 
-reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
+ret = reg_write_sclk_wait(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
+if (ret < 0)
+goto out;
 
 if (!(ohci->quirks & QUIRK_NO_MSI))
 pci_enable_msi(dev);
-if (request_irq(dev->irq, irq_handler,
-pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
-ohci_driver_name, ohci)) {
+ret = request_irq(dev->irq, irq_handler,
+  pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
+  ohci_driver_name, ohci);
+if (ret < 0) {
 dev_err(card->device, "failed to allocate interrupt %d\n",
 dev->irq);
 pci_disable_msi(dev);
-
-if (config_rom) {
-dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
-  ohci->next_config_rom,
-  ohci->next_config_rom_bus);
-ohci->next_config_rom = NULL;
-}
-return -EIO;
+goto out;
 }
 
 irqs =OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
< at >< at > -2386,7 +2489,6 < at >< at > static int ohci_enable(struct fw_card *c
 OHCI1394_isochTx | OHCI1394_isochRx |
 OHCI1394_postedWriteErr |
 OHCI1394_selfIDComplete |
-OHCI1394_regAccessFail |
 OHCI1394_cycle64Seconds |
 OHCI1394_cycleInconsistent |
 OHCI1394_unrecoverableError |
< at >< at > -2400,9 +2502,11 < at >< at > static int ohci_enable(struct fw_card *c
   OHCI1394_HCControl_linkEnable |
   OHCI1394_HCControl_BIBimageValid);
 
-reg_write(ohci, OHCI1394_LinkControlSet,
-  OHCI1394_LinkControl_rcvSelfID |
-  OHCI1394_LinkControl_rcvPhyPkt);
+ret = reg_write_sclk_wait(ohci, OHCI1394_LinkControlSet,
+  OHCI1394_LinkControl_rcvSelfID |
+  OHCI1394_LinkControl_rcvPhyPkt);
+if (ret < 0)
+goto out;
 
 ar_context_run(&ohci->ar_request_ctx);
 ar_context_run(&ohci->ar_response_ctx);
< at >< at > -2413,6 +2517,14 < at >< at > static int ohci_enable(struct fw_card *c
 fw_schedule_bus_reset(&ohci->card, false, true);
 
 return 0;
+ out:
+if (config_rom) {
+dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
+  ohci->next_config_rom,
+  ohci->next_config_rom_bus);
+ohci->next_config_rom = NULL;
+}
+return ret;
 }
 
 static int ohci_set_config_rom(struct fw_card *card,
< at >< at > -2574,11 +2686,9 < at >< at > static int ohci_enable_phys_dma(struct f
 
 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
 if (n < 32)
-reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
+reg_write_sclk(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
 else
-reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
-
-flush_writes(ohci);
+reg_write_sclk(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
  out:
 spin_unlock_irqrestore(&ohci->lock, flags);
 
< at >< at > -2866,16 +2976,23 < at >< at > static int handle_it_packet(struct conte
 return 1;
 }
 
-static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
+static int set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
 {
 u32 hi = channels >> 32, lo = channels;
+unsigned long flags;
+int ret;
 
+spin_lock_irqsave(&ohci->sclk_domain_reg_lock, flags);
 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
 reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
 reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
-mmiowb();
-ohci->mc_channels = channels;
+ret = check_reg_access_fail(ohci);
+if (ret == 0)
+ohci->mc_channels = channels;
+spin_unlock_irqrestore(&ohci->sclk_domain_reg_lock, flags);
+
+return ret;
 }
 
 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
< at >< at > -2949,11 +3066,16 < at >< at > static struct fw_iso_context *ohci_alloc
 if (ret < 0)
 goto out_with_header;
 
-if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL)
-set_multichannel_mask(ohci, 0);
+if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL) {
+ret = set_multichannel_mask(ohci, 0);
+if (ret < 0)
+goto out_with_context;
+}
 
 return &ctx->base;
 
+ out_with_context:
+context_release(&ctx->context);
  out_with_header:
 free_page((unsigned long)ctx->header);
  out:
< at >< at > -3497,6 +3619,7 < at >< at > static int __devinit pci_probe(struct pc
 pci_set_drvdata(dev, ohci);
 
 spin_lock_init(&ohci->lock);
+spin_lock_init(&ohci->sclk_domain_reg_lock);
 mutex_init(&ohci->phy_reg_mutex);
 
 INIT_WORK(&ohci->bus_reset_work, bus_reset_work);
--- a/drivers/firewire/ohci.h
+++ b/drivers/firewire/ohci.h
< at >< at > -6,9 +6,10 < at >< at >
 #define OHCI1394_Version                      0x000
 #define OHCI1394_GUID_ROM                     0x004
 #define OHCI1394_ATRetries                    0x008
-#define OHCI1394_CSRData                      0x00C
-#define OHCI1394_CSRCompareData               0x010
-#define OHCI1394_CSRControl                   0x014
+#define OHCI1394_CSRData                      0x00C/* SCLK domain */
+#define OHCI1394_CSRCompareData               0x010/* SCLK domain */
+#define OHCI1394_CSRControl                   0x014/* SCLK domain */
+#define  OHCI1394_CSRControl_csrDone0x80000000
 #define OHCI1394_ConfigROMhdr                 0x018
 #define OHCI1394_BusID                        0x01C
 #define OHCI1394_BusOptions                   0x020
< at >< at > -31,10 +32,10 < at >< at >
 #define OHCI1394_SelfIDBuffer                 0x064
 #define OHCI1394_SelfIDCount                  0x068
 #define  OHCI1394_SelfIDCount_selfIDError0x80000000
-#define OHCI1394_IRMultiChanMaskHiSet         0x070
-#define OHCI1394_IRMultiChanMaskHiClear       0x074
-#define OHCI1394_IRMultiChanMaskLoSet         0x078
-#define OHCI1394_IRMultiChanMaskLoClear       0x07C
+#define OHCI1394_IRMultiChanMaskHiSet         0x070/* SCLK domain */
+#define OHCI1394_IRMultiChanMaskHiClear       0x074/* SCLK domain */
+#define OHCI1394_IRMultiChanMaskLoSet         0x078/* SCLK domain */
+#define OHCI1394_IRMultiChanMaskLoClear       0x07C/* SCLK domain */
 #define OHCI1394_IntEventSet                  0x080
 #define OHCI1394_IntEventClear                0x084
 #define OHCI1394_IntMaskSet                   0x088
< at >< at > -50,34 +51,34 < at >< at >
 #define OHCI1394_InitialBandwidthAvailable    0x0B0
 #define OHCI1394_InitialChannelsAvailableHi   0x0B4
 #define OHCI1394_InitialChannelsAvailableLo   0x0B8
-#define OHCI1394_FairnessControl              0x0DC
-#define OHCI1394_LinkControlSet               0x0E0
-#define OHCI1394_LinkControlClear             0x0E4
+#define OHCI1394_FairnessControl              0x0DC/* fixme SCLK domain */
+#define OHCI1394_LinkControlSet               0x0E0/* fixme SCLK domain */
+#define OHCI1394_LinkControlClear             0x0E4/* fixme SCLK domain */
 #define   OHCI1394_LinkControl_rcvSelfID(1 << 9)
 #define   OHCI1394_LinkControl_rcvPhyPkt(1 << 10)
 #define   OHCI1394_LinkControl_cycleTimerEnable(1 << 20)
 #define   OHCI1394_LinkControl_cycleMaster(1 << 21)
 #define   OHCI1394_LinkControl_cycleSource(1 << 22)
-#define OHCI1394_NodeID                       0x0E8
+#define OHCI1394_NodeID                       0x0E8/* fixme SCLK domain */
 #define   OHCI1394_NodeID_idValid             0x80000000
 #define   OHCI1394_NodeID_root                0x40000000
 #define   OHCI1394_NodeID_nodeNumber          0x0000003f
 #define   OHCI1394_NodeID_busNumber           0x0000ffc0
-#define OHCI1394_PhyControl                   0x0EC
+#define OHCI1394_PhyControl                   0x0EC/* SCLK domain */
 #define   OHCI1394_PhyControl_Read(addr)(((addr) << 8) | 0x00008000)
 #define   OHCI1394_PhyControl_ReadDone0x80000000
 #define   OHCI1394_PhyControl_ReadData(r)(((r) & 0x00ff0000) >> 16)
 #define   OHCI1394_PhyControl_Write(addr, data)(((addr) << 8) | (data) | 0x00004000)
 #define   OHCI1394_PhyControl_WritePending0x00004000
-#define OHCI1394_IsochronousCycleTimer        0x0F0
-#define OHCI1394_AsReqFilterHiSet             0x100
-#define OHCI1394_AsReqFilterHiClear           0x104
-#define OHCI1394_AsReqFilterLoSet             0x108
-#define OHCI1394_AsReqFilterLoClear           0x10C
-#define OHCI1394_PhyReqFilterHiSet            0x110
-#define OHCI1394_PhyReqFilterHiClear          0x114
-#define OHCI1394_PhyReqFilterLoSet            0x118
-#define OHCI1394_PhyReqFilterLoClear          0x11C
+#define OHCI1394_IsochronousCycleTimer        0x0F0/* fixme SCLK domain */
+#define OHCI1394_AsReqFilterHiSet             0x100/* SCLK domain */
+#define OHCI1394_AsReqFilterHiClear           0x104/* SCLK domain */
+#define OHCI1394_AsReqFilterLoSet             0x108/* SCLK domain */
+#define OHCI1394_AsReqFilterLoClear           0x10C/* SCLK domain */
+#define OHCI1394_PhyReqFilterHiSet            0x110/* SCLK domain */
+#define OHCI1394_PhyReqFilterHiClear          0x114/* SCLK domain */
+#define OHCI1394_PhyReqFilterLoSet            0x118/* SCLK domain */
+#define OHCI1394_PhyReqFilterLoClear          0x11C/* SCLK domain */
 #define OHCI1394_PhyUpperBound                0x120
 
 #define OHCI1394_AsReqTrContextBase           0x180
< at >< at > -108,8 +109,8 < at >< at >
 
 /* Isochronous receive registers */
 #define OHCI1394_IsoRcvContextBase(n)         (0x400 + 32 * (n))
-#define OHCI1394_IsoRcvContextControlSet(n)   (0x400 + 32 * (n))
-#define OHCI1394_IsoRcvContextControlClear(n) (0x404 + 32 * (n))
+#define OHCI1394_IsoRcvContextControlSet(n)   (0x400 + 32 * (n)) /* fixme SCLK domain */
+#define OHCI1394_IsoRcvContextControlClear(n) (0x404 + 32 * (n)) /* fixme SCLK domain */
 #define OHCI1394_IsoRcvCommandPtr(n)          (0x40C + 32 * (n))
 #define OHCI1394_IsoRcvContextMatch(n)        (0x410 + 32 * (n))

[PATCH] firewire: tone down some diagnostic log messages

Stefan Richter — 2012-03-04T13:24:31

The "skipped bus generations" message was added together with the
respective fw_device retaining/ reviving code in order to see how it all
works out.  It did well, so don't spam the log anymore.

The "register access failure" situation still needs an actual handler.
But at this point it makes less sense to ask folks to send mails about
it.  We now have a pretty good picture of what controllers emit this and
when:

Texas Instruments PCIxx21 FireWire + CardBus + flash memory card
controller:
https://bugzilla.redhat.com/show_bug.cgi?id=608544

O2 Micro FireWire + flash memory card controller:
https://bugs.launchpad.net/ubuntu/+source/linux/+bug/801719
https://bugs.launchpad.net/ubuntu/+source/linux/+bug/881688
http://marc.info/?l=linux1394-devel&m=132309283531423
http://marc.info/?l=linux1394-devel&m=132368567907469
http://marc.info/?l=linux1394-devel&m=132516165727468
http://marc.info/?l=linux1394-devel&m=133006486927699

Pinnacle Movieboard:
commit 7f7e37115a8b6724f26d0637a04e1d35e3c59717
http://marc.info/?l=linux1394-devel&m=130714243325962

Signed-off-by: Stefan Richter <stefanr< at >s5r6.in-berlin.de>
---
 drivers/firewire/core-topology.c |    1 -
 drivers/firewire/ohci.c          |    3 +--
 2 files changed, 1 insertion(+), 3 deletions(-)

--- a/drivers/firewire/core-topology.c
+++ b/drivers/firewire/core-topology.c
< at >< at > -530,7 +530,6 < at >< at > void fw_core_handle_bus_reset(struct fw_
  */
 if (!is_next_generation(generation, card->generation) &&
     card->local_node != NULL) {
-fw_notice(card, "skipped bus generations, destroying all nodes\n");
 fw_destroy_nodes(card);
 card->bm_retries = 0;
 }
--- a/drivers/firewire/ohci.c
+++ b/drivers/firewire/ohci.c
< at >< at > -2080,8 +2080,7 < at >< at > static irqreturn_t irq_handler(int irq,
 }
 
 if (unlikely(event & OHCI1394_regAccessFail))
-dev_err(ohci->card.device,
-"register access failure - please notify linux1394-devel< at >lists.sf.net\n");
+dev_err(ohci->card.device, "register access failure\n");
 
 if (unlikely(event & OHCI1394_postedWriteErr)) {
 reg_read(ohci, OHCI1394_PostedWriteAddressHi);