gmane.linux.kernel.cryptoapi

(unknown)

robothroli company — 2012-05-25T13:45:54

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RFC: support for MV_CESA with TDMA

Phil Sutter — 2012-05-25T16:08:26

Hi,

The following patch series adds support for the TDMA engine built into
Marvell's Kirkwood-based SoCs, and enhances mv_cesa.c in order to use it
for speeding up crypto operations. Kirkwood hardware contains a security
accelerator, which can control DMA as well as crypto engines. It allows
for operation with minimal software intervenience, which the following
patches implement: using a chain of DMA descriptors, data input,
configuration, engine startup and data output repeat fully automatically
until the whole input data has been handled.

The point for this being RFC is backwards-compatibility: earlier
hardware (Orion) ships a (slightly) different DMA engine (IDMA) along
with the same crypto engine, so in fact mv_cesa.c is in use on these
platforms, too. But since I don't possess hardware of this kind, I am
not able to make this code IDMA-compatible. Also, due to the quite
massive reorganisation of code flow, I don't really see how to make TDMA
support optional in mv_cesa.c.

Greetings, Phil

[PATCH 1/4] mv_cesa: add an expiry timer in case anything goes wrong

Phil Sutter — 2012-05-25T13:54:46

The timer triggers when 500ms have gone by after triggering the engine
and no completion interrupt was received. The callback then tries to
sanitise things as well as possible.

Signed-off-by: Phil Sutter <phil.sutter< at >viprinet.com>
---
 drivers/crypto/mv_cesa.c |   41 +++++++++++++++++++++++++++++++----------
 1 files changed, 31 insertions(+), 10 deletions(-)

diff --git a/drivers/crypto/mv_cesa.c b/drivers/crypto/mv_cesa.c
index e6ecc5f..8327bed 100644
--- a/drivers/crypto/mv_cesa.c
+++ b/drivers/crypto/mv_cesa.c
< at >< at > -23,6 +23,7 < at >< at >
 
 #define MV_CESA"MV-CESA:"
 #define MAX_HW_HASH_SIZE0xFFFF
+#define MV_CESA_EXPIRE500 /* msec */
 
 /*
  * STM:
< at >< at > -85,6 +86,7 < at >< at > struct crypto_priv {
 spinlock_t lock;
 struct crypto_queue queue;
 enum engine_status eng_st;
+struct timer_list completion_timer;
 struct crypto_async_request *cur_req;
 struct req_progress p;
 int max_req_size;
< at >< at > -136,6 +138,29 < at >< at > struct mv_req_hash_ctx {
 int count_add;
 };
 
+static void mv_completion_timer_callback(unsigned long unused)
+{
+int active = readl(cpg->reg + SEC_ACCEL_CMD) & SEC_CMD_EN_SEC_ACCL0;
+
+printk(KERN_ERR MV_CESA
+       "completion timer expired (CESA %sactive), cleaning up.\n",
+       active ? "" : "in");
+
+del_timer(&cpg->completion_timer);
+writel(SEC_CMD_DISABLE_SEC, cpg->reg + SEC_ACCEL_CMD);
+while(readl(cpg->reg + SEC_ACCEL_CMD) & SEC_CMD_DISABLE_SEC)
+printk(KERN_INFO MV_CESA "%s: waiting for engine finishing\n", __func__);
+cpg->eng_st = ENGINE_W_DEQUEUE;
+wake_up_process(cpg->queue_th);
+}
+
+static void mv_setup_timer(void)
+{
+setup_timer(&cpg->completion_timer, &mv_completion_timer_callback, 0);
+mod_timer(&cpg->completion_timer,
+jiffies + msecs_to_jiffies(MV_CESA_EXPIRE));
+}
+
 static void compute_aes_dec_key(struct mv_ctx *ctx)
 {
 struct crypto_aes_ctx gen_aes_key;
< at >< at > -271,12 +296,8 < at >< at > static void mv_process_current_q(int first_block)
 sizeof(struct sec_accel_config));
 
 /* GO */
+mv_setup_timer();
 writel(SEC_CMD_EN_SEC_ACCL0, cpg->reg + SEC_ACCEL_CMD);
-
-/*
- * XXX: add timer if the interrupt does not occur for some mystery
- * reason
- */
 }
 
 static void mv_crypto_algo_completion(void)
< at >< at > -355,12 +376,8 < at >< at > static void mv_process_hash_current(int first_block)
 memcpy(cpg->sram + SRAM_CONFIG, &op, sizeof(struct sec_accel_config));
 
 /* GO */
+mv_setup_timer();
 writel(SEC_CMD_EN_SEC_ACCL0, cpg->reg + SEC_ACCEL_CMD);
-
-/*
-* XXX: add timer if the interrupt does not occur for some mystery
-* reason
-*/
 }
 
 static inline int mv_hash_import_sha1_ctx(const struct mv_req_hash_ctx *ctx,
< at >< at > -886,6 +903,10 < at >< at > irqreturn_t crypto_int(int irq, void *priv)
 if (!(val & SEC_INT_ACCEL0_DONE))
 return IRQ_NONE;
 
+if (!del_timer(&cpg->completion_timer)) {
+printk(KERN_WARNING MV_CESA
+       "got an interrupt but no pending timer?\n");
+}
 val &= ~SEC_INT_ACCEL0_DONE;
 writel(val, cpg->reg + FPGA_INT_STATUS);
 writel(val, cpg->reg + SEC_ACCEL_INT_STATUS);

[PATCH] crypto: sha1 - use Kbuild supplied flags for AVX test

Mathias Krause — 2012-05-24T09:13:42

Commit ea4d26ae ("raid5: add AVX optimized RAID5 checksumming")
introduced x86/ arch wide defines for AFLAGS and CFLAGS indicating AVX
support in binutils based on the same test we have in x86/crypto/ right
now. To minimize duplication drop our implementation in favour to the
one in x86/.

Signed-off-by: Mathias Krause <minipli< at >googlemail.com>
---

This should be applied to cryptodev-2.6.git after it contains the above
mentioned commit, e.g. after cryptodev-2.6.git rebased to/merged v3.5-rc1.

 arch/x86/crypto/Makefile          |    7 -------
 arch/x86/crypto/sha1_ssse3_asm.S  |    2 +-
 arch/x86/crypto/sha1_ssse3_glue.c |    6 +++---
 3 files changed, 4 insertions(+), 11 deletions(-)

diff --git a/arch/x86/crypto/Makefile b/arch/x86/crypto/Makefile
index e191ac0..479f95a 100644
--- a/arch/x86/crypto/Makefile
+++ b/arch/x86/crypto/Makefile
< at >< at > -34,12 +34,5 < at >< at > salsa20-x86_64-y := salsa20-x86_64-asm_64.o salsa20_glue.o
 serpent-sse2-x86_64-y := serpent-sse2-x86_64-asm_64.o serpent_sse2_glue.o
 
 aesni-intel-y := aesni-intel_asm.o aesni-intel_glue.o fpu.o
-
 ghash-clmulni-intel-y := ghash-clmulni-intel_asm.o ghash-clmulni-intel_glue.o
-
-# enable AVX support only when $(AS) can actually assemble the instructions
-ifeq ($(call as-instr,vpxor %xmm0$(comma)%xmm1$(comma)%xmm2,yes,no),yes)
-AFLAGS_sha1_ssse3_asm.o += -DSHA1_ENABLE_AVX_SUPPORT
-CFLAGS_sha1_ssse3_glue.o += -DSHA1_ENABLE_AVX_SUPPORT
-endif
 sha1-ssse3-y := sha1_ssse3_asm.o sha1_ssse3_glue.o
diff --git a/arch/x86/crypto/sha1_ssse3_asm.S b/arch/x86/crypto/sha1_ssse3_asm.S
index b2c2f57..49d6987 100644
--- a/arch/x86/crypto/sha1_ssse3_asm.S
+++ b/arch/x86/crypto/sha1_ssse3_asm.S
< at >< at > -468,7 +468,7 < at >< at > W_PRECALC_SSSE3
  */
 SHA1_VECTOR_ASM     sha1_transform_ssse3
 
-#ifdef SHA1_ENABLE_AVX_SUPPORT
+#ifdef CONFIG_AS_AVX
 
 .macro W_PRECALC_AVX
 
diff --git a/arch/x86/crypto/sha1_ssse3_glue.c b/arch/x86/crypto/sha1_ssse3_glue.c
index f916499..4a11a9d 100644
--- a/arch/x86/crypto/sha1_ssse3_glue.c
+++ b/arch/x86/crypto/sha1_ssse3_glue.c
< at >< at > -35,7 +35,7 < at >< at >
 
 asmlinkage void sha1_transform_ssse3(u32 *digest, const char *data,
      unsigned int rounds);
-#ifdef SHA1_ENABLE_AVX_SUPPORT
+#ifdef CONFIG_AS_AVX
 asmlinkage void sha1_transform_avx(u32 *digest, const char *data,
    unsigned int rounds);
 #endif
< at >< at > -184,7 +184,7 < at >< at > static struct shash_alg alg = {
 }
 };
 
-#ifdef SHA1_ENABLE_AVX_SUPPORT
+#ifdef CONFIG_AS_AVX
 static bool __init avx_usable(void)
 {
 u64 xcr0;
< at >< at > -209,7 +209,7 < at >< at > static int __init sha1_ssse3_mod_init(void)
 if (cpu_has_ssse3)
 sha1_transform_asm = sha1_transform_ssse3;
 
-#ifdef SHA1_ENABLE_AVX_SUPPORT
+#ifdef CONFIG_AS_AVX
 /* allow AVX to override SSSE3, it's a little faster */
 if (avx_usable())
 sha1_transform_asm = sha1_transform_avx;

[RFC/PATCH] crypto: talitos - replace the tasklet implementation with NAPI

Horia Geanta — 2012-05-21T16:53:35

Hi,

During performance measurements & optimization phase, we found out that we get
better numbers (in the range of 9-10%) by using the NAPI approach for the
crypto engine interrupt mechanism instead of tasklet.
We found out that for the tasklet-based interrupt mechanism, we were facing
imbalanced processing - NET RX softirq was running more frequently than the
crypto tasklet.

The patch replaces the tasklet-based implementation with NAPI. It is based on
latest crypto-2.6 tree.

I am aware of the fact that using NAPI for anything else than net devices might
be frowned upon, that's why I am adding the netdev folks to comment, advise.

Thanks,
Horia


From 30f6247fa5ada7e53523492ca4e70b61e3f5aeeb Mon Sep 17 00:00:00 2001
From: Horia Geanta <horia.geanta< at >freescale.com>
Date: Wed, 2 May 2012 18:40:03 +0300
Subject: [RFC/PATCH] crypto: talitos - replace the tasklet implementation with NAPI

This patch updates the current tasklet implement to NAPI so as
the system is more balanced in the terms that the packet submission
and the packet forwarding after being processed can be done at
the same priority.

Signed-off-by: Sandeep Malik <Sandeep.Malik< at >freescale.com>
Signed-off-by: Horia Geanta <horia.geanta< at >freescale.com>
---
 drivers/crypto/Kconfig   |    2 +-
 drivers/crypto/talitos.c |  148 +++++++++++++++++++++++++++++++++-------------
 drivers/crypto/talitos.h |    4 +-
 3 files changed, 110 insertions(+), 44 deletions(-)

diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index ab9abb4..934fa57 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
< at >< at > -209,7 +209,7 < at >< at > config CRYPTO_DEV_TALITOS
 select CRYPTO_ALGAPI
 select CRYPTO_AUTHENC
 select HW_RANDOM
-depends on FSL_SOC
+depends on FSL_SOC && NET
 help
   Say 'Y' here to use the Freescale Security Engine (SEC)
   to offload cryptographic algorithm computation.
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index 921039e..817f74c 100644
--- a/drivers/crypto/talitos.c
+++ b/drivers/crypto/talitos.c
< at >< at > -1,7 +1,7 < at >< at >
 /*
  * talitos - Freescale Integrated Security Engine (SEC) device driver
  *
- * Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
+ * Copyright (c) 2008-2012 Freescale Semiconductor, Inc.
  *
  * Scatterlist Crypto API glue code copied from files with the following:
  * Copyright (c) 2006-2007 Herbert Xu <herbert< at >gondor.apana.org.au>
< at >< at > -37,6 +37,7 < at >< at >
 #include <linux/io.h>
 #include <linux/spinlock.h>
 #include <linux/rtnetlink.h>
+#include <linux/netdevice.h>
 #include <linux/slab.h>
 
 #include <crypto/algapi.h>
< at >< at > -121,6 +122,7 < at >< at > struct talitos_channel {
 struct talitos_private {
 struct device *dev;
 struct platform_device *ofdev;
+struct net_device __percpu *netdev;
 void __iomem *reg;
 int irq[2];
 
< at >< at > -148,8 +150,8 < at >< at > struct talitos_private {
 /* next channel to be assigned next incoming descriptor */
 atomic_t last_chan ____cacheline_aligned;
 
-/* request callback tasklet */
-struct tasklet_struct done_task[2];
+/* request callback napi */
+struct napi_struct __percpu *done_task[2];
 
 /* list of registered algorithms */
 struct list_head alg_list;
< at >< at > -352,17 +354,18 < at >< at > static int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc,
 /*
  * process what was done, notify callback of error if not
  */
-static void flush_channel(struct device *dev, int ch, int error, int reset_ch)
+static int flush_channel(struct device *dev, int ch, int error, int reset_ch,
+ int weight)
 {
 struct talitos_private *priv = dev_get_drvdata(dev);
 struct talitos_request *request, saved_req;
 unsigned long flags;
-int tail, status;
+int tail, status, count = 0;
 
 spin_lock_irqsave(&priv->chan[ch].tail_lock, flags);
 
 tail = priv->chan[ch].tail;
-while (priv->chan[ch].fifo[tail].desc) {
+while (priv->chan[ch].fifo[tail].desc && (count < weight)) {
 request = &priv->chan[ch].fifo[tail];
 
 /* descriptors with their done bits set don't get the error */
< at >< at > -399,46 +402,57 < at >< at > static void flush_channel(struct device *dev, int ch, int error, int reset_ch)
    status);
 /* channel may resume processing in single desc error case */
 if (error && !reset_ch && status == error)
-return;
+return 0;
+count++;
 spin_lock_irqsave(&priv->chan[ch].tail_lock, flags);
 tail = priv->chan[ch].tail;
 }
 
 spin_unlock_irqrestore(&priv->chan[ch].tail_lock, flags);
+
+return count;
 }
 
 /*
  * process completed requests for channels that have done status
  */
-#define DEF_TALITOS_DONE(name, ch_done_mask)\
-static void talitos_done_##name(unsigned long data)\
+#define DEF_TALITOS_DONE(name, ch_done_mask, num_ch)\
+static int talitos_done_##name(struct napi_struct *napi, int budget)\
 {\
-struct device *dev = (struct device *)data;\
+struct device *dev = &napi->dev->dev;\
 struct talitos_private *priv = dev_get_drvdata(dev);\
+int budget_per_ch = budget / num_ch, work_done = 0;\
 unsigned long flags;\
 \
 if (ch_done_mask & 1)\
-flush_channel(dev, 0, 0, 0);\
+work_done += flush_channel(dev, 0, 0, 0, budget_per_ch);\
 if (priv->num_channels == 1)\
 goto out;\
 if (ch_done_mask & (1 << 2))\
-flush_channel(dev, 1, 0, 0);\
+work_done += flush_channel(dev, 1, 0, 0, budget_per_ch);\
 if (ch_done_mask & (1 << 4))\
-flush_channel(dev, 2, 0, 0);\
+work_done += flush_channel(dev, 2, 0, 0, budget_per_ch);\
 if (ch_done_mask & (1 << 6))\
-flush_channel(dev, 3, 0, 0);\
+work_done += flush_channel(dev, 3, 0, 0, budget_per_ch);\
 \
 out:\
-/* At this point, all completed channels have been processed */\
-/* Unmask done interrupts for channels completed later on. */\
-spin_lock_irqsave(&priv->reg_lock, flags);\
-setbits32(priv->reg + TALITOS_IMR, ch_done_mask);\
-setbits32(priv->reg + TALITOS_IMR_LO, TALITOS_IMR_LO_INIT);\
-spin_unlock_irqrestore(&priv->reg_lock, flags);\
+if (work_done < budget) {\
+napi_complete(napi);\
+/* At this point, all completed channels have been */\
+/* processed. Unmask done interrupts for channels */\
+/* completed later on. */\
+spin_lock_irqsave(&priv->reg_lock, flags);\
+setbits32(priv->reg + TALITOS_IMR, ch_done_mask);\
+setbits32(priv->reg + TALITOS_IMR_LO,\
+  TALITOS_IMR_LO_INIT);\
+spin_unlock_irqrestore(&priv->reg_lock, flags);\
+}\
+\
+return work_done;\
 }
-DEF_TALITOS_DONE(4ch, TALITOS_ISR_4CHDONE)
-DEF_TALITOS_DONE(ch0_2, TALITOS_ISR_CH_0_2_DONE)
-DEF_TALITOS_DONE(ch1_3, TALITOS_ISR_CH_1_3_DONE)
+DEF_TALITOS_DONE(4ch, TALITOS_ISR_4CHDONE, 4)
+DEF_TALITOS_DONE(ch0_2, TALITOS_ISR_CH_0_2_DONE, 2)
+DEF_TALITOS_DONE(ch1_3, TALITOS_ISR_CH_1_3_DONE, 2)
 
 /*
  * locate current (offending) descriptor
< at >< at > -588,7 +602,7 < at >< at > static void talitos_error(struct device *dev, u32 isr, u32 isr_lo)
 if (v_lo & TALITOS_CCPSR_LO_SRL)
 dev_err(dev, "scatter return/length error\n");
 
-flush_channel(dev, ch, error, reset_ch);
+flush_channel(dev, ch, error, reset_ch, priv->fifo_len);
 
 if (reset_ch) {
 reset_channel(dev, ch);
< at >< at > -612,14 +626,14 < at >< at > static void talitos_error(struct device *dev, u32 isr, u32 isr_lo)
 
 /* purge request queues */
 for (ch = 0; ch < priv->num_channels; ch++)
-flush_channel(dev, ch, -EIO, 1);
+flush_channel(dev, ch, -EIO, 1, priv->fifo_len);
 
 /* reset and reinitialize the device */
 init_device(dev);
 }
 }
 
-#define DEF_TALITOS_INTERRUPT(name, ch_done_mask, ch_err_mask, tlet)       \
+#define DEF_TALITOS_INTERRUPT(name, ch_done_mask, ch_err_mask, sirq)       \
 static irqreturn_t talitos_interrupt_##name(int irq, void *data)       \
 {       \
 struct device *dev = data;       \
< at >< at > -643,7 +657,8 < at >< at > static irqreturn_t talitos_interrupt_##name(int irq, void *data)       \
 /* mask further done interrupts. */       \
 clrbits32(priv->reg + TALITOS_IMR, ch_done_mask);      \
 /* done_task will unmask done interrupts at exit */    \
-tasklet_schedule(&priv->done_task[tlet]);       \
+napi_schedule(per_cpu_ptr(priv->done_task[sirq],       \
+  smp_processor_id()));       \
 }       \
 spin_unlock_irqrestore(&priv->reg_lock, flags);       \
 }       \
< at >< at > -2567,7 +2582,7 < at >< at > static int talitos_remove(struct platform_device *ofdev)
 struct device *dev = &ofdev->dev;
 struct talitos_private *priv = dev_get_drvdata(dev);
 struct talitos_crypto_alg *t_alg, *n;
-int i;
+int i, j;
 
 list_for_each_entry_safe(t_alg, n, &priv->alg_list, entry) {
 switch (t_alg->algt.type) {
< at >< at > -2586,25 +2601,32 < at >< at > static int talitos_remove(struct platform_device *ofdev)
 if (hw_supports(dev, DESC_HDR_SEL0_RNG))
 talitos_unregister_rng(dev);
 
-for (i = 0; i < priv->num_channels; i++)
-kfree(priv->chan[i].fifo);
-
-kfree(priv->chan);
-
 for (i = 0; i < 2; i++)
 if (priv->irq[i]) {
 free_irq(priv->irq[i], dev);
 irq_dispose_mapping(priv->irq[i]);
+
+for_each_possible_cpu(j) {
+napi_disable(per_cpu_ptr(priv->done_task[i],
+ j));
+netif_napi_del(per_cpu_ptr(priv->done_task[i],
+   j));
+}
+
+free_percpu(priv->done_task[i]);
 }
 
-tasklet_kill(&priv->done_task[0]);
-if (priv->irq[1])
-tasklet_kill(&priv->done_task[1]);
+for (i = 0; i < priv->num_channels; i++)
+kfree(priv->chan[i].fifo);
+
+kfree(priv->chan);
 
 iounmap(priv->reg);
 
 dev_set_drvdata(dev, NULL);
 
+free_percpu(priv->netdev);
+
 kfree(priv);
 
 return 0;
< at >< at > -2730,21 +2752,63 < at >< at > static int talitos_probe(struct platform_device *ofdev)
 dev_set_drvdata(dev, priv);
 
 priv->ofdev = ofdev;
+priv->dev = dev;
 
 spin_lock_init(&priv->reg_lock);
 
+priv->netdev = alloc_percpu(struct net_device);
+if (!priv->netdev) {
+dev_err(dev, "failed to allocate netdevice\n");
+err = -ENOMEM;
+goto err_out;
+}
+
+for_each_possible_cpu(i) {
+err = init_dummy_netdev(per_cpu_ptr(priv->netdev, i));
+if (err) {
+dev_err(dev, "failed to initialize dummy netdevice\n");
+goto err_out;
+}
+(per_cpu_ptr(priv->netdev, i))->dev = *dev;
+}
+
 err = talitos_probe_irq(ofdev);
 if (err)
 goto err_out;
 
+priv->done_task[0] = alloc_percpu(struct napi_struct);
+if (!priv->done_task[0]) {
+dev_err(dev, "failed to allocate napi for 1st irq\n");
+err = -ENOMEM;
+goto err_out;
+}
+
 if (!priv->irq[1]) {
-tasklet_init(&priv->done_task[0], talitos_done_4ch,
-     (unsigned long)dev);
+for_each_possible_cpu(i) {
+netif_napi_add(per_cpu_ptr(priv->netdev, i),
+       per_cpu_ptr(priv->done_task[0], i),
+talitos_done_4ch, TALITOS_NAPI_WEIGHT);
+napi_enable(per_cpu_ptr(priv->done_task[0], i));
+}
 } else {
-tasklet_init(&priv->done_task[0], talitos_done_ch0_2,
-     (unsigned long)dev);
-tasklet_init(&priv->done_task[1], talitos_done_ch1_3,
-     (unsigned long)dev);
+priv->done_task[1] = alloc_percpu(struct napi_struct);
+if (!priv->done_task[1]) {
+dev_err(dev, "failed to allocate napi for 2nd irq\n");
+err = -ENOMEM;
+goto err_out;
+}
+
+for_each_possible_cpu(i) {
+netif_napi_add(per_cpu_ptr(priv->netdev, i),
+       per_cpu_ptr(priv->done_task[0], i),
+       talitos_done_ch0_2, TALITOS_NAPI_WEIGHT);
+napi_enable(per_cpu_ptr(priv->done_task[0], i));
+
+netif_napi_add(per_cpu_ptr(priv->netdev, i),
+       per_cpu_ptr(priv->done_task[1], i),
+       talitos_done_ch1_3, TALITOS_NAPI_WEIGHT);
+napi_enable(per_cpu_ptr(priv->done_task[1], i));
+}
 }
 
 INIT_LIST_HEAD(&priv->alg_list);
diff --git a/drivers/crypto/talitos.h b/drivers/crypto/talitos.h
index 3c17395..3fe0e36 100644
--- a/drivers/crypto/talitos.h
+++ b/drivers/crypto/talitos.h
< at >< at > -1,7 +1,7 < at >< at >
 /*
  * Freescale SEC (talitos) device register and descriptor header defines
  *
- * Copyright (c) 2006-2011 Freescale Semiconductor, Inc.
+ * Copyright (c) 2006-2012 Freescale Semiconductor, Inc.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
< at >< at > -28,6 +28,8 < at >< at >
  *
  */
 
+#define TALITOS_NAPI_WEIGHT22
+
 /*
  * TALITOS_xxx_LO addresses point to the low data bits (32-63) of the register
  */

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2012-05-15T19:35:20

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Mr.Saeed Ahmed. — 2012-05-09T06:27:58


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CRYPTO_ALG_TYPE_ABLKCIPHER concepts guide

Rodel Miguel — 2012-05-14T04:46:52

Hello Experts,

I am writing a driver for my AES encryption hardware.  It is a
hardware which can do encryption of 4k bytes of data every time.  I
have tried creating a driver based on geode-aes.c code which uses the
CRYPTO_ALG_TYPE_BLKCIPHER interface.  While testing the driver, I
found out that the limit for this type of API is 512 bytes of data
sent on every encryption/decryption call.  I have sent the dm-crypt
mailing list a query about this and they said that this limit cannot
be changed at the moment.

I am now looking at a different type of crypto API which is the
CRYPTO_ALG_TYPE_ABLKCIPHER but I could not find any
tutorials/documentation which would guide to the minimum code required
to create this type of driver.  I looked at the mv_cesa.c but I am
still quite lost at the procedures in doing this type of driver.  The
reason I want to explore this driver is that I am assuming that the
CRYPTO_ALG_TYPE_ABLKCIPHER type of interface would allow me to collect
4k bytes of data first before doing DMA to my hardware for
encryption/decryption.  Is this a correct assumption?

Is there a good documentation that would lay out the requirements to
write an asynchronous type of block cipher?

Thank you very much for your help!

Kind Regards,
Rodel

haalloo,

abi — 2012-05-12T16:57:06

haalloo,
how are you doing,i hope you are fine,my name is miss abi okom i got your
contact and want us to be a good friend,
please try and write back to me so that i will give you my pictures and tell
you more about me,

[PATCH] crypto: mv_cesa requires on CRYPTO_HASH to build

Alexander Clouter — 2012-05-12T08:45:08

Without CRYPTO_HASH being selected, mv_cesa has a lot of hooks
into undefined exports.
----
  MODPOST 81 modules
  Kernel: arch/arm/boot/Image is ready
  AS      arch/arm/boot/compressed/head.o
  GZIP    arch/arm/boot/compressed/piggy.gzip
  CC      arch/arm/boot/compressed/misc.o
  CC      arch/arm/boot/compressed/decompress.o
ERROR: "crypto_ahash_type" [drivers/crypto/mv_cesa.ko] undefined!
ERROR: "crypto_shash_final" [drivers/crypto/mv_cesa.ko] undefined!
ERROR: "crypto_register_ahash" [drivers/crypto/mv_cesa.ko] undefined!
ERROR: "crypto_unregister_ahash" [drivers/crypto/mv_cesa.ko] undefined!
ERROR: "crypto_shash_update" [drivers/crypto/mv_cesa.ko] undefined!
ERROR: "crypto_shash_digest" [drivers/crypto/mv_cesa.ko] undefined!
ERROR: "crypto_shash_setkey" [drivers/crypto/mv_cesa.ko] undefined!
ERROR: "crypto_alloc_shash" [drivers/crypto/mv_cesa.ko] undefined!
make[1]: *** [__modpost] Error 1
make: *** [modules] Error 2
make: *** Waiting for unfinished jobs....
----

Signed-off-by: Alexander Clouter <alex< at >digriz.org.uk>
---
 drivers/crypto/Kconfig |    1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index e707979..07dbc77 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
< at >< at > -173,6 +173,7 < at >< at > config CRYPTO_DEV_MV_CESA
 select CRYPTO_ALGAPI
 select CRYPTO_AES
 select CRYPTO_BLKCIPHER2
+select CRYPTO_HASH
 help
   This driver allows you to utilize the Cryptographic Engines and
   Security Accelerator (CESA) which can be found on the Marvell Orion

Writing Asynchronous Block Ciphers

Rodel Miguel — 2012-05-11T16:58:24

Hello,

I would like to know if anyone has a tutorial/document link in writing
a CRYPTO_ALG_TYPE_ABLKCIPHER crypto device driver?  I am looking at
drivers/cipher/mv_cesa.c but there are lots of things going on which
are hardware context related.  I would like to know what the minimum
requirements for an asynchronous block cipher drivers are before I
hand over (DMA) the collected data to my encryption hardware.

Thanks in advance for your help!

Kind Regards,
Rodel

[PATCH 1/2] crypto: aesni-intel: use crypto_[un]register_algs

Jussi Kivilinna — 2012-05-11T13:00:48

Combine all crypto_alg to be registered and use new crypto_[un]register_algs
functions. Simplifies init/exit code and reduce object size.

Cc: Huang Ying <ying.huang< at >intel.com>
Signed-off-by: Jussi Kivilinna <jussi.kivilinna< at >mbnet.fi>
---
 arch/x86/crypto/aesni-intel_glue.c |  727 +++++++++++++++---------------------
 1 file changed, 305 insertions(+), 422 deletions(-)

diff --git a/arch/x86/crypto/aesni-intel_glue.c b/arch/x86/crypto/aesni-intel_glue.c
index c799352..20c6220 100644
--- a/arch/x86/crypto/aesni-intel_glue.c
+++ b/arch/x86/crypto/aesni-intel_glue.c
< at >< at > -222,27 +222,6 < at >< at > static void aes_decrypt(struct crypto_tfm *tfm, u8 *dst, const u8 *src)
 }
 }
 
-static struct crypto_alg aesni_alg = {
-.cra_name= "aes",
-.cra_driver_name= "aes-aesni",
-.cra_priority= 300,
-.cra_flags= CRYPTO_ALG_TYPE_CIPHER,
-.cra_blocksize= AES_BLOCK_SIZE,
-.cra_ctxsize= sizeof(struct crypto_aes_ctx)+AESNI_ALIGN-1,
-.cra_alignmask= 0,
-.cra_module= THIS_MODULE,
-.cra_list= LIST_HEAD_INIT(aesni_alg.cra_list),
-.cra_u= {
-.cipher= {
-.cia_min_keysize= AES_MIN_KEY_SIZE,
-.cia_max_keysize= AES_MAX_KEY_SIZE,
-.cia_setkey= aes_set_key,
-.cia_encrypt= aes_encrypt,
-.cia_decrypt= aes_decrypt
-}
-}
-};
-
 static void __aes_encrypt(struct crypto_tfm *tfm, u8 *dst, const u8 *src)
 {
 struct crypto_aes_ctx *ctx = aes_ctx(crypto_tfm_ctx(tfm));
< at >< at > -257,27 +236,6 < at >< at > static void __aes_decrypt(struct crypto_tfm *tfm, u8 *dst, const u8 *src)
 aesni_dec(ctx, dst, src);
 }
 
-static struct crypto_alg __aesni_alg = {
-.cra_name= "__aes-aesni",
-.cra_driver_name= "__driver-aes-aesni",
-.cra_priority= 0,
-.cra_flags= CRYPTO_ALG_TYPE_CIPHER,
-.cra_blocksize= AES_BLOCK_SIZE,
-.cra_ctxsize= sizeof(struct crypto_aes_ctx)+AESNI_ALIGN-1,
-.cra_alignmask= 0,
-.cra_module= THIS_MODULE,
-.cra_list= LIST_HEAD_INIT(__aesni_alg.cra_list),
-.cra_u= {
-.cipher= {
-.cia_min_keysize= AES_MIN_KEY_SIZE,
-.cia_max_keysize= AES_MAX_KEY_SIZE,
-.cia_setkey= aes_set_key,
-.cia_encrypt= __aes_encrypt,
-.cia_decrypt= __aes_decrypt
-}
-}
-};
-
 static int ecb_encrypt(struct blkcipher_desc *desc,
        struct scatterlist *dst, struct scatterlist *src,
        unsigned int nbytes)
< at >< at > -326,28 +284,6 < at >< at > static int ecb_decrypt(struct blkcipher_desc *desc,
 return err;
 }
 
-static struct crypto_alg blk_ecb_alg = {
-.cra_name= "__ecb-aes-aesni",
-.cra_driver_name= "__driver-ecb-aes-aesni",
-.cra_priority= 0,
-.cra_flags= CRYPTO_ALG_TYPE_BLKCIPHER,
-.cra_blocksize= AES_BLOCK_SIZE,
-.cra_ctxsize= sizeof(struct crypto_aes_ctx)+AESNI_ALIGN-1,
-.cra_alignmask= 0,
-.cra_type= &crypto_blkcipher_type,
-.cra_module= THIS_MODULE,
-.cra_list= LIST_HEAD_INIT(blk_ecb_alg.cra_list),
-.cra_u = {
-.blkcipher = {
-.min_keysize= AES_MIN_KEY_SIZE,
-.max_keysize= AES_MAX_KEY_SIZE,
-.setkey= aes_set_key,
-.encrypt= ecb_encrypt,
-.decrypt= ecb_decrypt,
-},
-},
-};
-
 static int cbc_encrypt(struct blkcipher_desc *desc,
        struct scatterlist *dst, struct scatterlist *src,
        unsigned int nbytes)
< at >< at > -396,28 +332,6 < at >< at > static int cbc_decrypt(struct blkcipher_desc *desc,
 return err;
 }
 
-static struct crypto_alg blk_cbc_alg = {
-.cra_name= "__cbc-aes-aesni",
-.cra_driver_name= "__driver-cbc-aes-aesni",
-.cra_priority= 0,
-.cra_flags= CRYPTO_ALG_TYPE_BLKCIPHER,
-.cra_blocksize= AES_BLOCK_SIZE,
-.cra_ctxsize= sizeof(struct crypto_aes_ctx)+AESNI_ALIGN-1,
-.cra_alignmask= 0,
-.cra_type= &crypto_blkcipher_type,
-.cra_module= THIS_MODULE,
-.cra_list= LIST_HEAD_INIT(blk_cbc_alg.cra_list),
-.cra_u = {
-.blkcipher = {
-.min_keysize= AES_MIN_KEY_SIZE,
-.max_keysize= AES_MAX_KEY_SIZE,
-.setkey= aes_set_key,
-.encrypt= cbc_encrypt,
-.decrypt= cbc_decrypt,
-},
-},
-};
-
 #ifdef CONFIG_X86_64
 static void ctr_crypt_final(struct crypto_aes_ctx *ctx,
     struct blkcipher_walk *walk)
< at >< at > -461,29 +375,6 < at >< at > static int ctr_crypt(struct blkcipher_desc *desc,
 
 return err;
 }
-
-static struct crypto_alg blk_ctr_alg = {
-.cra_name= "__ctr-aes-aesni",
-.cra_driver_name= "__driver-ctr-aes-aesni",
-.cra_priority= 0,
-.cra_flags= CRYPTO_ALG_TYPE_BLKCIPHER,
-.cra_blocksize= 1,
-.cra_ctxsize= sizeof(struct crypto_aes_ctx)+AESNI_ALIGN-1,
-.cra_alignmask= 0,
-.cra_type= &crypto_blkcipher_type,
-.cra_module= THIS_MODULE,
-.cra_list= LIST_HEAD_INIT(blk_ctr_alg.cra_list),
-.cra_u = {
-.blkcipher = {
-.min_keysize= AES_MIN_KEY_SIZE,
-.max_keysize= AES_MAX_KEY_SIZE,
-.ivsize= AES_BLOCK_SIZE,
-.setkey= aes_set_key,
-.encrypt= ctr_crypt,
-.decrypt= ctr_crypt,
-},
-},
-};
 #endif
 
 static int ablk_set_key(struct crypto_ablkcipher *tfm, const u8 *key,
< at >< at > -572,30 +463,6 < at >< at > static int ablk_ecb_init(struct crypto_tfm *tfm)
 return 0;
 }
 
-static struct crypto_alg ablk_ecb_alg = {
-.cra_name= "ecb(aes)",
-.cra_driver_name= "ecb-aes-aesni",
-.cra_priority= 400,
-.cra_flags= CRYPTO_ALG_TYPE_ABLKCIPHER|CRYPTO_ALG_ASYNC,
-.cra_blocksize= AES_BLOCK_SIZE,
-.cra_ctxsize= sizeof(struct async_aes_ctx),
-.cra_alignmask= 0,
-.cra_type= &crypto_ablkcipher_type,
-.cra_module= THIS_MODULE,
-.cra_list= LIST_HEAD_INIT(ablk_ecb_alg.cra_list),
-.cra_init= ablk_ecb_init,
-.cra_exit= ablk_exit,
-.cra_u = {
-.ablkcipher = {
-.min_keysize= AES_MIN_KEY_SIZE,
-.max_keysize= AES_MAX_KEY_SIZE,
-.setkey= ablk_set_key,
-.encrypt= ablk_encrypt,
-.decrypt= ablk_decrypt,
-},
-},
-};
-
 static int ablk_cbc_init(struct crypto_tfm *tfm)
 {
 struct cryptd_ablkcipher *cryptd_tfm;
< at >< at > -607,31 +474,6 < at >< at > static int ablk_cbc_init(struct crypto_tfm *tfm)
 return 0;
 }
 
-static struct crypto_alg ablk_cbc_alg = {
-.cra_name= "cbc(aes)",
-.cra_driver_name= "cbc-aes-aesni",
-.cra_priority= 400,
-.cra_flags= CRYPTO_ALG_TYPE_ABLKCIPHER|CRYPTO_ALG_ASYNC,
-.cra_blocksize= AES_BLOCK_SIZE,
-.cra_ctxsize= sizeof(struct async_aes_ctx),
-.cra_alignmask= 0,
-.cra_type= &crypto_ablkcipher_type,
-.cra_module= THIS_MODULE,
-.cra_list= LIST_HEAD_INIT(ablk_cbc_alg.cra_list),
-.cra_init= ablk_cbc_init,
-.cra_exit= ablk_exit,
-.cra_u = {
-.ablkcipher = {
-.min_keysize= AES_MIN_KEY_SIZE,
-.max_keysize= AES_MAX_KEY_SIZE,
-.ivsize= AES_BLOCK_SIZE,
-.setkey= ablk_set_key,
-.encrypt= ablk_encrypt,
-.decrypt= ablk_decrypt,
-},
-},
-};
-
 #ifdef CONFIG_X86_64
 static int ablk_ctr_init(struct crypto_tfm *tfm)
 {
< at >< at > -644,32 +486,6 < at >< at > static int ablk_ctr_init(struct crypto_tfm *tfm)
 return 0;
 }
 
-static struct crypto_alg ablk_ctr_alg = {
-.cra_name= "ctr(aes)",
-.cra_driver_name= "ctr-aes-aesni",
-.cra_priority= 400,
-.cra_flags= CRYPTO_ALG_TYPE_ABLKCIPHER|CRYPTO_ALG_ASYNC,
-.cra_blocksize= 1,
-.cra_ctxsize= sizeof(struct async_aes_ctx),
-.cra_alignmask= 0,
-.cra_type= &crypto_ablkcipher_type,
-.cra_module= THIS_MODULE,
-.cra_list= LIST_HEAD_INIT(ablk_ctr_alg.cra_list),
-.cra_init= ablk_ctr_init,
-.cra_exit= ablk_exit,
-.cra_u = {
-.ablkcipher = {
-.min_keysize= AES_MIN_KEY_SIZE,
-.max_keysize= AES_MAX_KEY_SIZE,
-.ivsize= AES_BLOCK_SIZE,
-.setkey= ablk_set_key,
-.encrypt= ablk_encrypt,
-.decrypt= ablk_encrypt,
-.geniv= "chainiv",
-},
-},
-};
-
 #ifdef HAS_CTR
 static int ablk_rfc3686_ctr_init(struct crypto_tfm *tfm)
 {
< at >< at > -682,32 +498,6 < at >< at > static int ablk_rfc3686_ctr_init(struct crypto_tfm *tfm)
 ablk_init_common(tfm, cryptd_tfm);
 return 0;
 }
-
-static struct crypto_alg ablk_rfc3686_ctr_alg = {
-.cra_name= "rfc3686(ctr(aes))",
-.cra_driver_name= "rfc3686-ctr-aes-aesni",
-.cra_priority= 400,
-.cra_flags= CRYPTO_ALG_TYPE_ABLKCIPHER|CRYPTO_ALG_ASYNC,
-.cra_blocksize= 1,
-.cra_ctxsize= sizeof(struct async_aes_ctx),
-.cra_alignmask= 0,
-.cra_type= &crypto_ablkcipher_type,
-.cra_module= THIS_MODULE,
-.cra_list= LIST_HEAD_INIT(ablk_rfc3686_ctr_alg.cra_list),
-.cra_init= ablk_rfc3686_ctr_init,
-.cra_exit= ablk_exit,
-.cra_u = {
-.ablkcipher = {
-.min_keysize = AES_MIN_KEY_SIZE+CTR_RFC3686_NONCE_SIZE,
-.max_keysize = AES_MAX_KEY_SIZE+CTR_RFC3686_NONCE_SIZE,
-.ivsize     = CTR_RFC3686_IV_SIZE,
-.setkey     = ablk_set_key,
-.encrypt     = ablk_encrypt,
-.decrypt     = ablk_decrypt,
-.geniv     = "seqiv",
-},
-},
-};
 #endif
 #endif
 
< at >< at > -723,31 +513,6 < at >< at > static int ablk_lrw_init(struct crypto_tfm *tfm)
 ablk_init_common(tfm, cryptd_tfm);
 return 0;
 }
-
-static struct crypto_alg ablk_lrw_alg = {
-.cra_name= "lrw(aes)",
-.cra_driver_name= "lrw-aes-aesni",
-.cra_priority= 400,
-.cra_flags= CRYPTO_ALG_TYPE_ABLKCIPHER|CRYPTO_ALG_ASYNC,
-.cra_blocksize= AES_BLOCK_SIZE,
-.cra_ctxsize= sizeof(struct async_aes_ctx),
-.cra_alignmask= 0,
-.cra_type= &crypto_ablkcipher_type,
-.cra_module= THIS_MODULE,
-.cra_list= LIST_HEAD_INIT(ablk_lrw_alg.cra_list),
-.cra_init= ablk_lrw_init,
-.cra_exit= ablk_exit,
-.cra_u = {
-.ablkcipher = {
-.min_keysize= AES_MIN_KEY_SIZE + AES_BLOCK_SIZE,
-.max_keysize= AES_MAX_KEY_SIZE + AES_BLOCK_SIZE,
-.ivsize= AES_BLOCK_SIZE,
-.setkey= ablk_set_key,
-.encrypt= ablk_encrypt,
-.decrypt= ablk_decrypt,
-},
-},
-};
 #endif
 
 #ifdef HAS_PCBC
< at >< at > -762,31 +527,6 < at >< at > static int ablk_pcbc_init(struct crypto_tfm *tfm)
 ablk_init_common(tfm, cryptd_tfm);
 return 0;
 }
-
-static struct crypto_alg ablk_pcbc_alg = {
-.cra_name= "pcbc(aes)",
-.cra_driver_name= "pcbc-aes-aesni",
-.cra_priority= 400,
-.cra_flags= CRYPTO_ALG_TYPE_ABLKCIPHER|CRYPTO_ALG_ASYNC,
-.cra_blocksize= AES_BLOCK_SIZE,
-.cra_ctxsize= sizeof(struct async_aes_ctx),
-.cra_alignmask= 0,
-.cra_type= &crypto_ablkcipher_type,
-.cra_module= THIS_MODULE,
-.cra_list= LIST_HEAD_INIT(ablk_pcbc_alg.cra_list),
-.cra_init= ablk_pcbc_init,
-.cra_exit= ablk_exit,
-.cra_u = {
-.ablkcipher = {
-.min_keysize= AES_MIN_KEY_SIZE,
-.max_keysize= AES_MAX_KEY_SIZE,
-.ivsize= AES_BLOCK_SIZE,
-.setkey= ablk_set_key,
-.encrypt= ablk_encrypt,
-.decrypt= ablk_decrypt,
-},
-},
-};
 #endif
 
 #ifdef HAS_XTS
< at >< at > -801,31 +541,6 < at >< at > static int ablk_xts_init(struct crypto_tfm *tfm)
 ablk_init_common(tfm, cryptd_tfm);
 return 0;
 }
-
-static struct crypto_alg ablk_xts_alg = {
-.cra_name= "xts(aes)",
-.cra_driver_name= "xts-aes-aesni",
-.cra_priority= 400,
-.cra_flags= CRYPTO_ALG_TYPE_ABLKCIPHER|CRYPTO_ALG_ASYNC,
-.cra_blocksize= AES_BLOCK_SIZE,
-.cra_ctxsize= sizeof(struct async_aes_ctx),
-.cra_alignmask= 0,
-.cra_type= &crypto_ablkcipher_type,
-.cra_module= THIS_MODULE,
-.cra_list= LIST_HEAD_INIT(ablk_xts_alg.cra_list),
-.cra_init= ablk_xts_init,
-.cra_exit= ablk_exit,
-.cra_u = {
-.ablkcipher = {
-.min_keysize= 2 * AES_MIN_KEY_SIZE,
-.max_keysize= 2 * AES_MAX_KEY_SIZE,
-.ivsize= AES_BLOCK_SIZE,
-.setkey= ablk_set_key,
-.encrypt= ablk_encrypt,
-.decrypt= ablk_decrypt,
-},
-},
-};
 #endif
 
 #ifdef CONFIG_X86_64
< at >< at > -1050,32 +765,6 < at >< at > static int rfc4106_decrypt(struct aead_request *req)
 }
 }
 
-static struct crypto_alg rfc4106_alg = {
-.cra_name = "rfc4106(gcm(aes))",
-.cra_driver_name = "rfc4106-gcm-aesni",
-.cra_priority = 400,
-.cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
-.cra_blocksize = 1,
-.cra_ctxsize = sizeof(struct aesni_rfc4106_gcm_ctx) + AESNI_ALIGN,
-.cra_alignmask = 0,
-.cra_type = &crypto_nivaead_type,
-.cra_module = THIS_MODULE,
-.cra_list = LIST_HEAD_INIT(rfc4106_alg.cra_list),
-.cra_init = rfc4106_init,
-.cra_exit = rfc4106_exit,
-.cra_u = {
-.aead = {
-.setkey = rfc4106_set_key,
-.setauthsize = rfc4106_set_authsize,
-.encrypt = rfc4106_encrypt,
-.decrypt = rfc4106_decrypt,
-.geniv = "seqiv",
-.ivsize = 8,
-.maxauthsize = 16,
-},
-},
-};
-
 static int __driver_rfc4106_encrypt(struct aead_request *req)
 {
 u8 one_entry_in_sg = 0;
< at >< at > -1233,26 +922,316 < at >< at > static int __driver_rfc4106_decrypt(struct aead_request *req)
 }
 return retval;
 }
+#endif
 
-static struct crypto_alg __rfc4106_alg = {
-.cra_name= "__gcm-aes-aesni",
-.cra_driver_name= "__driver-gcm-aes-aesni",
+static struct crypto_alg aesni_algs[] = { {
+.cra_name= "aes",
+.cra_driver_name= "aes-aesni",
+.cra_priority= 300,
+.cra_flags= CRYPTO_ALG_TYPE_CIPHER,
+.cra_blocksize= AES_BLOCK_SIZE,
+.cra_ctxsize= sizeof(struct crypto_aes_ctx) +
+  AESNI_ALIGN - 1,
+.cra_alignmask= 0,
+.cra_module= THIS_MODULE,
+.cra_u= {
+.cipher= {
+.cia_min_keysize= AES_MIN_KEY_SIZE,
+.cia_max_keysize= AES_MAX_KEY_SIZE,
+.cia_setkey= aes_set_key,
+.cia_encrypt= aes_encrypt,
+.cia_decrypt= aes_decrypt
+}
+}
+}, {
+.cra_name= "__aes-aesni",
+.cra_driver_name= "__driver-aes-aesni",
+.cra_priority= 0,
+.cra_flags= CRYPTO_ALG_TYPE_CIPHER,
+.cra_blocksize= AES_BLOCK_SIZE,
+.cra_ctxsize= sizeof(struct crypto_aes_ctx) +
+  AESNI_ALIGN - 1,
+.cra_alignmask= 0,
+.cra_module= THIS_MODULE,
+.cra_u= {
+.cipher= {
+.cia_min_keysize= AES_MIN_KEY_SIZE,
+.cia_max_keysize= AES_MAX_KEY_SIZE,
+.cia_setkey= aes_set_key,
+.cia_encrypt= __aes_encrypt,
+.cia_decrypt= __aes_decrypt
+}
+}
+}, {
+.cra_name= "__ecb-aes-aesni",
+.cra_driver_name= "__driver-ecb-aes-aesni",
+.cra_priority= 0,
+.cra_flags= CRYPTO_ALG_TYPE_BLKCIPHER,
+.cra_blocksize= AES_BLOCK_SIZE,
+.cra_ctxsize= sizeof(struct crypto_aes_ctx) +
+  AESNI_ALIGN - 1,
+.cra_alignmask= 0,
+.cra_type= &crypto_blkcipher_type,
+.cra_module= THIS_MODULE,
+.cra_u = {
+.blkcipher = {
+.min_keysize= AES_MIN_KEY_SIZE,
+.max_keysize= AES_MAX_KEY_SIZE,
+.setkey= aes_set_key,
+.encrypt= ecb_encrypt,
+.decrypt= ecb_decrypt,
+},
+},
+}, {
+.cra_name= "__cbc-aes-aesni",
+.cra_driver_name= "__driver-cbc-aes-aesni",
+.cra_priority= 0,
+.cra_flags= CRYPTO_ALG_TYPE_BLKCIPHER,
+.cra_blocksize= AES_BLOCK_SIZE,
+.cra_ctxsize= sizeof(struct crypto_aes_ctx) +
+  AESNI_ALIGN - 1,
+.cra_alignmask= 0,
+.cra_type= &crypto_blkcipher_type,
+.cra_module= THIS_MODULE,
+.cra_u = {
+.blkcipher = {
+.min_keysize= AES_MIN_KEY_SIZE,
+.max_keysize= AES_MAX_KEY_SIZE,
+.setkey= aes_set_key,
+.encrypt= cbc_encrypt,
+.decrypt= cbc_decrypt,
+},
+},
+}, {
+.cra_name= "ecb(aes)",
+.cra_driver_name= "ecb-aes-aesni",
+.cra_priority= 400,
+.cra_flags= CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+.cra_blocksize= AES_BLOCK_SIZE,
+.cra_ctxsize= sizeof(struct async_aes_ctx),
+.cra_alignmask= 0,
+.cra_type= &crypto_ablkcipher_type,
+.cra_module= THIS_MODULE,
+.cra_init= ablk_ecb_init,
+.cra_exit= ablk_exit,
+.cra_u = {
+.ablkcipher = {
+.min_keysize= AES_MIN_KEY_SIZE,
+.max_keysize= AES_MAX_KEY_SIZE,
+.setkey= ablk_set_key,
+.encrypt= ablk_encrypt,
+.decrypt= ablk_decrypt,
+},
+},
+}, {
+.cra_name= "cbc(aes)",
+.cra_driver_name= "cbc-aes-aesni",
+.cra_priority= 400,
+.cra_flags= CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+.cra_blocksize= AES_BLOCK_SIZE,
+.cra_ctxsize= sizeof(struct async_aes_ctx),
+.cra_alignmask= 0,
+.cra_type= &crypto_ablkcipher_type,
+.cra_module= THIS_MODULE,
+.cra_init= ablk_cbc_init,
+.cra_exit= ablk_exit,
+.cra_u = {
+.ablkcipher = {
+.min_keysize= AES_MIN_KEY_SIZE,
+.max_keysize= AES_MAX_KEY_SIZE,
+.ivsize= AES_BLOCK_SIZE,
+.setkey= ablk_set_key,
+.encrypt= ablk_encrypt,
+.decrypt= ablk_decrypt,
+},
+},
+#ifdef CONFIG_X86_64
+}, {
+.cra_name= "__ctr-aes-aesni",
+.cra_driver_name= "__driver-ctr-aes-aesni",
+.cra_priority= 0,
+.cra_flags= CRYPTO_ALG_TYPE_BLKCIPHER,
+.cra_blocksize= 1,
+.cra_ctxsize= sizeof(struct crypto_aes_ctx) +
+  AESNI_ALIGN - 1,
+.cra_alignmask= 0,
+.cra_type= &crypto_blkcipher_type,
+.cra_module= THIS_MODULE,
+.cra_u = {
+.blkcipher = {
+.min_keysize= AES_MIN_KEY_SIZE,
+.max_keysize= AES_MAX_KEY_SIZE,
+.ivsize= AES_BLOCK_SIZE,
+.setkey= aes_set_key,
+.encrypt= ctr_crypt,
+.decrypt= ctr_crypt,
+},
+},
+}, {
+.cra_name= "ctr(aes)",
+.cra_driver_name= "ctr-aes-aesni",
+.cra_priority= 400,
+.cra_flags= CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+.cra_blocksize= 1,
+.cra_ctxsize= sizeof(struct async_aes_ctx),
+.cra_alignmask= 0,
+.cra_type= &crypto_ablkcipher_type,
+.cra_module= THIS_MODULE,
+.cra_init= ablk_ctr_init,
+.cra_exit= ablk_exit,
+.cra_u = {
+.ablkcipher = {
+.min_keysize= AES_MIN_KEY_SIZE,
+.max_keysize= AES_MAX_KEY_SIZE,
+.ivsize= AES_BLOCK_SIZE,
+.setkey= ablk_set_key,
+.encrypt= ablk_encrypt,
+.decrypt= ablk_encrypt,
+.geniv= "chainiv",
+},
+},
+}, {
+.cra_name= "__gcm-aes-aesni",
+.cra_driver_name= "__driver-gcm-aes-aesni",
 .cra_priority= 0,
 .cra_flags= CRYPTO_ALG_TYPE_AEAD,
 .cra_blocksize= 1,
-.cra_ctxsize= sizeof(struct aesni_rfc4106_gcm_ctx) + AESNI_ALIGN,
+.cra_ctxsize= sizeof(struct aesni_rfc4106_gcm_ctx) +
+  AESNI_ALIGN,
 .cra_alignmask= 0,
 .cra_type= &crypto_aead_type,
 .cra_module= THIS_MODULE,
-.cra_list= LIST_HEAD_INIT(__rfc4106_alg.cra_list),
 .cra_u = {
 .aead = {
 .encrypt= __driver_rfc4106_encrypt,
 .decrypt= __driver_rfc4106_decrypt,
 },
 },
-};
+}, {
+.cra_name= "rfc4106(gcm(aes))",
+.cra_driver_name= "rfc4106-gcm-aesni",
+.cra_priority= 400,
+.cra_flags= CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
+.cra_blocksize= 1,
+.cra_ctxsize= sizeof(struct aesni_rfc4106_gcm_ctx) +
+  AESNI_ALIGN,
+.cra_alignmask= 0,
+.cra_type= &crypto_nivaead_type,
+.cra_module= THIS_MODULE,
+.cra_init= rfc4106_init,
+.cra_exit= rfc4106_exit,
+.cra_u = {
+.aead = {
+.setkey= rfc4106_set_key,
+.setauthsize= rfc4106_set_authsize,
+.encrypt= rfc4106_encrypt,
+.decrypt= rfc4106_decrypt,
+.geniv= "seqiv",
+.ivsize= 8,
+.maxauthsize= 16,
+},
+},
+#ifdef HAS_CTR
+}, {
+.cra_name= "rfc3686(ctr(aes))",
+.cra_driver_name= "rfc3686-ctr-aes-aesni",
+.cra_priority= 400,
+.cra_flags= CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+.cra_blocksize= 1,
+.cra_ctxsize= sizeof(struct async_aes_ctx),
+.cra_alignmask= 0,
+.cra_type= &crypto_ablkcipher_type,
+.cra_module= THIS_MODULE,
+.cra_init= ablk_rfc3686_ctr_init,
+.cra_exit= ablk_exit,
+.cra_u = {
+.ablkcipher = {
+.min_keysize = AES_MIN_KEY_SIZE +
+       CTR_RFC3686_NONCE_SIZE,
+.max_keysize = AES_MAX_KEY_SIZE +
+       CTR_RFC3686_NONCE_SIZE,
+.ivsize     = CTR_RFC3686_IV_SIZE,
+.setkey     = ablk_set_key,
+.encrypt     = ablk_encrypt,
+.decrypt     = ablk_decrypt,
+.geniv     = "seqiv",
+},
+},
+#endif
+#endif
+#ifdef HAS_LRW
+}, {
+.cra_name= "lrw(aes)",
+.cra_driver_name= "lrw-aes-aesni",
+.cra_priority= 400,
+.cra_flags= CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+.cra_blocksize= AES_BLOCK_SIZE,
+.cra_ctxsize= sizeof(struct async_aes_ctx),
+.cra_alignmask= 0,
+.cra_type= &crypto_ablkcipher_type,
+.cra_module= THIS_MODULE,
+.cra_init= ablk_lrw_init,
+.cra_exit= ablk_exit,
+.cra_u = {
+.ablkcipher = {
+.min_keysize= AES_MIN_KEY_SIZE + AES_BLOCK_SIZE,
+.max_keysize= AES_MAX_KEY_SIZE + AES_BLOCK_SIZE,
+.ivsize= AES_BLOCK_SIZE,
+.setkey= ablk_set_key,
+.encrypt= ablk_encrypt,
+.decrypt= ablk_decrypt,
+},
+},
+#endif
+#ifdef HAS_PCBC
+}, {
+.cra_name= "pcbc(aes)",
+.cra_driver_name= "pcbc-aes-aesni",
+.cra_priority= 400,
+.cra_flags= CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+.cra_blocksize= AES_BLOCK_SIZE,
+.cra_ctxsize= sizeof(struct async_aes_ctx),
+.cra_alignmask= 0,
+.cra_type= &crypto_ablkcipher_type,
+.cra_module= THIS_MODULE,
+.cra_init= ablk_pcbc_init,
+.cra_exit= ablk_exit,
+.cra_u = {
+.ablkcipher = {
+.min_keysize= AES_MIN_KEY_SIZE,
+.max_keysize= AES_MAX_KEY_SIZE,
+.ivsize= AES_BLOCK_SIZE,
+.setkey= ablk_set_key,
+.encrypt= ablk_encrypt,
+.decrypt= ablk_decrypt,
+},
+},
+#endif
+#ifdef HAS_XTS
+}, {
+.cra_name= "xts(aes)",
+.cra_driver_name= "xts-aes-aesni",
+.cra_priority= 400,
+.cra_flags= CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+.cra_blocksize= AES_BLOCK_SIZE,
+.cra_ctxsize= sizeof(struct async_aes_ctx),
+.cra_alignmask= 0,
+.cra_type= &crypto_ablkcipher_type,
+.cra_module= THIS_MODULE,
+.cra_init= ablk_xts_init,
+.cra_exit= ablk_exit,
+.cra_u = {
+.ablkcipher = {
+.min_keysize= 2 * AES_MIN_KEY_SIZE,
+.max_keysize= 2 * AES_MAX_KEY_SIZE,
+.ivsize= AES_BLOCK_SIZE,
+.setkey= ablk_set_key,
+.encrypt= ablk_encrypt,
+.decrypt= ablk_decrypt,
+},
+},
 #endif
+} };
 
 
 static const struct x86_cpu_id aesni_cpu_id[] = {
< at >< at > -1263,120 +1242,24 < at >< at > MODULE_DEVICE_TABLE(x86cpu, aesni_cpu_id);
 
 static int __init aesni_init(void)
 {
-int err;
+int err, i;
 
 if (!x86_match_cpu(aesni_cpu_id))
 return -ENODEV;
 
-if ((err = crypto_fpu_init()))
-goto fpu_err;
-if ((err = crypto_register_alg(&aesni_alg)))
-goto aes_err;
-if ((err = crypto_register_alg(&__aesni_alg)))
-goto __aes_err;
-if ((err = crypto_register_alg(&blk_ecb_alg)))
-goto blk_ecb_err;
-if ((err = crypto_register_alg(&blk_cbc_alg)))
-goto blk_cbc_err;
-if ((err = crypto_register_alg(&ablk_ecb_alg)))
-goto ablk_ecb_err;
-if ((err = crypto_register_alg(&ablk_cbc_alg)))
-goto ablk_cbc_err;
-#ifdef CONFIG_X86_64
-if ((err = crypto_register_alg(&blk_ctr_alg)))
-goto blk_ctr_err;
-if ((err = crypto_register_alg(&ablk_ctr_alg)))
-goto ablk_ctr_err;
-if ((err = crypto_register_alg(&__rfc4106_alg)))
-goto __aead_gcm_err;
-if ((err = crypto_register_alg(&rfc4106_alg)))
-goto aead_gcm_err;
-#ifdef HAS_CTR
-if ((err = crypto_register_alg(&ablk_rfc3686_ctr_alg)))
-goto ablk_rfc3686_ctr_err;
-#endif
-#endif
-#ifdef HAS_LRW
-if ((err = crypto_register_alg(&ablk_lrw_alg)))
-goto ablk_lrw_err;
-#endif
-#ifdef HAS_PCBC
-if ((err = crypto_register_alg(&ablk_pcbc_alg)))
-goto ablk_pcbc_err;
-#endif
-#ifdef HAS_XTS
-if ((err = crypto_register_alg(&ablk_xts_alg)))
-goto ablk_xts_err;
-#endif
-return err;
+err = crypto_fpu_init();
+if (err)
+return err;
 
-#ifdef HAS_XTS
-ablk_xts_err:
-#endif
-#ifdef HAS_PCBC
-crypto_unregister_alg(&ablk_pcbc_alg);
-ablk_pcbc_err:
-#endif
-#ifdef HAS_LRW
-crypto_unregister_alg(&ablk_lrw_alg);
-ablk_lrw_err:
-#endif
-#ifdef CONFIG_X86_64
-#ifdef HAS_CTR
-crypto_unregister_alg(&ablk_rfc3686_ctr_alg);
-ablk_rfc3686_ctr_err:
-#endif
-crypto_unregister_alg(&rfc4106_alg);
-aead_gcm_err:
-crypto_unregister_alg(&__rfc4106_alg);
-__aead_gcm_err:
-crypto_unregister_alg(&ablk_ctr_alg);
-ablk_ctr_err:
-crypto_unregister_alg(&blk_ctr_alg);
-blk_ctr_err:
-#endif
-crypto_unregister_alg(&ablk_cbc_alg);
-ablk_cbc_err:
-crypto_unregister_alg(&ablk_ecb_alg);
-ablk_ecb_err:
-crypto_unregister_alg(&blk_cbc_alg);
-blk_cbc_err:
-crypto_unregister_alg(&blk_ecb_alg);
-blk_ecb_err:
-crypto_unregister_alg(&__aesni_alg);
-__aes_err:
-crypto_unregister_alg(&aesni_alg);
-aes_err:
-fpu_err:
-return err;
+for (i = 0; i < ARRAY_SIZE(aesni_algs); i++)
+INIT_LIST_HEAD(&aesni_algs[i].cra_list);
+
+return crypto_register_algs(aesni_algs, ARRAY_SIZE(aesni_algs));
 }
 
 static void __exit aesni_exit(void)
 {
-#ifdef HAS_XTS
-crypto_unregister_alg(&ablk_xts_alg);
-#endif
-#ifdef HAS_PCBC
-crypto_unregister_alg(&ablk_pcbc_alg);
-#endif
-#ifdef HAS_LRW
-crypto_unregister_alg(&ablk_lrw_alg);
-#endif
-#ifdef CONFIG_X86_64
-#ifdef HAS_CTR
-crypto_unregister_alg(&ablk_rfc3686_ctr_alg);
-#endif
-crypto_unregister_alg(&rfc4106_alg);
-crypto_unregister_alg(&__rfc4106_alg);
-crypto_unregister_alg(&ablk_ctr_alg);
-crypto_unregister_alg(&blk_ctr_alg);
-#endif
-crypto_unregister_alg(&ablk_cbc_alg);
-crypto_unregister_alg(&ablk_ecb_alg);
-crypto_unregister_alg(&blk_cbc_alg);
-crypto_unregister_alg(&blk_ecb_alg);
-crypto_unregister_alg(&__aesni_alg);
-crypto_unregister_alg(&aesni_alg);
+crypto_unregister_algs(aesni_algs, ARRAY_SIZE(aesni_algs));
 
 crypto_fpu_exit();
 }

async hash & hmac

Kasatkin, Dmitry — 2012-05-11T08:58:03

Hello,

When allocating hmac like: crypto_alloc_ahash("hmac(sha1)", ..),
it is actually fallsback to  "shash" hmac and software shash hash
implementation..
Even when HW accelerator provides AHASH it will not be used with hmac.

Basically HW driver needs to provide its own implementation for async
hmac, like I did for omap-sham.

.cra_name= "hmac(sha1)",
.cra_driver_name= "omap-hmac-sha1",

Is that correct, right?

Thanks.

- Dmitry

(unknown)

Mrs Sabah Halif — 2012-05-05T18:59:22

CRYPTO_ALG_ASYNC

Kasatkin, Dmitry — 2012-05-10T09:33:40

Hello Herbert,

CRYPTO_ALG_ASYNC is heavily used like:

    crypto_alloc_shash(hash_alg, 0, CRYPTO_ALG_ASYNC);
or
   .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC;
   .cra_flags = CRYPTO_ALG_TYPE_AHASH |  CRYPTO_ALG_ASYNC,

I see that only place where it is tested is in
ablockcipher.c:crypto_default_geniv()

What is actually meaning of that?

and setting it for hash??

Thanks,
Dmitry

[PATCH v2 0/3] Update for ux500 CRYP and HASH

Andreas Westin — 2012-05-10T08:14:05

Hi,

V2 of the patches.

* Removed symbol export
* Removed usage of SOC specific functions in the drivers.
* Readded overlooked config for DMA in mach-ux500.

After some internal discussion we felt that the now implemented
hardware identification solution is cleaner than the suggested
solution.

The hardware identification patch applies cleanly to
the cryptodev tree.

Regards
Andreas

Andreas Westin (3):
  mach-ux500: Crypto: core support for CRYP/HASH module.
  crypto: ux500: Update DMA handling for 3.4
  crypto: ux500: Cleanup hardware identification

 arch/arm/mach-ux500/board-mop500.c              |   48 ++++++++++++++++++++
 arch/arm/mach-ux500/clock.c                     |   18 ++++----
 arch/arm/mach-ux500/devices-common.h            |   54 +++++++++++++++++++++++
 arch/arm/mach-ux500/devices-db8500.c            |    3 ++
 arch/arm/mach-ux500/devices-db8500.h            |    4 ++
 arch/arm/mach-ux500/include/mach/crypto-ux500.h |    1 +
 arch/arm/mach-ux500/include/mach/devices.h      |    3 ++
 arch/arm/mach-ux500/include/mach/hardware.h     |    3 ++
 drivers/crypto/ux500/cryp/cryp.c                |   10 ++---
 drivers/crypto/ux500/cryp/cryp_core.c           |    5 +--
 drivers/crypto/ux500/cryp/cryp_p.h              |    1 -
 drivers/crypto/ux500/hash/hash_core.c           |   12 +----
 12 files changed, 133 insertions(+), 29 deletions(-)

General Protection Fault in aesni_cbc_dec in kernel 3.3

2012-05-08T19:08:14

Hello,

when using a VPN connection, my 3.3.4 and 3.3.5 kernel oopses in the
aesni_intel module. 


[  157.571310] general protection fault: 0000 [#1] SMP 
[  157.571411] Modules linked in: authenc esp4 xfrm4_mode_tunnel tun
deflate zlib_deflate ctr acpi_cpufreq mperf twofish_generic twofish_i586
twofish_common camellia cpufreq_conservative serpent_generic
cpufreq_stats blowfish_generic blowfish_common cpufreq_userspace cast5
cpufreq_powersave des_generic xcbc rmd160 sha512_generic sha1_generic
hmac crypto_null af_key parport_pc ppdev lp parport rfcomm bnep
binfmt_misc uinput fuse ip6t_LOG ip6t_REJECT nf_conntrack_ipv6
nf_defrag_ipv6 ip6table_filter ip6_tables ipt_LOG xt_recent ipt_REJECT
xt_tcpudp nf_conntrack_ipv4 nf_defrag_ipv4 xt_state nf_conntrack
iptable_filter ip_tables x_tables nfsd exportfs nfs nfs_acl auth_rpcgss
fscache lockd sunrpc ext2 loop btusb snd_hda_codec_hdmi arc4 bluetooth
snd_hda_codec_conexant iwlwifi i915 snd_hda_intel mac80211 joydev
drm_kms_helper snd_hda_codec snd_hwdep drm snd_pcm snd_page_alloc
thinkpad_acpi ehci_hcd i2c_i801 nvram e1000e xhci_hcd snd_seq
snd_seq_device snd_timer cfg80211 sdhci_pci sdhci mmc_core i2c_algo_bit
i2c_core iTCO_wdt iTCO_vendor_support snd usbcore battery ac soundcore
wmi evdev rfkill usb_common psmouse power_supply serio_raw pcspkr
tpm_tis tpm tpm_bios processor button video ext4 crc16 jbd2 mbcache
sha256_generic aesni_intel cryptd aes_i586 aes_generic cbc dm_crypt
dm_mod sd_mod crc_t10dif ahci libahci libata scsi_mod thermal
thermal_sys
[  157.573825] 
[  157.573855] Pid: 0, comm: swapper/0 Not tainted 3.3.4 #21 LENOVO
4287CTO/4287CTO
[  157.573985] EIP: 0060:[<f83768c0>] EFLAGS: 00010286 CPU: 0
[  157.574083] EIP is at aesni_cbc_dec+0x5c/0xbc [aesni_intel]
[  157.574172] EAX: f023409e EBX: 00000020 ECX: f403bd90 EDX: f023409e
[  157.574269] ESI: 00000040 EDI: f403bd20 EBP: f023408e ESP: f400fbec
[  157.574367]  DS: 007b ES: 007b FS: 00d8 GS: 00e0 SS: 0068
[  157.574454] Process swapper/0 (pid: 0, ti=f400e000 task=c13d0fe0
task.ti=c13ca000)
[  157.574570] Stack:
[  157.574604]  f400fc6c f400fc18 f403bc30 00000040 f8376e12 f403bc30
f023409e f023409e
[  157.574761]  00000040 f023408e 00000000 f4d14680 f023409e f4d14680
f023409e f026edfc
[  157.574917]  0000009e 00000040 f026edfc 0000009e 00000040 00000000
00000000 f023408e
[  157.575074] Call Trace:
[  157.575133]  [<f8376e12>] ? cbc_decrypt+0x5a/0x86 [aesni_intel]
[  157.575240]  [<f8376b1f>] ? ablk_decrypt+0x5d/0x66 [aesni_intel]
[  157.575337]  [<f93da1ff>] ? esp_input_done2+0x152/0x152 [esp4]
[  157.575432]  [<f94548f7>] ? crypto_authenc_decrypt+0x1c5/0x1e4
[authenc]
[  157.575539]  [<f93daba9>] ? esp_input+0x1f7/0x21a [esp4]
[  157.575632]  [<c126fa4d>] ? xfrm_input+0x1b4/0x391
[  157.575711]  [<c12549d7>] ? __udp4_lib_lookup+0x174/0x193
[  157.575802]  [<c12688f3>] ? xfrm4_udp_encap_rcv+0x12a/0x143
[  157.575892]  [<c1254beb>] ? udp_queue_rcv_skb+0x42/0x1bd
[  157.575978]  [<c12551f3>] ? __udp4_lib_rcv+0x299/0x40e
[  157.576063]  [<c1237ac8>] ? xfrm4_policy_check.constprop.11+0x45/0x45
[  157.576166]  [<c1237bc5>] ? ip_local_deliver_finish+0xfd/0x199
[  157.576260]  [<c1237ac8>] ? xfrm4_policy_check.constprop.11+0x45/0x45
[  157.576363]  [<c1237a80>] ? NF_HOOK.constprop.10+0x36/0x39
[  157.576451]  [<c1237d5a>] ? ip_local_deliver+0x39/0x3c
[  157.576534]  [<c1237ac8>] ? xfrm4_policy_check.constprop.11+0x45/0x45
[  157.576637]  [<c1237a2c>] ? ip_rcv_finish+0x2c4/0x2e2
[  157.576718]  [<c1237768>] ? inet_del_protocol+0x24/0x24
[  157.576802]  [<c1237a80>] ? NF_HOOK.constprop.10+0x36/0x39
[  157.576891]  [<c121654d>] ? __netif_receive_skb+0x331/0x36d
[  157.576980]  [<c1237768>] ? inet_del_protocol+0x24/0x24
[  157.577066]  [<c121733d>] ? netif_receive_skb+0x66/0x6b
[  157.577181]  [<f8874c90>] ? ieee80211_deliver_skb+0xa6/0xd9
[mac80211]
[  157.577307]  [<f8875e8e>] ? ieee80211_rx_handlers+0xf21/0x183c
[mac80211]
[  157.577418]  [<c1030d45>] ? _local_bh_enable_ip.isra.9+0x15/0x6d
[  157.581963]  [<c1064449>] ? arch_local_irq_save+0xf/0x14
[  157.586407]  [<c12b9a8b>] ? _raw_spin_lock_irqsave+0x8/0x21
[  157.590692]  [<f8876f0b>] ? ieee80211_prepare_and_rx_handle
+0x762/0x7ad [mac80211]
[  157.594887]  [<f88775cf>] ? ieee80211_rx+0x679/0x697 [mac80211]
[  157.598906]  [<f890e169>] ? iwlagn_rx_reply_rx+0x678/0x68d [iwlwifi]
[  157.602776]  [<c10c51ba>] ? kfree+0x9c/0xa3
[  157.606477]  [<c10c51ba>] ? kfree+0x9c/0xa3
[  157.610004]  [<f890e4b5>] ? iwl_rx_dispatch+0x12c/0x193 [iwlwifi]
[  157.613407]  [<f8919c20>] ? iwl_irq_tasklet+0x625/0x8d5 [iwlwifi]
[  157.616645]  [<c1064449>] ? arch_local_irq_save+0xf/0x14
[  157.619913]  [<c103080b>] ? tasklet_action+0x62/0xa5
[  157.623464]  [<c1030da1>] ? local_bh_enable+0x2/0x2
[  157.626658]  [<c1030e35>] ? __do_softirq+0x94/0x12f
[  157.629806]  [<c1030da1>] ? local_bh_enable+0x2/0x2
[  157.632933]  <IRQ> 
[  157.636025]  [<c1031026>] ? irq_exit+0x32/0x7d
[  157.639134]  [<c100cfd8>] ? do_IRQ+0x65/0x76
[  157.642204]  [<c12bf570>] ? common_interrupt+0x30/0x38
[  157.645226]  [<c105007b>] ? load_balance+0x487/0x504
[  157.648221]  [<f86b422c>] ? arch_local_irq_enable+0x2/0x7 [processor]
[  157.651240]  [<f86b4caa>] ? acpi_idle_enter_bm+0x23a/0x27a
[processor]
[  157.654235]  [<c1204734>] ? menu_select+0x1ae/0x356
[  157.657195]  [<c1203abd>] ? cpuidle_idle_call+0xcc/0x142
[  157.660131]  [<c100b255>] ? cpu_idle+0x8b/0xb4
[  157.663062]  [<c140a6e5>] ? start_kernel+0x316/0x31b
[  157.665956] Code: 83 fe 40 72 5a 66 90 0f 10 0a 0f 28 c1 0f 10 7a 10
0f 28 e7 0f 10 4a 20 0f 28 e9 0f 10 7a 30 0f 28 f7 e8 d8 fc ff ff 66 0f
ef c3 <66> 0f ef 22 66 0f ef 6a 10 66 0f ef f1 0f 28 df 0f 11 00 0f 11 
[  157.672635] EIP: [<f83768c0>] aesni_cbc_dec+0x5c/0xbc [aesni_intel]
SS:ESP 0068:f400fbec


Is this a known issue? Apart from this bug in Ubuntu
https://bugs.launchpad.net/ubuntu/+source/linux/+bug/980155
I found no other reference.


Best regards,
Daniel

[PATCH 0/2] Update for ux500 CRYP and HASH

Andreas Westin — 2012-05-08T11:28:31

Hi,

This is an update of the core platform support for
ux500 HASH and CRYP driver. Also a small update for DMA
in the drivers.

Note that this does not apply cleanly on the cryptodev tree since it
does not seem to be up to date for ux500.

Herbert, how should we handle this, do you want to ack this and we send
it during the merge window or another way ?

Cheers
Andreas

Andreas Westin (2):
  mach-ux500: Crypto: core support for CRYP/HASH module.
  crypto: ux500: Update DMA handling for 3.4

 arch/arm/mach-ux500/board-mop500.c              |   48 ++++++++++++++++++++
 arch/arm/mach-ux500/clock.c                     |   18 ++++----
 arch/arm/mach-ux500/devices-common.h            |   54 +++++++++++++++++++++++
 arch/arm/mach-ux500/devices-db8500.h            |    4 ++
 arch/arm/mach-ux500/id.c                        |    3 ++
 arch/arm/mach-ux500/include/mach/crypto-ux500.h |    1 +
 arch/arm/mach-ux500/include/mach/devices.h      |    3 ++
 drivers/crypto/ux500/cryp/cryp_core.c           |    5 +--
 drivers/crypto/ux500/hash/hash_core.c           |    2 +-
 9 files changed, 126 insertions(+), 12 deletions(-)

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Western Union — 2012-05-01T15:14:51