gmane.comp.gcc.patches
http://blog.gmane.org/gmane.comp.gcc.patches
hourly11901-01-01T00:00+00:00Gmanehttp://gmane.org/img/gmane-25t.png
http://gmane.org
Fix PR 53743 and other -freorder-blocks-and-partition failures
http://comments.gmane.org/gmane.comp.gcc.patches/286104
<pre>Patch 2 of 3 split out from the patch I sent last week that fixes problems with
-freorder-blocks-and-partition, with changes/fixes discussed in that thread,
along with some additional verification improvements.
See http://gcc.gnu.org/ml/gcc-patches/2013-05/threads.html#00388 for context.
This portion of the original patch fixes failures encountered when enabling
-freorder-blocks-and-partition, including the failure reported in PR 53743.
I attempted to make the handling of partition updates through the optimization
passes much more consistent, removing a number of partial fixes in the code
stream in the process. The code to fixup partitions (including the BB_PARTITION
assignment, region crossing jump notes, and switch text section notes) is
now handled in a few centralized locations. For example, inside
rtl_redirect_edge_and_branch and force_nonfallthru_and_redirect, so that callers
don't need to attempt the fixup themselves.
The main changes from the earlier patch are: (1) The switch text section
notes are not inserted until the free_cfg pass, avoiding the need to
maintain these properly when going in and out of cfglayout mode;
(2) Unnecessary forward blocks between partitions are avoided by
suppressing unnecessary calls to force_nonfallthru during bbpart, avoiding
the need for additional cleanup later; and (3) fixing a few places
where region crossing jump notes were not being maintained properly,
exposed by additional verification checks I added.
Tested on x86_64-unknown-linux-gnu with bootstrap and profiledbootstrap
builds and regression testing. Additionally built/ran cpu2006int with profile
feedback and -freorder-blocks-and-partition enabled - all benchmarks now
pass (previously only 6 passed). This also passes a profiledbootstrap with
-freorder-blocks-and-partition enabled by default (although this required
forcing the dwarf version down to 2 to workaround issues with debug range
generation and partitioning that still need to be addressed for -g
compilations).
Ok for trunk?
Thanks,
Teresa
2013-05-19 Teresa Johnson <tejohnson< at >google.com>
* ifcvt.c (find_if_case_1): Replace BB_COPY_PARTITION with assert
as this is now done by redirect_edge_and_branch_force.
* function.c (thread_prologue_and_epilogue_insns): Insert new bb after
barriers, and fix interaction with splitting.
* emit-rtl.c (try_split): Copy REG_CROSSING_JUMP notes.
* cfgcleanup.c (try_forward_edges): Fix early return value to properly
reflect changes made in the routine.
* bb-reorder.c (emit_barrier_after_bb): Handle insertion in
non-cfglayout mode.
(fix_up_fall_thru_edges): Remove incorrect check for bb layout order
since this is called in cfglayout mode, and replace partition fixup
with assert as that is now done by force_nonfallthru_and_redirect.
(add_reg_crossing_jump_notes): Handle the fact that some jumps may
already be marked with region crossing note.
(insert_section_boundary_note): Make non-static, gate on flag
has_bb_partition, rewrite to also check for multiple partitions.
(rest_of_handle_reorder_blocks): Remove call to
insert_section_boundary_note, now done later during free_cfg.
* bb-reorder.h: Declare insert_section_boundary_note and
emit_barrier_after_bb, which are no longer static.
* Makefile.in (cfgrtl.o): Depend on bb-reorder.h
* cfgrtl.c (rest_of_pass_free_cfg): If partitions exist
invoke insert_section_boundary_note.
(try_redirect_by_replacing_jump): Remove unnecessary
check for region crossing note.
(fixup_partition_crossing): New function.
(rtl_redirect_edge_and_branch): Fixup partition boundaries.
(force_nonfallthru_and_redirect): Fixup partition boundaries,
remove old code that tried to do this. Emit barrier correctly
when we are in cfglayout mode.
(rtl_split_edge): Correctly fixup partition boundaries.
(commit_one_edge_insertion): Remove old code that tried to
fixup region crossing edge since this is now handled in
split_block, and set up insertion point correctly since
block may now end in a jump.
(rtl_verify_edges): Add checks for incorrect/missing REG_CROSSING_JUMP
notes.
(fixup_reorder_chain): Remove old code that attempted to fixup region
crossing note as this is now handled in force_nonfallthru_and_redirect.
(duplicate_insn_chain): Don't duplicate switch section notes.
(rtl_can_remove_branch_p): Remove unnecessary check for region crossing
note.
Index: ifcvt.c
===================================================================
--- ifcvt.c(revision 199014)
+++ ifcvt.c(working copy)
< at >< at > -3905,10 +3905,9 < at >< at > find_if_case_1 (basic_block test_bb, edge then_edg
if (new_bb)
{
df_bb_replace (then_bb_index, new_bb);
- /* Since the fallthru edge was redirected from test_bb to new_bb,
- we need to ensure that new_bb is in the same partition as
- test bb (you can not fall through across section boundaries). */
- BB_COPY_PARTITION (new_bb, test_bb);
+ /* This should have been done above via force_nonfallthru_and_redirect
+ (possibly called from redirect_edge_and_branch_force). */
+ gcc_assert (BB_PARTITION (new_bb) == BB_PARTITION (test_bb));
}
num_true_changes++;
Index: function.c
===================================================================
--- function.c(revision 199014)
+++ function.c(working copy)
< at >< at > -6270,8 +6270,10 < at >< at > thread_prologue_and_epilogue_insns (void)
break;
if (e)
{
- copy_bb = create_basic_block (NEXT_INSN (BB_END (e->src)),
- NULL_RTX, e->src);
+ /* Make sure we insert after any barriers. */
+ rtx end = get_last_bb_insn (e->src);
+ copy_bb = create_basic_block (NEXT_INSN (end),
+ NULL_RTX, e->src);
BB_COPY_PARTITION (copy_bb, e->src);
}
else
< at >< at > -6538,7 +6540,7 < at >< at > epilogue_done:
basic_block simple_return_block_cold = NULL;
edge pending_edge_hot = NULL;
edge pending_edge_cold = NULL;
- basic_block exit_pred = EXIT_BLOCK_PTR->prev_bb;
+ basic_block exit_pred;
int i;
gcc_assert (entry_edge != orig_entry_edge);
< at >< at > -6566,6 +6568,12 < at >< at > epilogue_done:
else
pending_edge_cold = e;
}
+
+ /* Save a pointer to the exit's predecessor BB for use in
+ inserting new BBs at the end of the function. Do this
+ after the call to split_block above which may split
+ the original exit pred. */
+ exit_pred = EXIT_BLOCK_PTR->prev_bb;
FOR_EACH_VEC_ELT (unconverted_simple_returns, i, e)
{
Index: emit-rtl.c
===================================================================
--- emit-rtl.c(revision 199014)
+++ emit-rtl.c(working copy)
< at >< at > -3574,6 +3574,7 < at >< at > try_split (rtx pat, rtx trial, int last)
break;
case REG_NON_LOCAL_GOTO:
+case REG_CROSSING_JUMP:
for (insn = insn_last; insn != NULL_RTX; insn = PREV_INSN (insn))
{
if (JUMP_P (insn))
Index: cfgcleanup.c
===================================================================
--- cfgcleanup.c(revision 199014)
+++ cfgcleanup.c(working copy)
< at >< at > -456,7 +456,7 < at >< at > try_forward_edges (int mode, basic_block b)
if (first != EXIT_BLOCK_PTR
&& find_reg_note (BB_END (first), REG_CROSSING_JUMP, NULL_RTX))
-return false;
+return changed;
while (counter < n_basic_blocks)
{
Index: bb-reorder.c
===================================================================
--- bb-reorder.c(revision 199014)
+++ bb-reorder.c(working copy)
< at >< at > -1380,13 +1380,16 < at >< at > get_uncond_jump_length (void)
return length;
}
-/* Emit a barrier into the footer of BB. */
+/* Emit a barrier after BB, into the footer if we are in CFGLAYOUT mode. */
-static void
+void
emit_barrier_after_bb (basic_block bb)
{
rtx barrier = emit_barrier_after (BB_END (bb));
- BB_FOOTER (bb) = unlink_insn_chain (barrier, barrier);
+ gcc_assert (current_ir_type() == IR_RTL_CFGRTL
+ || current_ir_type () == IR_RTL_CFGLAYOUT);
+ if (current_ir_type () == IR_RTL_CFGLAYOUT)
+ BB_FOOTER (bb) = unlink_insn_chain (barrier, barrier);
}
/* The landing pad OLD_LP, in block OLD_BB, has edges from both partitions.
< at >< at > -1720,8 +1723,7 < at >< at > fix_up_fall_thru_edges (void)
(i.e. fix it so the fall through does not cross and
the cond jump does). */
- if (!cond_jump_crosses
- && cur_bb->aux == cond_jump->dest)
+ if (!cond_jump_crosses)
{
/* Find label in fall_thru block. We've already added
any missing labels, so there must be one. */
< at >< at > -1765,10 +1767,10 < at >< at > fix_up_fall_thru_edges (void)
new_bb->aux = cur_bb->aux;
cur_bb->aux = new_bb;
- /* Make sure new fall-through bb is in same
- partition as bb it's falling through from. */
+ /* This is done by force_nonfallthru_and_redirect. */
+ gcc_assert (BB_PARTITION (new_bb)
+ == BB_PARTITION (cur_bb));
- BB_COPY_PARTITION (new_bb, cur_bb);
single_succ_edge (new_bb)->flags |= EDGE_CROSSING;
}
else
< at >< at > -2064,7 +2066,10 < at >< at > add_reg_crossing_jump_notes (void)
FOR_EACH_BB (bb)
FOR_EACH_EDGE (e, ei, bb->succs)
if ((e->flags & EDGE_CROSSING)
- && JUMP_P (BB_END (e->src)))
+ && JUMP_P (BB_END (e->src))
+ /* Some notes were added during fix_up_fall_thru_edges, via
+ force_nonfallthru_and_redirect. */
+ && !find_reg_note (BB_END (e->src), REG_CROSSING_JUMP, NULL_RTX))
add_reg_note (BB_END (e->src), REG_CROSSING_JUMP, NULL_RTX);
}
< at >< at > -2133,25 +2138,39 < at >< at > reorder_basic_blocks (void)
encountering this note will make the compiler switch between the
hot and cold text sections. */
-static void
+void
insert_section_boundary_note (void)
{
basic_block bb;
- int first_partition = 0;
+ int err = 0;
+ bool switched_sections = false;
+ int current_partition = 0;
- if (!flag_reorder_blocks_and_partition)
+ if (!crtl->has_bb_partition)
return;
FOR_EACH_BB (bb)
{
- if (!first_partition)
-first_partition = BB_PARTITION (bb);
- if (BB_PARTITION (bb) != first_partition)
+ if (!current_partition)
+current_partition = BB_PARTITION (bb);
+ if (BB_PARTITION (bb) != current_partition)
{
- emit_note_before (NOTE_INSN_SWITCH_TEXT_SECTIONS, BB_HEAD (bb));
- break;
+ if (switched_sections)
+ {
+ error ("multiple hot/cold transitions found (bb %i)",
+ bb->index);
+ err = 1;
+ }
+ else
+ {
+ switched_sections = true;
+ emit_note_before (NOTE_INSN_SWITCH_TEXT_SECTIONS, BB_HEAD (bb));
+ current_partition = BB_PARTITION (bb);
+ }
}
}
+
+ gcc_assert(!err);
}
static bool
< at >< at > -2180,8 +2199,6 < at >< at > rest_of_handle_reorder_blocks (void)
bb->aux = bb->next_bb;
cfg_layout_finalize ();
- /* Add NOTE_INSN_SWITCH_TEXT_SECTIONS notes. */
- insert_section_boundary_note ();
return 0;
}
Index: bb-reorder.h
===================================================================
--- bb-reorder.h(revision 199014)
+++ bb-reorder.h(working copy)
< at >< at > -35,4 +35,8 < at >< at > extern struct target_bb_reorder *this_target_bb_re
extern int get_uncond_jump_length (void);
+extern void insert_section_boundary_note (void);
+
+extern void emit_barrier_after_bb (basic_block bb);
+
#endif
Index: Makefile.in
===================================================================
--- Makefile.in(revision 199014)
+++ Makefile.in(working copy)
< at >< at > -3151,7 +3151,7 < at >< at > cfgrtl.o : cfgrtl.c $(CONFIG_H) $(SYSTEM_H) corety
$(FUNCTION_H) $(EXCEPT_H) $(TM_P_H) $(INSN_ATTR_H) \
insn-config.h $(EXPR_H) \
$(CFGLOOP_H) $(OBSTACK_H) $(TARGET_H) $(TREE_H) \
- $(TREE_PASS_H) $(DF_H) $(GGC_H) $(COMMON_TARGET_H) gt-cfgrtl.h
+ $(TREE_PASS_H) $(DF_H) $(GGC_H) $(COMMON_TARGET_H) gt-cfgrtl.h bb-reorder.h
cfganal.o : cfganal.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(BASIC_BLOCK_H) \
$(TIMEVAR_H) sbitmap.h $(BITMAP_H)
cfgbuild.o : cfgbuild.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) $(RTL_H) \
Index: cfgrtl.c
===================================================================
--- cfgrtl.c(revision 199014)
+++ cfgrtl.c(working copy)
< at >< at > -44,6 +44,7 < at >< at > along with GCC; see the file COPYING3. If not see
#include "tree.h"
#include "hard-reg-set.h"
#include "basic-block.h"
+#include "bb-reorder.h"
#include "regs.h"
#include "flags.h"
#include "function.h"
< at >< at > -451,6 +452,9 < at >< at > rest_of_pass_free_cfg (void)
}
#endif
+ if (crtl->has_bb_partition)
+ insert_section_boundary_note ();
+
free_bb_for_insn ();
return 0;
}
< at >< at > -981,8 +985,7 < at >< at > try_redirect_by_replacing_jump (edge e, basic_bloc
partition boundaries). See the comments at the top of
bb-reorder.c:partition_hot_cold_basic_blocks for complete details. */
- if (find_reg_note (insn, REG_CROSSING_JUMP, NULL_RTX)
- || BB_PARTITION (src) != BB_PARTITION (target))
+ if (BB_PARTITION (src) != BB_PARTITION (target))
return NULL;
/* We can replace or remove a complex jump only when we have exactly
< at >< at > -1291,6 +1294,53 < at >< at > redirect_branch_edge (edge e, basic_block target)
return e;
}
+/* Called when edge E has been redirected to a new destination,
+ in order to update the region crossing flag on the edge and
+ jump. */
+
+static void
+fixup_partition_crossing (edge e)
+{
+ rtx note;
+
+ if (e->src == ENTRY_BLOCK_PTR || e->dest == EXIT_BLOCK_PTR)
+ return;
+ /* If we redirected an existing edge, it may already be marked
+ crossing, even though the new src is missing a reg crossing note.
+ But make sure reg crossing note doesn't already exist before
+ inserting. */
+ if (BB_PARTITION (e->src) != BB_PARTITION (e->dest))
+ {
+ e->flags |= EDGE_CROSSING;
+ note = find_reg_note (BB_END (e->src), REG_CROSSING_JUMP, NULL_RTX);
+ if (JUMP_P (BB_END (e->src))
+ && !note)
+ add_reg_note (BB_END (e->src), REG_CROSSING_JUMP, NULL_RTX);
+ }
+ else if (BB_PARTITION (e->src) == BB_PARTITION (e->dest))
+ {
+ e->flags &= ~EDGE_CROSSING;
+ /* Remove the region crossing note from jump at end of
+ src if it exists, and if no other successors are
+ still crossing. */
+ note = find_reg_note (BB_END (e->src), REG_CROSSING_JUMP, NULL_RTX);
+ if (note)
+ {
+ bool has_crossing_succ = false;
+ edge e2;
+ edge_iterator ei;
+ FOR_EACH_EDGE (e2, ei, e->src->succs)
+ {
+ has_crossing_succ |= (e2->flags & EDGE_CROSSING);
+ if (has_crossing_succ)
+ break;
+ }
+ if (!has_crossing_succ)
+ remove_note (BB_END (e->src), note);
+ }
+ }
+}
+
/* Attempt to change code to redirect edge E to TARGET. Don't do that on
expense of adding new instructions or reordering basic blocks.
< at >< at > -1307,16 +1357,18 < at >< at > rtl_redirect_edge_and_branch (edge e, basic_block
{
edge ret;
basic_block src = e->src;
+ basic_block dest = e->dest;
if (e->flags & (EDGE_ABNORMAL_CALL | EDGE_EH))
return NULL;
- if (e->dest == target)
+ if (dest == target)
return e;
if ((ret = try_redirect_by_replacing_jump (e, target, false)) != NULL)
{
df_set_bb_dirty (src);
+ fixup_partition_crossing (ret);
return ret;
}
< at >< at > -1325,6 +1377,7 < at >< at > rtl_redirect_edge_and_branch (edge e, basic_block
return NULL;
df_set_bb_dirty (src);
+ fixup_partition_crossing (ret);
return ret;
}
< at >< at > -1492,12 +1545,6 < at >< at > force_nonfallthru_and_redirect (edge e, basic_bloc
/* Make sure new block ends up in correct hot/cold section. */
BB_COPY_PARTITION (jump_block, e->src);
- if (flag_reorder_blocks_and_partition
- && targetm_common.have_named_sections
- && JUMP_P (BB_END (jump_block))
- && !any_condjump_p (BB_END (jump_block))
- && (EDGE_SUCC (jump_block, 0)->flags & EDGE_CROSSING))
-add_reg_note (BB_END (jump_block), REG_CROSSING_JUMP, NULL_RTX);
/* Wire edge in. */
new_edge = make_edge (e->src, jump_block, EDGE_FALLTHRU);
< at >< at > -1508,6 +1555,10 < at >< at > force_nonfallthru_and_redirect (edge e, basic_bloc
redirect_edge_pred (e, jump_block);
e->probability = REG_BR_PROB_BASE;
+ /* If e->src was previously region crossing, it no longer is
+ and the reg crossing note should be removed. */
+ fixup_partition_crossing (new_edge);
+
/* If asm goto has any label refs to target's label,
add also edge from asm goto bb to target. */
if (asm_goto_edge)
< at >< at > -1559,13 +1610,16 < at >< at > force_nonfallthru_and_redirect (edge e, basic_bloc
LABEL_NUSES (label)++;
}
- emit_barrier_after (BB_END (jump_block));
+ /* We might be in cfg layout mode, and if so, the following routine will
+ insert the barrier correctly. */
+ emit_barrier_after_bb (jump_block);
redirect_edge_succ_nodup (e, target);
if (abnormal_edge_flags)
make_edge (src, target, abnormal_edge_flags);
df_mark_solutions_dirty ();
+ fixup_partition_crossing (e);
return new_bb;
}
< at >< at > -1664,7 +1718,7 < at >< at > rtl_move_block_after (basic_block bb ATTRIBUTE_UNU
static basic_block
rtl_split_edge (edge edge_in)
{
- basic_block bb;
+ basic_block bb, new_bb;
rtx before;
/* Abnormal edges cannot be split. */
< at >< at > -1697,12 +1751,26 < at >< at > rtl_split_edge (edge edge_in)
else
{
bb = create_basic_block (before, NULL, edge_in->dest->prev_bb);
- /* ??? Why not edge_in->dest->prev_bb here? */
- BB_COPY_PARTITION (bb, edge_in->dest);
+ if (edge_in->src == ENTRY_BLOCK_PTR)
+ BB_COPY_PARTITION (bb, edge_in->dest);
+ else
+ /* Put the split bb into the src partition, to avoid creating
+ a situation where a cold bb dominates a hot bb, in the case
+ where src is cold and dest is hot. The src will dominate
+ the new bb (whereas it might not have dominated dest). */
+ BB_COPY_PARTITION (bb, edge_in->src);
}
make_single_succ_edge (bb, edge_in->dest, EDGE_FALLTHRU);
+ /* Can't allow a region crossing edge to be fallthrough. */
+ if (BB_PARTITION (bb) != BB_PARTITION (edge_in->dest)
+ && edge_in->dest != EXIT_BLOCK_PTR)
+ {
+ new_bb = force_nonfallthru (single_succ_edge (bb));
+ gcc_assert (!new_bb);
+ }
+
/* For non-fallthru edges, we must adjust the predecessor's
jump instruction to target our new block. */
if ((edge_in->flags & EDGE_FALLTHRU) == 0)
< at >< at > -1815,17 +1883,13 < at >< at > commit_one_edge_insertion (edge e)
else
{
bb = split_edge (e);
- after = BB_END (bb);
- if (flag_reorder_blocks_and_partition
- && targetm_common.have_named_sections
- && e->src != ENTRY_BLOCK_PTR
- && BB_PARTITION (e->src) == BB_COLD_PARTITION
- && !(e->flags & EDGE_CROSSING)
- && JUMP_P (after)
- && !any_condjump_p (after)
- && (single_succ_edge (bb)->flags & EDGE_CROSSING))
-add_reg_note (after, REG_CROSSING_JUMP, NULL_RTX);
+ /* If E crossed a partition boundary, we needed to make bb end in
+ a region-crossing jump, even though it was originally fallthru. */
+ if (JUMP_P (BB_END (bb)))
+before = BB_END (bb);
+ else
+ after = BB_END (bb);
}
/* Now that we've found the spot, do the insertion. */
< at >< at > -2116,6 +2180,7 < at >< at > rtl_verify_edges (void)
edge e, fallthru = NULL;
edge_iterator ei;
rtx note;
+ bool has_crossing_edge = false;
if (JUMP_P (BB_END (bb))
&& (note = find_reg_note (BB_END (bb), REG_BR_PROB, NULL_RTX))
< at >< at > -2141,6 +2206,7 < at >< at > rtl_verify_edges (void)
is_crossing = (BB_PARTITION (e->src) != BB_PARTITION (e->dest)
&& e->src != ENTRY_BLOCK_PTR
&& e->dest != EXIT_BLOCK_PTR);
+ has_crossing_edge |= is_crossing;
if (e->flags & EDGE_CROSSING)
{
if (!is_crossing)
< at >< at > -2160,6 +2226,13 < at >< at > rtl_verify_edges (void)
e->src->index);
err = 1;
}
+ if (JUMP_P (BB_END (bb))
+ && !find_reg_note (BB_END (bb), REG_CROSSING_JUMP, NULL_RTX))
+{
+ error ("No region crossing jump at section boundary in bb %i",
+ bb->index);
+ err = 1;
+}
}
else if (is_crossing)
{
< at >< at > -2188,6 +2261,15 < at >< at > rtl_verify_edges (void)
n_abnormal++;
}
+ if (!has_crossing_edge
+ && find_reg_note (BB_END (bb), REG_CROSSING_JUMP, NULL_RTX))
+ {
+ print_rtl_with_bb (stderr, get_insns (), TDF_RTL | TDF_BLOCKS | TDF_DETAILS);
+ error ("Region crossing jump across same section in bb %i",
+ bb->index);
+ err = 1;
+ }
+
if (n_eh && !find_reg_note (BB_END (bb), REG_EH_REGION, NULL_RTX))
{
error ("missing REG_EH_REGION note at the end of bb %i", bb->index);
< at >< at > -3343,7 +3425,7 < at >< at > fixup_reorder_chain (void)
edge e_fall, e_taken, e;
rtx bb_end_insn;
rtx ret_label = NULL_RTX;
- basic_block nb, src_bb;
+ basic_block nb;
edge_iterator ei;
if (EDGE_COUNT (bb->succs) == 0)
< at >< at > -3478,7 +3560,6 < at >< at > fixup_reorder_chain (void)
/* We got here if we need to add a new jump insn.
Note force_nonfallthru can delete E_FALL and thus we have to
save E_FALL->src prior to the call to force_nonfallthru. */
- src_bb = e_fall->src;
nb = force_nonfallthru_and_redirect (e_fall, e_fall->dest, ret_label);
if (nb)
{
< at >< at > -3486,17 +3567,6 < at >< at > fixup_reorder_chain (void)
bb->aux = nb;
/* Don't process this new block. */
bb = nb;
-
- /* Make sure new bb is tagged for correct section (same as
- fall-thru source, since you cannot fall-thru across
- section boundaries). */
- BB_COPY_PARTITION (src_bb, single_pred (bb));
- if (flag_reorder_blocks_and_partition
- && targetm_common.have_named_sections
- && JUMP_P (BB_END (bb))
- && !any_condjump_p (BB_END (bb))
- && (EDGE_SUCC (bb, 0)->flags & EDGE_CROSSING))
- add_reg_note (BB_END (bb), REG_CROSSING_JUMP, NULL_RTX);
}
}
< at >< at > -3796,10 +3866,11 < at >< at > duplicate_insn_chain (rtx from, rtx to)
case NOTE_INSN_FUNCTION_BEG:
/* There is always just single entry to function. */
case NOTE_INSN_BASIC_BLOCK:
+ /* We should only switch text sections once. */
+ case NOTE_INSN_SWITCH_TEXT_SECTIONS:
break;
case NOTE_INSN_EPILOGUE_BEG:
- case NOTE_INSN_SWITCH_TEXT_SECTIONS:
emit_note_copy (insn);
break;
< at >< at > -4611,8 +4682,7 < at >< at > rtl_can_remove_branch_p (const_edge e)
if (e->flags & (EDGE_ABNORMAL_CALL | EDGE_EH))
return false;
- if (find_reg_note (insn, REG_CROSSING_JUMP, NULL_RTX)
- || BB_PARTITION (src) != BB_PARTITION (target))
+ if (BB_PARTITION (src) != BB_PARTITION (target))
return false;
if (!onlyjump_p (insn)
</pre>Teresa Johnson2013-05-20T02:55:01Fix PR tree-optimization/57322
http://comments.gmane.org/gmane.comp.gcc.patches/286100
<pre>The UID of a newly generated statement in build_and_add_sum is set to
that of an adjacent statement in the BB. This is a problem in one case
where the BB is empty. This fix sets the UID to be 1 if the BB is
empty. Bootstraps and no test regressions on x86_64 . OK for trunk?
Thanks,
Easwaran
-----------
2013-05-19 Easwaran Raman <eraman< at >google.com>
PR tree-optimization/57322
* (build_and_add_sum): If a BB is empty, set the UID of the statement
added to the BB to be 1.
Index: gcc/tree-ssa-reassoc.c
===================================================================
--- gcc/tree-ssa-reassoc.c (revision 199048)
+++ gcc/tree-ssa-reassoc.c (working copy)
< at >< at > -1165,8 +1165,12 < at >< at > build_and_add_sum (tree type, tree op1, tree op2,
if ((!op1def || gimple_nop_p (op1def))
&& (!op2def || gimple_nop_p (op2def)))
{
+ gimple first_stmt;
+ unsigned uid;
gsi = gsi_after_labels (single_succ (ENTRY_BLOCK_PTR));
- gimple_set_uid (sum, gimple_uid (gsi_stmt (gsi)));
+ first_stmt = gsi_stmt (gsi);
+ uid = first_stmt ? gimple_uid (first_stmt) : 1;
+ gimple_set_uid (sum, uid);
gsi_insert_before (&gsi, sum, GSI_NEW_STMT);
}
else if ((!op1def || gimple_nop_p (op1def))
</pre>Easwaran Raman2013-05-19T23:41:40[patch] Preserve the CFG until after final
http://comments.gmane.org/gmane.comp.gcc.patches/286099
<pre>Hello,
This patch allows targets to keep the CFG around until after final, by
skipping pass_free_cfg and CFG-destructive passes like dbr_schedule,
and by making insn splitting before 'final' use split_all_insns
instead of split_all_insns_noflow if pass_free_cfg was skipped.
Most machine reorg passes also are not able to maintain the CFG, so
I've split the machine_reorg hook into separate CFG-aware and
CFG-unaware versions, renaming the existing hook (to signal that
maintaining the CFG is desirable in new ports ;-).
For the moment, only ix86 uses the CFG-aware version of the hook, but
there are a handful of targets that can be converted to do this also
(ia64, bfin, c6x, sparc, probably others). Other ports can change to
the CFG-aware machine reorg pass and keep part of the current, non
CFG-aware reorg pass for the second hook (mips). Some ports have
CFG-aware machine-reorg passes but verify_flow_info fails after the
machine-reorg pass because the port emits insns between basic blocks,
e.g. for const pools. What's missing is a way for verify_flow_info to
be tolerant of such non-insns but I'm not sure yet what the best
approach for this will be (possibilities I've considered so far are:
allow bare UNSPECV insns between basic blocks after machine-reorg; put
a flag on such non-insns; maintain a bitmap of uids for non-insns;
...).
I hope that maintainers will over time change their machine reorgs to
maintain the CFG, so that passes like pass_dwarf2_frame can use the
CFG instead of creating "a facsimile of one on the fly" (see
dwarf2cfi.c).
Bootstrapped&tested on x86_64-unknown-linux-gnu (unix{,-m32}).
OK for trunk?
Ciao!
Steven
* target.def (machine_dependent_reorg): Add documentation.
(machine_dependent_reorg_nocfg): New hook.
* doc/tm.texi.in (TARGET_MACHINE_DEPENDENT_REORG): Remove old
documentation.
(TARGET_MACHINE_DEPENDENT_REORG_NOCFG): New hook insert point.
* doc/tm.texi: Regenerate
* function.h (struct rtl_data): Add 'cfg_released' member.
* cfgrtl.c (rest_of_pass_free_cfg): Set it at the end.
* tree-pass.h (pass_cfg_unaware_passes, pass_machine_reorg_nocfg):
New passes.
* passes.c (init_optimization_passes): Schedule the new passes.
Use pass_machine_reorg_nocfg to group passes that do not maintain
the control flow graph.
* reorg.c (gate_handle_machine_reorg_nocfg): New function.
(rest_of_handle_machine_reorg_nocfg): New Function.
(gate_cfg_unaware_passes): New function.
(gate_handle_machine_reorg): New function.
(rest_of_handle_machine_reorg): New function.
(pass_machine_reorg_nocfg): New pass.
(pass_cfg_unaware_passes): New pass.
* recog.c (rest_of_handle_final_split): New function.
(pass_split_for_short): Call rest_of_handle_final_split instead
of directly calling split_all_insns_noflow.
* sched-ebb.c (schedule_ebbs_init): Do not call compute_bb_for_insn.
* config/i386/i386.c (ix86_reorg): Do not call compute_bb_for_insn.
* config/alpha/alpha.c: Replace TARGET_MACHINE_DEPENDENT_REORG
with TARGET_MACHINE_DEPENDENT_REORG_NOCFG.
* config/frv/frv.c: Likewise.
* config/s390/s390.c: Likewise.
* config/spu/spu.c: Likewise.
* config/mep/mep.c;
* config/tilegx/tilegx.c: Likewise.
* config/sh/sh.c: Likewise.
* config/avr/avr.c: Likewise.
* config/stormy16/stormy16.c: Likewise.
* config/mn10300/mn10300.c: Likewise.
* config/c6x/c6x.c: Likewise.
* config/ia64/ia64.c: Likewise.
* config/picochip/picochip.c: Likewise.
* config/mcore/mcore.c: Likewise.
* config/tilepro/tilepro.c: Likewise.
* config/arm/arm.c: Likewise.
* config/pa/pa.c: Likewise.
* config/mips/mips.c: Likewise.
* config/v850/v850.c: Likewise.
* config/h8300/h8300.c: Likewise.
* config/mmix/mmix.c: Likewise.
* config/bfin/bfin.c: Likewise.
Index: target.def
===================================================================
--- target.def(revision 199028)
+++ target.def(working copy)
< at >< at > -1888,11 +1888,37 < at >< at > DEFHOOK
enum machine_mode, (enum machine_mode m1, enum machine_mode m2),
default_cc_modes_compatible)
-/* Do machine-dependent code transformations. Called just before
- delayed-branch scheduling. */
+/* Do machine-dependent code transformations. */
DEFHOOK
(machine_dependent_reorg,
- "",
+ "If non-null, this hook can be used to perform target-specific passes \
+over the instruction stream near the very end of the compilation of \
+a function. The hook is called via < at >code{pass_machine_reorg} just \
+before the delayed-branch scheduling pass. This hook is optional, \
+< at >code{pass_machine_reorg} pass only runs if the hook non-null.\n\
+This target hook should maintain the CFG (< at >code{verify_flow_inf} \
+should not fail after this pass). Legacy machine dependent reorg \
+passes that destroy the CFG should not define this hook, but instead \
+use tne < at >code{machine_dependent_reorg_nocfg} hook. \
+\n\
+The hook an be used for various target-specific purposes, such as \
+machine-specific code transformations to work around errata or other \
+hazards, laying out constant pools. The hook can also be used for \
+the implementation of machine-dependent optimizations, although this \
+practice is discouraged if the optimization may be useful for other \
+target machines as well. Such optimizations should be implemented \
+in the compiler midde end.",
+ void, (void), NULL)
+
+/* Like machine_dependent_reorg but for legacy machine reorg passes that
+ are not aware of the CFG. */
+DEFHOOK
+(machine_dependent_reorg_nocfg,
+ "Like < at >code{machine_dependent_reorg}, but for use by legacy targets. \
+This hook assumes that the machine dependent pass is not aware of \
+the control flow graph and is unable to maintain it properly. Before \
+the hook is called, the control flow graph is released. Basic blocks \
+still exist but < at >code{BLOCK_FOR_INSN} will be nullified.",
void, (void), NULL)
/* Create the __builtin_va_list type. */
Index: doc/tm.texi.in
===================================================================
--- doc/tm.texi.in(revision 199028)
+++ doc/tm.texi.in(working copy)
< at >< at > -10707,18 +10707,8 < at >< at > to by < at >var{ce_info}.
< at >end defmac
< at >hook TARGET_MACHINE_DEPENDENT_REORG
-If non-null, this hook performs a target-specific pass over the
-instruction stream. The compiler will run it at all optimization levels,
-just before the point at which it normally does delayed-branch scheduling.
-The exact purpose of the hook varies from target to target. Some use
-it to do transformations that are necessary for correctness, such as
-laying out in-function constant pools or avoiding hardware hazards.
-Others use it as an opportunity to do some machine-dependent optimizations.
-
-You need not implement the hook if it has nothing to do. The default
-definition is null.
-< at >end deftypefn
+< at >hook TARGET_MACHINE_DEPENDENT_REORG_NOCFG
< at >hook TARGET_INIT_BUILTINS
Define this hook if you have any machine-specific built-in functions
Index: doc/tm.texi
===================================================================
--- doc/tm.texi(revision 199028)
+++ doc/tm.texi(working copy)
< at >< at > -10863,17 +10863,13 < at >< at > to by < at >var{ce_info}.
< at >end defmac
< at >deftypefn {Target Hook} void TARGET_MACHINE_DEPENDENT_REORG (void)
-If non-null, this hook performs a target-specific pass over the
-instruction stream. The compiler will run it at all optimization levels,
-just before the point at which it normally does delayed-branch scheduling.
-
-The exact purpose of the hook varies from target to target. Some use
-it to do transformations that are necessary for correctness, such as
-laying out in-function constant pools or avoiding hardware hazards.
-Others use it as an opportunity to do some machine-dependent optimizations.
+If non-null, this hook can be used to perform target-specific passes over the instruction stream near the very end of the compilation of a function. The hook is called via < at >code{pass_machine_reorg} just before the delayed-branch scheduling pass. This hook is optional, < at >code{pass_machine_reorg} pass only runs if the hook non-null.
+This target hook should maintain the CFG (< at >code{verify_flow_inf} should not fail after this pass). Legacy machine dependent reorg passes that destroy the CFG should not define this hook, but instead use tne < at >code{machine_dependent_reorg_nocfg} hook.
+The hook an be used for various target-specific purposes, such as machine-specific code transformations to work around errata or other hazards, laying out constant pools. The hook can also be used for the implementation of machine-dependent optimizations, although this practice is discouraged if the optimization may be useful for other target machines as well. Such optimizations should be implemented in the compiler midde end.
+< at >end deftypefn
-You need not implement the hook if it has nothing to do. The default
-definition is null.
+< at >deftypefn {Target Hook} void TARGET_MACHINE_DEPENDENT_REORG_NOCFG (void)
+Like < at >code{machine_dependent_reorg}, but for use by legacy targets. This hook assumes that the machine dependent pass is not aware of the control flow graph and is unable to maintain it properly. Before the hook is called, the control flow graph is released. Basic blocks still exist but < at >code{BLOCK_FOR_INSN} will be nullified.
< at >end deftypefn
< at >deftypefn {Target Hook} void TARGET_INIT_BUILTINS (void)
Index: function.h
===================================================================
--- function.h(revision 199028)
+++ function.h(working copy)
< at >< at > -455,6 +455,9 < at >< at > struct GTY(()) rtl_data {
pass. */
bool bb_reorder_complete;
+ /* Nonzero if pass_free_cfg has run. */
+ bool cfg_released;
+
/* Like regs_ever_live, but 1 if a reg is set or clobbered from an
asm. Unlike regs_ever_live, elements of this array corresponding
to eliminable regs (like the frame pointer) are set if an asm
Index: cfgrtl.c
===================================================================
--- cfgrtl.c(revision 199028)
+++ cfgrtl.c(working copy)
< at >< at > -452,6 +452,7 < at >< at > rest_of_pass_free_cfg (void)
#endif
free_bb_for_insn ();
+ crtl->cfg_released = true;
return 0;
}
Index: tree-pass.h
===================================================================
--- tree-pass.h(revision 199028)
+++ tree-pass.h(working copy)
< at >< at > -474,6 +474,8 < at >< at > extern struct rtl_opt_pass pass_duplicat
extern struct rtl_opt_pass pass_variable_tracking;
extern struct rtl_opt_pass pass_free_cfg;
extern struct rtl_opt_pass pass_machine_reorg;
+extern struct rtl_opt_pass pass_cfg_unaware_passes;
+extern struct rtl_opt_pass pass_machine_reorg_nocfg;
extern struct rtl_opt_pass pass_cleanup_barriers;
extern struct rtl_opt_pass pass_delay_slots;
extern struct rtl_opt_pass pass_split_for_shorten_branches;
Index: passes.c
===================================================================
--- passes.c(revision 199028)
+++ passes.c(working copy)
< at >< at > -1659,10 +1659,15 < at >< at > init_optimization_passes (void)
NEXT_PASS (pass_compute_alignments);
NEXT_PASS (pass_duplicate_computed_gotos);
NEXT_PASS (pass_variable_tracking);
- NEXT_PASS (pass_free_cfg);
NEXT_PASS (pass_machine_reorg);
- NEXT_PASS (pass_cleanup_barriers);
- NEXT_PASS (pass_delay_slots);
+ NEXT_PASS (pass_cfg_unaware_passes);
+ {
+ struct opt_pass **p = &pass_cfg_unaware_passes.pass.sub;
+ NEXT_PASS (pass_free_cfg);
+ NEXT_PASS (pass_machine_reorg_nocfg);
+ NEXT_PASS (pass_cleanup_barriers);
+ NEXT_PASS (pass_delay_slots);
+ }
NEXT_PASS (pass_split_for_shorten_branches);
NEXT_PASS (pass_convert_to_eh_region_ranges);
NEXT_PASS (pass_shorten_branches);
Index: reorg.c
===================================================================
--- reorg.c(revision 199028)
+++ reorg.c(working copy)
< at >< at > -3871,15 +3871,83 < at >< at > struct rtl_opt_pass pass_delay_slots =
0 /* todo_flags_finish */
}
};
+
+/* Machine dependent reorg pass, not CFG aware. */
+static bool
+gate_handle_machine_reorg_nocfg (void)
+{
+ return targetm.machine_dependent_reorg_nocfg != 0;
+}
+
+static unsigned int
+rest_of_handle_machine_reorg_nocfg (void)
+{
+ targetm.machine_dependent_reorg_nocfg ();
+ return 0;
+}
+
+struct rtl_opt_pass pass_machine_reorg_nocfg =
+{
+ {
+ RTL_PASS,
+ "mach_nocfg", /* name */
+ OPTGROUP_NONE, /* optinfo_flags */
+ gate_handle_machine_reorg_nocfg, /* gate */
+ rest_of_handle_machine_reorg_nocfg, /* execute */
+ NULL, /* sub */
+ NULL, /* next */
+ 0, /* static_pass_number */
+ TV_MACH_DEP, /* tv_id */
+ 0, /* properties_required */
+ 0, /* properties_provided */
+ 0, /* properties_destroyed */
+ 0, /* todo_flags_start */
+ 0 /* todo_flags_finish */
+ }
+};
+
+/* pass_delay_slots and rest_of_handle_machine_reorg_nocfg are not CFG-aware,
+ which means they do not properly maintain it and may even fail if the
+ BLOCK_FOR_INSN pointers are not cleared.
+ These CFG-unaware passes are grouped in pass_cfg_unaware_passes. */
-/* Machine dependent reorg pass. */
+static bool
+gate_cfg_unaware_passes (void)
+{
+#ifdef DELAY_SLOTS
+ return 1;
+#else
+ return gate_handle_machine_reorg_nocfg ();
+#endif
+}
+
+struct rtl_opt_pass pass_cfg_unaware_passes =
+{
+ {
+ RTL_PASS,
+ "*cfg_unaware", /* name */
+ OPTGROUP_NONE, /* optinfo_flags */
+ gate_cfg_unaware_passes, /* gate */
+ NULL,/* execute */
+ NULL, /* sub */
+ NULL, /* next */
+ 0, /* static_pass_number */
+ TV_NONE, /* tv_id */
+ 0, /* properties_required */
+ 0, /* properties_provided */
+ 0, /* properties_destroyed */
+ 0, /* todo_flags_start */
+ 0 /* todo_flags_finish */
+ }
+};
+
+/* CFG-aware machine dependent reorg pass. */
static bool
gate_handle_machine_reorg (void)
{
return targetm.machine_dependent_reorg != 0;
}
-
static unsigned int
rest_of_handle_machine_reorg (void)
{
< at >< at > -3903,6 +3971,7 < at >< at > struct rtl_opt_pass pass_machine_reorg =
0, /* properties_provided */
0, /* properties_destroyed */
0, /* todo_flags_start */
- 0 /* todo_flags_finish */
+ TODO_verify_flow /* todo_flags_finish */
}
};
+
Index: recog.c
===================================================================
--- recog.c(revision 199028)
+++ recog.c(working copy)
< at >< at > -3927,6 +3927,23 < at >< at > gate_do_final_split (void)
#endif
}
+static unsigned int
+rest_of_handle_final_split (void)
+{
+ if (crtl->cfg_released)
+ split_all_insns_noflow ();
+ else
+ {
+ /* Most targets expect the CFG to be destroyed at this point,
+ but some keep the CFG alive all the way to the final pass. */
+ split_all_insns ();
+#ifdef ENABLE_CHECKING
+ verify_flow_info ();
+#endif
+ }
+ return 0;
+}
+
struct rtl_opt_pass pass_split_for_shorten_branches =
{
{
< at >< at > -3934,7 +3951,7 < at >< at > struct rtl_opt_pass pass_split_for_short
"split5", /* name */
OPTGROUP_NONE, /* optinfo_flags */
gate_do_final_split, /* gate */
- split_all_insns_noflow, /* execute */
+ rest_of_handle_final_split, /* execute */
NULL, /* sub */
NULL, /* next */
0, /* static_pass_number */
Index: sched-ebb.c
===================================================================
--- sched-ebb.c(revision 199028)
+++ sched-ebb.c(working copy)
< at >< at > -593,8 +593,6 < at >< at > schedule_ebbs_init (void)
haifa_sched_init ();
- compute_bb_for_insn ();
-
/* Initialize DONT_CALC_DEPS and ebb-{start, end} markers. */
bitmap_initialize (&dont_calc_deps, 0);
bitmap_clear (&dont_calc_deps);
Index: config/i386/i386.c
===================================================================
--- config/i386/i386.c(revision 199028)
+++ config/i386/i386.c(working copy)
< at >< at > -35569,10 +35569,6 < at >< at > ix86_pad_short_function (void)
static void
ix86_reorg (void)
{
- /* We are freeing block_for_insn in the toplev to keep compatibility
- with old MDEP_REORGS that are not CFG based. Recompute it now. */
- compute_bb_for_insn ();
-
if (optimize && optimize_function_for_speed_p (cfun))
{
if (TARGET_PAD_SHORT_FUNCTION)
Index: config/alpha/alpha.c
===================================================================
--- config/alpha/alpha.c(revision 199028)
+++ config/alpha/alpha.c(working copy)
< at >< at > -9807,8 +9807,8 < at >< at > alpha_canonicalize_comparison (int *code
#undef TARGET_ADDRESS_COST
#define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
-#undef TARGET_MACHINE_DEPENDENT_REORG
-#define TARGET_MACHINE_DEPENDENT_REORG alpha_reorg
+#undef TARGET_MACHINE_DEPENDENT_REORG_NOCFG
+#define TARGET_MACHINE_DEPENDENT_REORG_NOCFG alpha_reorg
#undef TARGET_PROMOTE_FUNCTION_MODE
#define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
Index: config/frv/frv.c
===================================================================
--- config/frv/frv.c(revision 199028)
+++ config/frv/frv.c(working copy)
< at >< at > -477,8 +477,8 < at >< at > static bool frv_class_likely_spilled_p
#define TARGET_EXPAND_BUILTIN_SAVEREGS frv_expand_builtin_saveregs
#undef TARGET_SETUP_INCOMING_VARARGS
#define TARGET_SETUP_INCOMING_VARARGS frv_setup_incoming_varargs
-#undef TARGET_MACHINE_DEPENDENT_REORG
-#define TARGET_MACHINE_DEPENDENT_REORG frv_reorg
+#undef TARGET_MACHINE_DEPENDENT_REORG_NOCFG
+#define TARGET_MACHINE_DEPENDENT_REORG_NOCFG frv_reorg
#undef TARGET_EXPAND_BUILTIN_VA_START
#define TARGET_EXPAND_BUILTIN_VA_START frv_expand_builtin_va_start
< at >< at > -8182,7 +8182,7 < at >< at > frv_register_nop (rtx nop)
frv_nops[frv_num_nops++] = nop;
}
-/* Implement TARGET_MACHINE_DEPENDENT_REORG. Divide the instructions
+/* Implement TARGET_MACHINE_DEPENDENT_REORG_NOCFG. Divide the instructions
into packets and check whether we need to insert nops in order to
fulfill the processor's issue requirements. Also, if the user has
requested a certain alignment for a label, try to meet that alignment
Index: config/s390/s390.c
===================================================================
--- config/s390/s390.c(revision 199028)
+++ config/s390/s390.c(working copy)
< at >< at > -11036,8 +11036,8 < at >< at > s390_loop_unroll_adjust (unsigned nunrol
#undef TARGET_MEMORY_MOVE_COST
#define TARGET_MEMORY_MOVE_COST s390_memory_move_cost
-#undef TARGET_MACHINE_DEPENDENT_REORG
-#define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
+#undef TARGET_MACHINE_DEPENDENT_REORG_NOCFG
+#define TARGET_MACHINE_DEPENDENT_REORG_NOCFG s390_reorg
#undef TARGET_VALID_POINTER_MODE
#define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
Index: config/spu/spu.c
===================================================================
--- config/spu/spu.c(revision 199028)
+++ config/spu/spu.c(working copy)
< at >< at > -7240,8 +7240,8 < at >< at > static const struct attribute_spec spu_a
#undef TARGET_SETUP_INCOMING_VARARGS
#define TARGET_SETUP_INCOMING_VARARGS spu_setup_incoming_varargs
-#undef TARGET_MACHINE_DEPENDENT_REORG
-#define TARGET_MACHINE_DEPENDENT_REORG spu_machine_dependent_reorg
+#undef TARGET_MACHINE_DEPENDENT_REORG_NOCFG
+#define TARGET_MACHINE_DEPENDENT_REORG_NOCFG spu_machine_dependent_reorg
#undef TARGET_GIMPLIFY_VA_ARG_EXPR
#define TARGET_GIMPLIFY_VA_ARG_EXPR spu_gimplify_va_arg_expr
Index: config/mep/mep.c
===================================================================
--- config/mep/mep.c(revision 199028)
+++ config/mep/mep.c(working copy)
< at >< at > -7242,8 +7242,8 < at >< at > mep_asm_init_sections (void)
#define TARGET_RTX_COSTSmep_rtx_cost
#undef TARGET_ADDRESS_COST
#define TARGET_ADDRESS_COST mep_address_cost
-#undef TARGET_MACHINE_DEPENDENT_REORG
-#define TARGET_MACHINE_DEPENDENT_REORG mep_reorg
+#undef TARGET_MACHINE_DEPENDENT_REORG_NOCFG
+#define TARGET_MACHINE_DEPENDENT_REORG_NOCFG mep_reorg
#undef TARGET_SETUP_INCOMING_VARARGS
#define TARGET_SETUP_INCOMING_VARARGSmep_setup_incoming_varargs
#undef TARGET_PASS_BY_REFERENCE
Index: config/tilegx/tilegx.c
===================================================================
--- config/tilegx/tilegx.c(revision 199028)
+++ config/tilegx/tilegx.c(working copy)
< at >< at > -5549,8 +5549,8 < at >< at > tilegx_file_end (void)
#undef TARGET_SCHED_ADJUST_COST
#define TARGET_SCHED_ADJUST_COST tilegx_sched_adjust_cost
-#undef TARGET_MACHINE_DEPENDENT_REORG
-#define TARGET_MACHINE_DEPENDENT_REORG tilegx_reorg
+#undef TARGET_MACHINE_DEPENDENT_REORG_NOCFG
+#define TARGET_MACHINE_DEPENDENT_REORG_NOCFG tilegx_reorg
#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
#define TARGET_ASM_CAN_OUTPUT_MI_THUNK \
Index: config/sh/sh.c
===================================================================
--- config/sh/sh.c(revision 199028)
+++ config/sh/sh.c(working copy)
< at >< at > -490,8 +490,8 < at >< at > static const struct attribute_spec sh_at
#undef TARGET_ALLOCATE_INITIAL_VALUE
#define TARGET_ALLOCATE_INITIAL_VALUE sh_allocate_initial_value
-#undef TARGET_MACHINE_DEPENDENT_REORG
-#define TARGET_MACHINE_DEPENDENT_REORG sh_reorg
+#undef TARGET_MACHINE_DEPENDENT_REORG_NOCFG
+#define TARGET_MACHINE_DEPENDENT_REORG_NOCFG sh_reorg
#undef TARGET_DWARF_REGISTER_SPAN
#define TARGET_DWARF_REGISTER_SPAN sh_dwarf_register_span
Index: config/avr/avr.c
===================================================================
--- config/avr/avr.c(revision 199028)
+++ config/avr/avr.c(working copy)
< at >< at > -9683,7 +9683,7 < at >< at > avr_reorg_remove_redundant_compare (rtx
}
-/* Implement `TARGET_MACHINE_DEPENDENT_REORG'. */
+/* Implement `TARGET_MACHINE_DEPENDENT_REORG_NOCFG'. */
/* Optimize conditional jumps. */
static void
< at >< at > -12141,8 +12141,8 < at >< at > avr_fold_builtin (tree fndecl, int n_arg
#define TARGET_RTX_COSTS avr_rtx_costs
#undef TARGET_ADDRESS_COST
#define TARGET_ADDRESS_COST avr_address_cost
-#undef TARGET_MACHINE_DEPENDENT_REORG
-#define TARGET_MACHINE_DEPENDENT_REORG avr_reorg
+#undef TARGET_MACHINE_DEPENDENT_REORG_NOCFG
+#define TARGET_MACHINE_DEPENDENT_REORG_NOCFG avr_reorg
#undef TARGET_FUNCTION_ARG
#define TARGET_FUNCTION_ARG avr_function_arg
#undef TARGET_FUNCTION_ARG_ADVANCE
Index: config/stormy16/stormy16.c
===================================================================
--- config/stormy16/stormy16.c(revision 199028)
+++ config/stormy16/stormy16.c(working copy)
< at >< at > -2664,8 +2664,8 < at >< at > xstormy16_return_in_memory (const_tree t
#undef TARGET_FUNCTION_VALUE_REGNO_P
#define TARGET_FUNCTION_VALUE_REGNO_P xstormy16_function_value_regno_p
-#undef TARGET_MACHINE_DEPENDENT_REORG
-#define TARGET_MACHINE_DEPENDENT_REORG xstormy16_reorg
+#undef TARGET_MACHINE_DEPENDENT_REORG_NOCFG
+#define TARGET_MACHINE_DEPENDENT_REORG_NOCFG xstormy16_reorg
#undef TARGET_PREFERRED_RELOAD_CLASS
#define TARGET_PREFERRED_RELOAD_CLASS xstormy16_preferred_reload_class
Index: config/mn10300/mn10300.c
===================================================================
--- config/mn10300/mn10300.c(revision 199028)
+++ config/mn10300/mn10300.c(working copy)
< at >< at > -3308,8 +3308,8 < at >< at > mn10300_reorg (void)
/* Initialize the GCC target structure. */
-#undef TARGET_MACHINE_DEPENDENT_REORG
-#define TARGET_MACHINE_DEPENDENT_REORG mn10300_reorg
+#undef TARGET_MACHINE_DEPENDENT_REORG_NOCFG
+#define TARGET_MACHINE_DEPENDENT_REORG_NOCFG mn10300_reorg
#undef TARGET_ASM_ALIGNED_HI_OP
#define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
Index: config/c6x/c6x.c
===================================================================
--- config/c6x/c6x.c(revision 199028)
+++ config/c6x/c6x.c(working copy)
< at >< at > -5893,9 +5893,9 < at >< at > c6x_hwloops (void)
reorg_loops (true, &c6x_doloop_hooks);
}
-/* Implement the TARGET_MACHINE_DEPENDENT_REORG pass. We split call insns here
- into a sequence that loads the return register and performs the call,
- and emit the return label.
+/* Implement the TARGET_MACHINE_DEPENDENT_REORG_NOCFG pass.
+ We split call insns here into a sequence that loads the return
+ register and performs the call, and emit the return label.
If scheduling after reload is requested, it happens here. */
static void
< at >< at > -6796,8 +6796,8 < at >< at > c6x_debug_unwind_info (void)
#undef TARGET_PREFERRED_RENAME_CLASS
#define TARGET_PREFERRED_RENAME_CLASS c6x_preferred_rename_class
-#undef TARGET_MACHINE_DEPENDENT_REORG
-#define TARGET_MACHINE_DEPENDENT_REORG c6x_reorg
+#undef TARGET_MACHINE_DEPENDENT_REORG_NOCFG
+#define TARGET_MACHINE_DEPENDENT_REORG_NOCFG c6x_reorg
#undef TARGET_ASM_FILE_START
#define TARGET_ASM_FILE_START c6x_file_start
Index: config/ia64/ia64.c
===================================================================
--- config/ia64/ia64.c(revision 199028)
+++ config/ia64/ia64.c(working copy)
< at >< at > -527,8 +527,8 < at >< at > static const struct attribute_spec ia64_
#undef TARGET_UNSPEC_MAY_TRAP_P
#define TARGET_UNSPEC_MAY_TRAP_P ia64_unspec_may_trap_p
-#undef TARGET_MACHINE_DEPENDENT_REORG
-#define TARGET_MACHINE_DEPENDENT_REORG ia64_reorg
+#undef TARGET_MACHINE_DEPENDENT_REORG_NOCFG
+#define TARGET_MACHINE_DEPENDENT_REORG_NOCFG ia64_reorg
#undef TARGET_ENCODE_SECTION_INFO
#define TARGET_ENCODE_SECTION_INFO ia64_encode_section_info
< at >< at > -9637,10 +9637,6 < at >< at > emit_predicate_relation_info (void)
static void
ia64_reorg (void)
{
- /* We are freeing block_for_insn in the toplev to keep compatibility
- with old MDEP_REORGS that are not CFG based. Recompute it now. */
- compute_bb_for_insn ();
-
/* If optimizing, we'll have split before scheduling. */
if (optimize == 0)
split_all_insns ();
Index: config/picochip/picochip.c
===================================================================
--- config/picochip/picochip.c(revision 199028)
+++ config/picochip/picochip.c(working copy)
< at >< at > -255,8 +255,8 < at >< at > static char picochip_get_vliw_alu_id (vo
#undef TARGET_ASM_FILE_END
#define TARGET_ASM_FILE_END picochip_asm_file_end
-#undef TARGET_MACHINE_DEPENDENT_REORG
-#define TARGET_MACHINE_DEPENDENT_REORG picochip_reorg
+#undef TARGET_MACHINE_DEPENDENT_REORG_NOCFG
+#define TARGET_MACHINE_DEPENDENT_REORG_NOCFG picochip_reorg
#undef TARGET_ARG_PARTIAL_BYTES
#define TARGET_ARG_PARTIAL_BYTES picochip_arg_partial_bytes
Index: config/mcore/mcore.c
===================================================================
--- config/mcore/mcore.c(revision 199028)
+++ config/mcore/mcore.c(working copy)
< at >< at > -191,8 +191,8 < at >< at > static const struct attribute_spec mcore
#define TARGET_RTX_COSTS mcore_rtx_costs
#undef TARGET_ADDRESS_COST
#define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
-#undef TARGET_MACHINE_DEPENDENT_REORG
-#define TARGET_MACHINE_DEPENDENT_REORGmcore_reorg
+#undef TARGET_MACHINE_DEPENDENT_REORG_NOCFG
+#define TARGET_MACHINE_DEPENDENT_REORG_NOCFGmcore_reorg
#undef TARGET_PROMOTE_FUNCTION_MODE
#define TARGET_PROMOTE_FUNCTION_MODEdefault_promote_function_mode_always_promote
Index: config/tilepro/tilepro.c
===================================================================
--- config/tilepro/tilepro.c(revision 199028)
+++ config/tilepro/tilepro.c(working copy)
< at >< at > -5041,8 +5041,8 < at >< at > tilepro_file_end (void)
#undef TARGET_SCHED_ADJUST_COST
#define TARGET_SCHED_ADJUST_COST tilepro_sched_adjust_cost
-#undef TARGET_MACHINE_DEPENDENT_REORG
-#define TARGET_MACHINE_DEPENDENT_REORG tilepro_reorg
+#undef TARGET_MACHINE_DEPENDENT_REORG_NOCFG
+#define TARGET_MACHINE_DEPENDENT_REORG_NOCFG tilepro_reorg
#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
#define TARGET_ASM_CAN_OUTPUT_MI_THUNK \
Index: config/arm/arm.c
===================================================================
--- config/arm/arm.c(revision 199028)
+++ config/arm/arm.c(working copy)
< at >< at > -434,8 +434,8 < at >< at > static const struct attribute_spec arm_a
#define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
arm_autovectorize_vector_sizes
-#undef TARGET_MACHINE_DEPENDENT_REORG
-#define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
+#undef TARGET_MACHINE_DEPENDENT_REORG_NOCFG
+#define TARGET_MACHINE_DEPENDENT_REORG_NOCFG arm_reorg
#undef TARGET_INIT_BUILTINS
#define TARGET_INIT_BUILTINS arm_init_builtins
Index: config/pa/pa.c
===================================================================
--- config/pa/pa.c(revision 199028)
+++ config/pa/pa.c(working copy)
< at >< at > -313,8 +313,8 < at >< at > static size_t n_deferred_plabels = 0;
#undef TARGET_ADDRESS_COST
#define TARGET_ADDRESS_COST hppa_address_cost
-#undef TARGET_MACHINE_DEPENDENT_REORG
-#define TARGET_MACHINE_DEPENDENT_REORG pa_reorg
+#undef TARGET_MACHINE_DEPENDENT_REORG_NOCFG
+#define TARGET_MACHINE_DEPENDENT_REORG_NOCFG pa_reorg
#undef TARGET_INIT_LIBFUNCS
#define TARGET_INIT_LIBFUNCS pa_init_libfuncs
Index: config/mips/mips.c
===================================================================
--- config/mips/mips.c(revision 199028)
+++ config/mips/mips.c(working copy)
< at >< at > -16255,7 +16255,7 < at >< at > mips16_split_long_branches (void)
while (something_changed);
}
-/* Implement TARGET_MACHINE_DEPENDENT_REORG. */
+/* Implement TARGET_MACHINE_DEPENDENT_REORG_NOCFG. */
static void
mips_reorg (void)
< at >< at > -18619,8 +18619,8 < at >< at > mips_expand_vec_minmax (rtx target, rtx
#undef TARGET_IN_SMALL_DATA_P
#define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
-#undef TARGET_MACHINE_DEPENDENT_REORG
-#define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
+#undef TARGET_MACHINE_DEPENDENT_REORG_NOCFG
+#define TARGET_MACHINE_DEPENDENT_REORG_NOCFG mips_reorg
#undef TARGET_PREFERRED_RELOAD_CLASS
#define TARGET_PREFERRED_RELOAD_CLASS mips_preferred_reload_class
Index: config/v850/v850.c
===================================================================
--- config/v850/v850.c(revision 199028)
+++ config/v850/v850.c(working copy)
< at >< at > -1212,7 +1212,7 < at >< at > Saved %d bytes (%d uses of register %s)
}
-/* TARGET_MACHINE_DEPENDENT_REORG. On the 850, we use it to implement
+/* TARGET_MACHINE_DEPENDENT_REORG_NOCFG. On the 850, we use it to implement
the -mep mode to copy heavily used pointers to ep to use the implicit
addressing. */
< at >< at > -3223,8 +3223,8 < at >< at > v850_gen_movdi (rtx * operands)
#undef TARGET_ADDRESS_COST
#define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
-#undef TARGET_MACHINE_DEPENDENT_REORG
-#define TARGET_MACHINE_DEPENDENT_REORG v850_reorg
+#undef TARGET_MACHINE_DEPENDENT_REORG_NOCFG
+#define TARGET_MACHINE_DEPENDENT_REORG_NOCFG v850_reorg
#undef TARGET_SCHED_ISSUE_RATE
#define TARGET_SCHED_ISSUE_RATE v850_issue_rate
Index: config/h8300/h8300.c
===================================================================
--- config/h8300/h8300.c(revision 199028)
+++ config/h8300/h8300.c(working copy)
< at >< at > -6071,8 +6071,8 < at >< at > h8300_trampoline_init (rtx m_tramp, tree
#undef TARGET_FUNCTION_ARG_ADVANCE
#define TARGET_FUNCTION_ARG_ADVANCE h8300_function_arg_advance
-#undef TARGET_MACHINE_DEPENDENT_REORG
-#define TARGET_MACHINE_DEPENDENT_REORG h8300_reorg
+#undef TARGET_MACHINE_DEPENDENT_REORG_NOCFG
+#define TARGET_MACHINE_DEPENDENT_REORG_NOCFG h8300_reorg
#undef TARGET_HARD_REGNO_SCRATCH_OK
#define TARGET_HARD_REGNO_SCRATCH_OK h8300_hard_regno_scratch_ok
Index: config/mmix/mmix.c
===================================================================
--- config/mmix/mmix.c(revision 199028)
+++ config/mmix/mmix.c(working copy)
< at >< at > -226,8 +226,8 < at >< at > static void mmix_conditional_register_us
#undef TARGET_REGISTER_MOVE_COST
#define TARGET_REGISTER_MOVE_COST mmix_register_move_cost
-#undef TARGET_MACHINE_DEPENDENT_REORG
-#define TARGET_MACHINE_DEPENDENT_REORG mmix_reorg
+#undef TARGET_MACHINE_DEPENDENT_REORG_NOCFG
+#define TARGET_MACHINE_DEPENDENT_REORG_NOCFG mmix_reorg
#undef TARGET_PROMOTE_FUNCTION_MODE
#define TARGET_PROMOTE_FUNCTION_MODE mmix_promote_function_mode
< at >< at > -828,7 +828,7 < at >< at > mmix_target_asm_function_end_prologue (F
cfun->machine->in_prologue = 0;
}
-/* Implement TARGET_MACHINE_DEPENDENT_REORG. No actual rearrangements
+/* Implement TARGET_MACHINE_DEPENDENT_REORG_NOCFG. No actual rearrangements
done here; just virtually by calculating the highest saved stack
register number used to modify the register numbers at output time. */
Index: config/bfin/bfin.c
===================================================================
--- config/bfin/bfin.c(revision 199028)
+++ config/bfin/bfin.c(working copy)
< at >< at > -5717,8 +5717,8 < at >< at > bfin_conditional_register_usage (void)
#undef TARGET_ASM_INTEGER
#define TARGET_ASM_INTEGER bfin_assemble_integer
-#undef TARGET_MACHINE_DEPENDENT_REORG
-#define TARGET_MACHINE_DEPENDENT_REORG bfin_reorg
+#undef TARGET_MACHINE_DEPENDENT_REORG_NOCFG
+#define TARGET_MACHINE_DEPENDENT_REORG_NOCFG bfin_reorg
#undef TARGET_FUNCTION_OK_FOR_SIBCALL
#define TARGET_FUNCTION_OK_FOR_SIBCALL bfin_function_ok_for_sibcall
</pre>Steven Bosscher2013-05-19T15:59:55[C++ Patch] PR 57327
http://comments.gmane.org/gmane.comp.gcc.patches/286095
<pre>Hi,
a simple issue noticed by Jon, swap the arguments to inform. Tested
x86_64-linux.
Thanks,
Paolo.
////////////////////////
/cp
2013-05-19 Paolo Carlini <paolo.carlini< at >oracle.com>
PR c++/57327
* pt.c (unify_no_common_base): Swap arg and parm arguments to inform.
/testsuite
2013-05-19 Paolo Carlini <paolo.carlini< at >oracle.com>
PR c++/57327
* g++.dg/template/error50.C: New.
Index: cp/pt.c
===================================================================
--- cp/pt.c(revision 199076)
+++ cp/pt.c(working copy)
< at >< at > -5375,7 +5375,7 < at >< at > unify_no_common_base (bool explain_p, enum templat
{
case tbr_ambiguous_baseclass:
inform (input_location, " %qT is an ambiguous base class of %qT",
-arg, parm);
+parm, arg);
break;
default:
inform (input_location, " %qT is not derived from %qT", arg, parm);
Index: testsuite/g++.dg/template/error50.C
===================================================================
--- testsuite/g++.dg/template/error50.C(revision 0)
+++ testsuite/g++.dg/template/error50.C(working copy)
< at >< at > -0,0 +1,19 < at >< at >
+// PR c++/57327
+
+template<class T>
+struct A {};
+
+template<class T>
+void f(A<T>&) {}
+
+struct B : A<long> {};
+
+struct C : A<char> {};
+
+struct D : B, C {};
+
+int main()
+{
+ D d;
+ f(d); // { dg-error "no matching" }
+} // { dg-message "'A<T>' is an ambiguous base" "" { target *-*-* } 18 }
</pre>Paolo Carlini2013-05-19T11:14:03[MIPS, committed] Give MIPS16 instruction lengths directly
http://comments.gmane.org/gmane.comp.gcc.patches/286092
<pre>The .md "length" attributes for MIPS16 instructions have traditionally
been double their real values, with a compensating:
if (TARGET_MIPS16)
length /= 2;
in ADJUST_INSN_LENGTH. This was probably the most expedient way of
doing things way back when, because many patterns specified the
length directly. However, these days the length is often inferred
from other attributes like extended_mips16, and this doubling trick
probably hinders more than it helps. E.g. I notice that we don't
double the size of the constant table patterns, so I think they ended
up being too small. Doubling also made the branch calculations more
confusing, since the ranges had to be specified in real units,
but the resulting branch lengths had to be specified in doubled units.
This patch instead specifies the real lengths directly. This involves
adding a macro to give the length of a nop insn, and since microMIPS
also has 16-bit NOPs, I used TARGET_COMPRESSION rather than TARGET_MIPS16.
Also, the JR in a microMIPS long branch sequence is 2 bytes rather than 4.
Tested on mipsisa32-sde-elf and applied.
Richard
gcc/
* config/mips/mips.h (BASE_INSN_LENGTH, NOP_INSN_LENGTH): New macros.
* config/mips/mips.c (mips_symbol_insns, mips_address_insns)
(mips_const_insns, mips_split_const_insns, mips_load_store_insns)
(mips_idiv_insns): Update the comments to say that the returned
instruction counts are in units of BASE_INSN_LENGTH.
(mips_adjust_insn_length): Multiply the mips_load_label_num_insns
by BASE_INSN_LENGTH rather than 4. Add the jump separately,
using 2 rather than 4 as the length of indirect MIPS16 and
microMIPS jumps. Use NOP_INSN_LENGTH rather than 4 as the
length of a NOP. Don't divide MIPS16 lengths by 2.
(mips16_split_long_branches): Assume a branch is long if the
length is greater than 4 rather than 8.
* config/mips/mips.md (length): Give MIPS16 lengths directly,
rather than multiplying them by 2. Multiply instruction counts
by BASE_INSN_LENGTH rather than 4.
(*jump_mips16, tls_get_tp_mips16_<mode>)
(*tls_get_tp_mips16_call_<mode>): Divide lengths by 2.
Index: gcc/config/mips/mips.h
===================================================================
--- gcc/config/mips/mips.h2013-05-19 11:05:09.987763980 +0100
+++ gcc/config/mips/mips.h2013-05-19 11:10:32.138190186 +0100
< at >< at > -2439,6 +2439,14 < at >< at > #define AVOID_CCMODE_COPIES
#define BRANCH_COST(speed_p, predictable_p) mips_branch_cost
#define LOGICAL_OP_NON_SHORT_CIRCUIT 0
+/* The MIPS port has several functions that return an instruction count.
+ Multiplying the count by this value gives the number of bytes that
+ the instructions occupy. */
+#define BASE_INSN_LENGTH (TARGET_MIPS16 ? 2 : 4)
+
+/* The length of a NOP in bytes. */
+#define NOP_INSN_LENGTH (TARGET_COMPRESSION ? 2 : 4)
+
/* If defined, modifies the length assigned to instruction INSN as a
function of the context in which it is used. LENGTH is an lvalue
that contains the initially computed length of the insn and should
Index: gcc/config/mips/mips.c
===================================================================
--- gcc/config/mips/mips.c2013-05-19 11:05:09.987763980 +0100
+++ gcc/config/mips/mips.c2013-05-19 11:10:32.137190179 +0100
< at >< at > -2007,7 +2007,7 < at >< at > mips_symbol_insns_1 (enum mips_symbol_ty
values of mode MODE to or from addresses of type TYPE. Return 0 if
the given type of symbol is not valid in addresses.
- In both cases, treat extended MIPS16 instructions as two instructions. */
+ In both cases, instruction counts are based off BASE_INSN_LENGTH. */
static int
mips_symbol_insns (enum mips_symbol_type type, enum machine_mode mode)
< at >< at > -2334,12 +2334,11 < at >< at > mips16_unextended_reference_p (enum mach
}
/* Return the number of instructions needed to load or store a value
- of mode MODE at address X. Return 0 if X isn't valid for MODE.
+ of mode MODE at address X, assuming that BASE_INSN_LENGTH is the
+ length of one instruction. Return 0 if X isn't valid for MODE.
Assume that multiword moves may need to be split into word moves
if MIGHT_SPLIT_P, otherwise assume that a single load or store is
- enough.
-
- For MIPS16 code, count extended instructions as two instructions. */
+ enough. */
int
mips_address_insns (rtx x, enum machine_mode mode, bool might_split_p)
< at >< at > -2441,7 +2440,8 < at >< at > umips_12bit_offset_address_p (rtx x, enu
&& UMIPS_12BIT_OFFSET_P (INTVAL (addr.offset)));
}
-/* Return the number of instructions needed to load constant X.
+/* Return the number of instructions needed to load constant X,
+ assuming that BASE_INSN_LENGTH is the length of one instruction.
Return 0 if X isn't a valid constant. */
int
< at >< at > -2524,7 +2524,8 < at >< at > mips_const_insns (rtx x)
/* X is a doubleword constant that can be handled by splitting it into
two words and loading each word separately. Return the number of
- instructions required to do this. */
+ instructions required to do this, assuming that BASE_INSN_LENGTH
+ is the length of one instruction. */
int
mips_split_const_insns (rtx x)
< at >< at > -2538,8 +2539,8 < at >< at > mips_split_const_insns (rtx x)
}
/* Return the number of instructions needed to implement INSN,
- given that it loads from or stores to MEM. Count extended
- MIPS16 instructions as two instructions. */
+ given that it loads from or stores to MEM. Assume that
+ BASE_INSN_LENGTH is the length of one instruction. */
int
mips_load_store_insns (rtx mem, rtx insn)
< at >< at > -2563,7 +2564,8 < at >< at > mips_load_store_insns (rtx mem, rtx insn
return mips_address_insns (XEXP (mem, 0), mode, might_split_p);
}
-/* Return the number of instructions needed for an integer division. */
+/* Return the number of instructions needed for an integer division,
+ assuming that BASE_INSN_LENGTH is the length of one instruction. */
int
mips_idiv_insns (void)
< at >< at > -12273,16 +12275,18 < at >< at > mips_adjust_insn_length (rtx insn, int l
is a conditional branch. */
length = simplejump_p (insn) ? 0 : 8;
- /* Load the label into $AT and jump to it. Ignore the delay
- slot of the jump. */
- length += 4 * mips_load_label_num_insns() + 4;
+ /* Add the size of a load into $AT. */
+ length += BASE_INSN_LENGTH * mips_load_label_num_insns ();
+
+ /* Add the length of an indirect jump, ignoring the delay slot. */
+ length += TARGET_COMPRESSION ? 2 : 4;
}
/* A unconditional jump has an unfilled delay slot if it is not part
of a sequence. A conditional jump normally has a delay slot, but
does not on MIPS16. */
if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
- length += 4;
+ length += TARGET_MIPS16 ? 2 : 4;
/* See how many nops might be needed to avoid hardware hazards. */
if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
< at >< at > -12292,20 +12296,14 < at >< at > mips_adjust_insn_length (rtx insn, int l
break;
case HAZARD_DELAY:
-length += 4;
+length += NOP_INSN_LENGTH;
break;
case HAZARD_HILO:
-length += 8;
+length += NOP_INSN_LENGTH * 2;
break;
}
- /* In order to make it easier to share MIPS16 and non-MIPS16 patterns,
- the .md file length attributes are 4-based for both modes.
- Adjust the MIPS16 ones here. */
- if (TARGET_MIPS16)
- length /= 2;
-
return length;
}
< at >< at > -16201,7 +16199,7 < at >< at > mips16_split_long_branches (void)
something_changed = false;
for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
if (JUMP_P (insn)
- && get_attr_length (insn) > 8
+ && get_attr_length (insn) > 4
&& (any_condjump_p (insn) || any_uncondjump_p (insn)))
{
rtx old_label, new_label, temp, saved_temp;
Index: gcc/config/mips/mips.md
===================================================================
--- gcc/config/mips/mips.md2013-05-19 11:05:09.987763980 +0100
+++ gcc/config/mips/mips.md2013-05-19 11:11:29.059618158 +0100
< at >< at > -425,7 +425,7 < at >< at > (define_attr "enabled" "no,yes"
(define_attr "length" ""
(cond [(and (eq_attr "extended_mips16" "yes")
(match_test "TARGET_MIPS16"))
- (const_int 8)
+ (const_int 4)
(and (eq_attr "compression" "micromips,all")
(eq_attr "dword_mode" "no")
< at >< at > -567,68 +567,69 < at >< at > (define_attr "length" ""
;; move $2,$12 bytes
;; foo:
;;(20 bytes in the worst case)
- ;;
- ;; Note that the conditions test adjusted lengths, whereas the
- ;; result is an unadjusted length, and is thus twice the true value.
(and (eq_attr "type" "branch")
(match_test "TARGET_MIPS16"))
(cond [(and (le (minus (match_dup 0) (pc)) (const_int 254))
(le (minus (pc) (match_dup 0)) (const_int 254)))
- (const_int 4)
+ (const_int 2)
(and (le (minus (match_dup 0) (pc)) (const_int 65534))
(le (minus (pc) (match_dup 0)) (const_int 65532)))
- (const_int 8)
+ (const_int 4)
(and (match_test "TARGET_ABICALLS")
(not (match_test "TARGET_ABSOLUTE_ABICALLS")))
- (const_int 40)
+ (const_int 20)
(match_test "Pmode == SImode")
- (const_int 32)
- ] (const_int 48))
+ (const_int 16)
+ ] (const_int 24))
;; "Ghost" instructions occupy no space.
(eq_attr "type" "ghost")
(const_int 0)
+ ;; GOT loads are extended MIPS16 instructions and 4-byte
+ ;; microMIPS instructions.
(eq_attr "got" "load")
- (if_then_else (match_test "TARGET_MIPS16")
-(const_int 8)
-(const_int 4))
+ (const_int 4)
+
+ ;; A GOT load followed by an add of $gp.
(eq_attr "got" "xgot_high")
(const_int 8)
;; In general, constant-pool loads are extended instructions.
(eq_attr "move_type" "loadpool")
- (const_int 8)
+ (const_int 4)
;; SHIFT_SHIFTs are decomposed into two separate instructions.
;; They are extended instructions on MIPS16 targets.
(eq_attr "move_type" "shift_shift")
- (if_then_else (match_test "TARGET_MIPS16")
-(const_int 16)
-(const_int 8))
+ (const_int 8)
;; Check for doubleword moves that are decomposed into two
- ;; instructions.
+ ;; instructions. The individual instructions are unextended
+ ;; MIPS16 ones or 2-byte microMIPS ones.
(and (eq_attr "move_type" "mtc,mfc,mtlo,mflo,move")
(eq_attr "dword_mode" "yes"))
- (const_int 8)
+ (if_then_else (match_test "TARGET_COMPRESSION")
+ (const_int 4)
+ (const_int 8))
;; Doubleword CONST{,N} moves are split into two word
;; CONST{,N} moves.
(and (eq_attr "move_type" "const,constN")
(eq_attr "dword_mode" "yes"))
- (symbol_ref "mips_split_const_insns (operands[1]) * 4")
+ (symbol_ref "mips_split_const_insns (operands[1]) * BASE_INSN_LENGTH")
;; Otherwise, constants, loads and stores are handled by external
;; routines.
(eq_attr "move_type" "const,constN")
- (symbol_ref "mips_const_insns (operands[1]) * 4")
+ (symbol_ref "mips_const_insns (operands[1]) * BASE_INSN_LENGTH")
(eq_attr "move_type" "load,fpload")
- (symbol_ref "mips_load_store_insns (operands[1], insn) * 4")
+ (symbol_ref "mips_load_store_insns (operands[1], insn)
+ * BASE_INSN_LENGTH")
(eq_attr "move_type" "store,fpstore")
- (cond [(not (match_test "TARGET_FIX_24K"))
- (symbol_ref "mips_load_store_insns (operands[0], insn) * 4")]
- (symbol_ref "mips_load_store_insns (operands[0], insn) * 4 + 4"))
+ (symbol_ref "mips_load_store_insns (operands[0], insn)
+ * BASE_INSN_LENGTH
+ + (TARGET_FIX_24K ? NOP_INSN_LENGTH : 0)")
;; In the worst case, a call macro will take 8 instructions:
;;
< at >< at > -659,10 +660,14 < at >< at > (define_attr "length" ""
(const_int 8)
(eq_attr "type" "idiv,idiv3")
- (symbol_ref "mips_idiv_insns () * 4")
+ (symbol_ref "mips_idiv_insns () * BASE_INSN_LENGTH")
(not (eq_attr "sync_mem" "none"))
- (symbol_ref "mips_sync_loop_insns (insn, operands) * 4")
+ (symbol_ref "mips_sync_loop_insns (insn, operands)
+ * BASE_INSN_LENGTH")
+
+ (match_test "TARGET_MIPS16")
+ (const_int 2)
] (const_int 4)))
;; Attribute describing the processor.
< at >< at > -5373,7 +5378,7 < at >< at > (define_insn_and_split ""
""
[(set_attr "type""load")
(set_attr "mode""SI")
- (set_attr "length""16")])
+ (set_attr "length""8")])
(define_insn "rotr<mode>3"
[(set (match_operand:GPR 0 "register_operand" "=d")
< at >< at > -5845,16 +5850,16 < at >< at > (define_insn "*jump_mips16"
;; is one instruction shorter than for conditional branches.
(cond [(and (le (minus (match_dup 0) (pc)) (const_int 2046))
(le (minus (pc) (match_dup 0)) (const_int 2046)))
- (const_int 4)
+ (const_int 2)
(and (le (minus (match_dup 0) (pc)) (const_int 65534))
(le (minus (pc) (match_dup 0)) (const_int 65532)))
- (const_int 8)
+ (const_int 4)
(and (match_test "TARGET_ABICALLS")
(not (match_test "TARGET_ABSOLUTE_ABICALLS")))
- (const_int 36)
+ (const_int 18)
(match_test "Pmode == SImode")
- (const_int 28)
- ] (const_int 44)))])
+ (const_int 14)
+ ] (const_int 22)))])
(define_expand "indirect_jump"
[(set (pc) (match_operand 0 "register_operand"))]
< at >< at > -6947,7 +6952,7 < at >< at > (define_insn_and_split "tls_get_tp_mips1
(set (match_dup 0) (reg:P TLS_GET_TP_REGNUM))]
""
[(set_attr "type" "multi")
- (set_attr "length" "16")
+ (set_attr "length" "8")
(set_attr "mode" "<MODE>")])
(define_insn "*tls_get_tp_mips16_call_<mode>"
< at >< at > -6959,7 +6964,7 < at >< at > (define_insn "*tls_get_tp_mips16_call_<m
"HAVE_AS_TLS && TARGET_MIPS16"
{ return MIPS_CALL ("jal", operands, 0, -1); }
[(set_attr "type" "call")
- (set_attr "length" "12")
+ (set_attr "length" "6")
(set_attr "mode" "<MODE>")])
;; Named pattern for expanding thread pointer reference.
</pre>Richard Sandiford2013-05-19T10:15:51[MIPS, committed] Fix compile/20001226-1.c for MIPS16
http://comments.gmane.org/gmane.comp.gcc.patches/286091
<pre>gcc.c-torture/compile/20001226-1.c started failing for MIPS16 after
the microMIPS patch. This was because the patch added a new check of
"extended_mips16" at the top of the "length" attribute, before the
check for branch lengths, and because "extended_mips16" was still set
to "yes" for branch instructions. However, it was really my fault
for not removing the branch check from extended_mips16 when adding
the long branch support.
Fixed as follows. Tested on mipsisa32-sde-elf and applied.
Richard
gcc/
* config/mips/mips.md (extended_mips16): Remove branch case.
(length): Remove duplicated extended_mips16 test.
Index: gcc/config/mips/mips.md
===================================================================
--- gcc/config/mips/mips.md2013-05-19 10:57:13.399153082 +0100
+++ gcc/config/mips/mips.md2013-05-19 10:57:24.039233504 +0100
< at >< at > -407,7 +407,6 < at >< at > (define_attr "cnv_mode" "unknown,I2S,I2D
;; Is this an extended instruction in mips16 mode?
(define_attr "extended_mips16" "no,yes"
(if_then_else (ior (eq_attr "move_type" "sll0")
- (eq_attr "type" "branch")
(eq_attr "jal" "direct"))
(const_string "yes")
(const_string "no")))
< at >< at > -586,10 +585,6 < at >< at > (define_attr "length" ""
(const_int 32)
] (const_int 48))
- (and (eq_attr "extended_mips16" "yes")
- (match_test "TARGET_MIPS16"))
- (const_int 8)
-
;; "Ghost" instructions occupy no space.
(eq_attr "type" "ghost")
(const_int 0)
</pre>Richard Sandiford2013-05-19T09:58:49[MIPS, committed] Remove 64-bit microMIPS multilibs from mips*-sde-elf
http://comments.gmane.org/gmane.comp.gcc.patches/286090
<pre>The microMIPS patch added microMIPS multilibs to mips*-sde-elf. The 32-bit
ones build fine, but the 64-bit ones don't, at least not with FSF binutils.
My impression from:
http://www.cygwin.com/ml/binutils/2010-07/msg00405.html
was that this is expected -- 32-bit has been extensively tested, but the
64-bit side was more theoretical at this stage.
This patch therefore disables the 64-bit microMIPS multilibs,
as is already done for MIPS16. Tested on mips*-sde-elf and applied.
We should consider reverting it once 64-bit microMIPS is known to work
and be useful for at least one core.
Thanks,
Richard
gcc/
* config/mips/t-sde: Don't build 64-bit microMIPS multilibs.
Index: gcc/config/mips/t-sde
===================================================================
--- gcc/config/mips/t-sde2013-03-20 21:01:21.674584349 +0000
+++ gcc/config/mips/t-sde2013-05-18 20:47:11.293525699 +0100
< at >< at > -27,9 +27,11 < at >< at > else
MULTILIB_EXCLUSIONS := !mips32r2/mfp64
endif
-# Don't build 64-bit MIPS16 multilibs.
+# Don't build 64-bit MIPS16 and microMIPS multilibs.
ifneq ($(filter MIPS_ISA_DEFAULT=6%,$(tm_defines)),)
MULTILIB_EXCLUSIONS += !mips32/!mips32r2/mips16
+MULTILIB_EXCLUSIONS += !mips32/!mips32r2/mmicromips
else
MULTILIB_EXCLUSIONS += mips64/mips16 mips64r2/mips16
+MULTILIB_EXCLUSIONS += mips64/mmicromips mips64r2/mmicromips
endif
</pre>Richard Sandiford2013-05-19T09:51:21[patch] fix libstdc++ docbook markup error
http://comments.gmane.org/gmane.comp.gcc.patches/286078
<pre> * doc/xml/manual/status_cxx2011.xml: Fix markup error.
Committed to trunk.
commit 175045eddc4c111600767bd4e3b42929118ae3ba
Author: Jonathan Wakely <jwakely.gcc< at >gmail.com>
Date: Sat May 18 19:08:52 2013 +0100
* doc/xml/manual/status_cxx2011.xml: Fix markup error.
diff --git a/libstdc++-v3/doc/xml/manual/status_cxx2011.xml b/libstdc++-v3/doc/xml/manual/status_cxx2011.xml
index d8caf0f..c0780de 100644
--- a/libstdc++-v3/doc/xml/manual/status_cxx2011.xml
+++ b/libstdc++-v3/doc/xml/manual/status_cxx2011.xml
< at >< at > -2613,7 +2613,7 < at >< at > particular release.
<entry>D.11</entry>
<entry>Violating exception-specifications</entry>
<entry/>
- </entry>
+ <entry/>
</row>
</tbody>
</pre>Jonathan Wakely2013-05-18T18:10:02[patch] implement std::exchange
http://comments.gmane.org/gmane.comp.gcc.patches/286076
<pre> * include/std/utility (exchange): Define.
* testsuite/20_util/exchange/1.cc: New.
Tested x86_64-linux, committed to trunk.
commit f368932e633134e5fb50a1e7d6ffcf6aa4b79b0d
Author: Jonathan Wakely <jwakely.gcc< at >gmail.com>
Date: Sat May 18 16:27:13 2013 +0100
* include/std/utility (exchange): Define.
* testsuite/20_util/exchange/1.cc: New.
diff --git a/libstdc++-v3/include/std/utility b/libstdc++-v3/include/std/utility
index 8142ea4..ee8c6b1 100644
--- a/libstdc++-v3/include/std/utility
+++ b/libstdc++-v3/include/std/utility
< at >< at > -152,6 +152,18 < at >< at > _GLIBCXX_BEGIN_NAMESPACE_VERSION
get(const std::pair<_Tp1, _Tp2>& __in) noexcept
{ return __pair_get<_Int>::__const_get(__in); }
+#if __cplusplus > 201103L
+ /// Assign < at >p __new_val to < at >p __obj and return its previous value.
+ template <class _Tp, class _Up = _Tp>
+ inline _Tp
+ exchange(_Tp& __obj, _Up&& __new_val)
+ {
+ _Tp __old_val = std::move(__obj);
+ __obj = std::forward<_Up>(__new_val);
+ return __old_val;
+ }
+#endif
+
_GLIBCXX_END_NAMESPACE_VERSION
} // namespace
diff --git a/libstdc++-v3/testsuite/20_util/exchange/1.cc b/libstdc++-v3/testsuite/20_util/exchange/1.cc
new file mode 100644
index 0000000..d16d9e9
--- /dev/null
+++ b/libstdc++-v3/testsuite/20_util/exchange/1.cc
< at >< at > -0,0 +1,103 < at >< at >
+// { dg-options "-std=gnu++1y" }
+
+// Copyright (C) 2013 Free Software Foundation, Inc.
+//
+// This file is part of the GNU ISO C++ Library. This library is free
+// software; you can redistribute it and/or modify it under the
+// terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 3, or (at your option)
+// any later version.
+
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+
+// You should have received a copy of the GNU General Public License along
+// with this library; see the file COPYING3. If not see
+// <http://www.gnu.org/licenses/>.
+
+// 20.2.3 exchange [utility.exchange]
+
+#include <utility>
+#include <type_traits>
+#include <testsuite_hooks.h>
+
+void
+test01()
+{
+ const unsigned val = 4;
+ int i = 1;
+ auto prev = std::exchange(i, val);
+ static_assert( std::is_same<decltype(prev), int>::value, "return type" );
+ VERIFY( i == 4 );
+ VERIFY( prev == 1 );
+ prev = std::exchange(i, 3);
+ VERIFY( i == 3 );
+ VERIFY( prev == 4 );
+}
+
+// Default construction from empty braces
+void
+test02()
+{
+ bool test __attribute__((unused)) = true;
+
+ struct DefaultConstructible
+ {
+ DefaultConstructible(int i = 0) : value(i) { }
+ int value;
+ };
+
+ DefaultConstructible x = 1;
+ auto old = std::exchange(x, {});
+ VERIFY( x.value == 0 );
+ VERIFY( old.value == 1 );
+}
+
+// Deduce type of overloaded function
+void
+test03()
+{
+ bool test __attribute__((unused)) = true;
+
+ int (*fp)(int);
+ int f(int);
+ double f(double);
+ std::exchange(fp, &f);
+ VERIFY( fp != nullptr );
+}
+
+void test04()
+{
+ struct From { };
+ struct To {
+ int value = 0;
+ To() = default;
+ To(const To&) = default;
+ To(const From&) = delete;
+ To& operator=(const From&) { value = 1; }
+ To& operator=(From&&) { value = 2; }
+ };
+
+ To t;
+ From f;
+
+ auto prev = std::exchange(t, f);
+ VERIFY( t.value == 1 );
+ VERIFY( prev.value == 0 );
+
+ prev = std::exchange(t, From{});
+ VERIFY( t.value == 2 );
+ VERIFY( prev.value == 1 );
+}
+
+int
+main()
+{
+ test01();
+ test02();
+ test03();
+ test04();
+ return 0;
+}
</pre>Jonathan Wakely2013-05-18T16:22:47C++ copy elision and alignment
http://comments.gmane.org/gmane.comp.gcc.patches/286075
<pre>Hello,
this patch passes bootstrap+testsuite on x86_64-linux-gnu. As explained in
the PR, it seems that the check for alignment is in the wrong direction
(tree-nrv.c and ada have the reverse one).
2013-05-18 Marc Glisse <marc.glisse< at >inria.fr>
PR c++/57175
gcc/cp/
* typeck.c (check_return_expr): Reverse the alignment comparison.
gcc/testsuite/
* g++.dg/pr57175.C: New testcase.
</pre>Marc Glisse2013-05-18T16:17:59[patch] Implement std::make_unique
http://comments.gmane.org/gmane.comp.gcc.patches/286071
<pre> * include/bits/unique_ptr.h (make_unique): Define.
* testsuite/20_util/unique_ptr/creation/single.cc: New.
* testsuite/20_util/unique_ptr/creation/array.cc: New.
* testsuite/20_util/unique_ptr/creation/array_neg.cc: New.
Tested x86_64-linux, committed to trunk.
This is safe for 4.8.2 so I'll commit it there once the branch reopens.
It might even be nice to provide this for C++11, maybe when using
-std=gnu++11 not -std=c++11, or by putting the declarations in
namespace std::__cxx14, which is inline in C++14 but not in C++11
mode.
commit d0ee6a7b7520d0386c4dbc4189f86ade9268462f
Author: Jonathan Wakely <jwakely.gcc< at >gmail.com>
Date: Sat May 18 15:23:07 2013 +0100
* include/bits/unique_ptr.h (make_unique): Define.
* testsuite/20_util/unique_ptr/creation/single.cc: New.
* testsuite/20_util/unique_ptr/creation/array.cc: New.
* testsuite/20_util/unique_ptr/creation/array_neg.cc: New.
diff --git a/libstdc++-v3/include/bits/unique_ptr.h b/libstdc++-v3/include/bits/unique_ptr.h
index 66d73b2..e98b85f 100644
--- a/libstdc++-v3/include/bits/unique_ptr.h
+++ b/libstdc++-v3/include/bits/unique_ptr.h
< at >< at > -607,6 +607,37 < at >< at > _GLIBCXX_BEGIN_NAMESPACE_VERSION
}
};
+#if __cplusplus > 201103L
+ template<typename _Tp>
+ struct _MakeUniq
+ { typedef unique_ptr<_Tp> __single_object; };
+
+ template<typename _Tp>
+ struct _MakeUniq<_Tp[]>
+ { typedef unique_ptr<_Tp[]> __array; };
+
+ template<typename _Tp, size_t _Bound>
+ struct _MakeUniq<_Tp[_Bound]>
+ { struct __invalid_type { }; };
+
+ /// std::make_unique for single objects
+ template<typename _Tp, typename... _Args>
+ typename _MakeUniq<_Tp>::__single_object
+ make_unique(_Args&&... __args)
+ { return unique_ptr<_Tp>(new _Tp(std::forward<_Args>(__args)...)); }
+
+ /// std::make_unique for arrays of unknown bound
+ template<typename _Tp>
+ typename _MakeUniq<_Tp>::__array
+ make_unique(size_t __num)
+ { return unique_ptr<_Tp>(new typename remove_extent<_Tp>::type[__num]()); }
+
+ /// Disable std::make_unique for arrays of known bound
+ template<typename _Tp, typename... _Args>
+ typename _MakeUniq<_Tp>::__invalid_type
+ make_unique(_Args&&...) = delete;
+#endif
+
// < at >} group pointer_abstractions
_GLIBCXX_END_NAMESPACE_VERSION
diff --git a/libstdc++-v3/testsuite/20_util/unique_ptr/creation/array.cc b/libstdc++-v3/testsuite/20_util/unique_ptr/creation/array.cc
new file mode 100644
index 0000000..8943310
--- /dev/null
+++ b/libstdc++-v3/testsuite/20_util/unique_ptr/creation/array.cc
< at >< at > -0,0 +1,46 < at >< at >
+// { dg-options "-std=gnu++1y" }
+
+// Copyright (C) 2013 Free Software Foundation, Inc.
+//
+// This file is part of the GNU ISO C++ Library. This library is free
+// software; you can redistribute it and/or modify it under the
+// terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 3, or (at your option)
+// any later version.
+
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+
+// You should have received a copy of the GNU General Public License along
+// with this library; see the file COPYING3. If not see
+// <http://www.gnu.org/licenses/>.
+
+// 20.9.1.4 unique_ptr creation [unique.ptr.create]
+
+#include <memory>
+#include <testsuite_hooks.h>
+
+struct A
+{
+ A() : b(true) { }
+ A(int) : b(false) { }
+ bool b;
+};
+
+void
+test01()
+{
+ bool test __attribute__((unused)) = true;
+
+ std::unique_ptr<A[]> a = std::make_unique<A[]>(3);
+ VERIFY( a != nullptr );
+ VERIFY( a[0].b && a[1].b && a[2].b );
+}
+
+int
+main()
+{
+ test01();
+}
diff --git a/libstdc++-v3/testsuite/20_util/unique_ptr/creation/array_neg.cc b/libstdc++-v3/testsuite/20_util/unique_ptr/creation/array_neg.cc
new file mode 100644
index 0000000..1e55622
--- /dev/null
+++ b/libstdc++-v3/testsuite/20_util/unique_ptr/creation/array_neg.cc
< at >< at > -0,0 +1,34 < at >< at >
+// { dg-options "-std=gnu++1y" }
+// { dg-do compile }
+
+// Copyright (C) 2013 Free Software Foundation, Inc.
+//
+// This file is part of the GNU ISO C++ Library. This library is free
+// software; you can redistribute it and/or modify it under the
+// terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 3, or (at your option)
+// any later version.
+
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+
+// You should have received a copy of the GNU General Public License along
+// with this library; see the file COPYING3. If not see
+// <http://www.gnu.org/licenses/>.
+
+// 20.9.1.4 unique_ptr creation [unique.ptr.create]
+
+#include <memory>
+#include <testsuite_hooks.h>
+
+struct A { };
+
+auto p1 = std::make_unique<A[]>(); // { dg-error "no matching function" }
+auto p2 = std::make_unique<A[]>(1, 2); // { dg-error "no matching function" }
+auto p3 = std::make_unique<A[1]>(); // { dg-error "deleted" }
+auto p4 = std::make_unique<A[1]>(1); // { dg-error "deleted" }
+
+// { dg-prune-output "declared here" }
+// { dg-prune-output "no type named" }
diff --git a/libstdc++-v3/testsuite/20_util/unique_ptr/creation/single.cc b/libstdc++-v3/testsuite/20_util/unique_ptr/creation/single.cc
new file mode 100644
index 0000000..689e849
--- /dev/null
+++ b/libstdc++-v3/testsuite/20_util/unique_ptr/creation/single.cc
< at >< at > -0,0 +1,53 < at >< at >
+// { dg-options "-std=gnu++1y" }
+
+// Copyright (C) 2013 Free Software Foundation, Inc.
+//
+// This file is part of the GNU ISO C++ Library. This library is free
+// software; you can redistribute it and/or modify it under the
+// terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 3, or (at your option)
+// any later version.
+
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+
+// You should have received a copy of the GNU General Public License along
+// with this library; see the file COPYING3. If not see
+// <http://www.gnu.org/licenses/>.
+
+// 20.9.1.4 unique_ptr creation [unique.ptr.create]
+
+#include <memory>
+#include <testsuite_hooks.h>
+
+struct A
+{
+ A() : b(false) { }
+ A(int, double&, char&&, void*) : b(true) { }
+ bool b;
+};
+
+void
+test01()
+{
+ bool test __attribute__((unused)) = true;
+
+ int i = 0;
+ double d = 0;
+ char c = 0;
+ std::unique_ptr<A> a = std::make_unique<A>(i, d, std::move(c), nullptr);
+ VERIFY( a != nullptr );
+ VERIFY( a->b );
+
+ a = std::make_unique<A>();
+ VERIFY( a != nullptr );
+ VERIFY( !a->b );
+}
+
+int
+main()
+{
+ test01();
+}
</pre>Jonathan Wakely2013-05-18T15:11:29[Patch] Extend script ./contrib/download_prerequisites usage for isl and cloog
http://comments.gmane.org/gmane.comp.gcc.patches/286067
<pre>Hi all,
Using current trunk repository, it is now able to build
compiler with in-tree isl and cloog.
This patch is to extend ./contrib/download_prerequisites
usage to download isl and cloog conditionally in case
people would like to build gcc with graphite loop optimizations.
OK for the trunk?
contrib/ChangeLog
2013-05-18 Chung-Ju Wu <jasonwucj< at >gmail.com>
* download_prerequisites: Download isl and cloog conditionally.
Index: contrib/download_prerequisites
===================================================================
--- contrib/download_prerequisites (revision 199006)
+++ contrib/download_prerequisites (working copy)
< at >< at > -19,6 +19,12 < at >< at >
# You should have received a copy of the GNU General Public License
# along with this program. If not, see http://www.gnu.org/licenses/.
+# If you want to build GCC with the Graphite loop optimizations,
+# set GRAPHITE_LOOP_OPT=yes to download optional prerequisties
+# ISL Library and CLooG.
+GRAPHITE_LOOP_OPT=no
+
+# Necessary to build GCC.
MPFR=mpfr-2.4.2
GMP=gmp-4.3.2
MPC=mpc-0.8.1
< at >< at > -36,3 +42,19 < at >< at >
ln -sf $MPC mpc || exit 1
rm $MPFR.tar.bz2 $GMP.tar.bz2 $MPC.tar.gz || exit 1
+
+# Necessary to build GCC with the Graphite loop optimizations.
+if [ "$GRAPHITE_LOOP_OPT" == "yes" ] ; then
+ ISL=isl-0.11.1
+ CLOOG=cloog-0.18.0
+
+ wget ftp://gcc.gnu.org/pub/gcc/infrastructure/$ISL.tar.bz2 || exit 1
+ tar xjf $ISL.tar.bz2 || exit 1
+ ln -sf $ISL isl || exit 1
+
+ wget ftp://gcc.gnu.org/pub/gcc/infrastructure/$CLOOG.tar.gz || exit 1
+ tar xzf $CLOOG.tar.gz || exit 1
+ ln -sf $CLOOG cloog || exit 1
+
+ rm $ISL.tar.bz2 $CLOOG.tar.gz || exit 1
+fi
Best regards,
jasonwucj
</pre>Chung-Ju Wu2013-05-18T02:37:45[C++ Patch] PR 10207
http://comments.gmane.org/gmane.comp.gcc.patches/286065
<pre>Hi,
in this even older ;) and related issue, we reject empty initializer
lists in compound-literals. The fix seems simple: just use
cp_parser_braced_list instead of cp_parser_initializer_list, which
allows for the special case of empty list. Tested x86_64-linux.
There is a nit which I don't want to hide: cp_parser_initializer_list +
build_constructor does a little more than cp_parser_braced_list: in
build_constructor there is a loop setting TREE_SIDE_EFFECTS and
TREE_CONSTANT to the right value for the CONSTRUCTOR overall, which
doesn't exist in cp_parser_braced_list. In case it matters - I don't
think it does, and we have testcases with side effects in the testsuite
- we can't simply add it to cp_parser_braced_list, because its many
existing uses are perfectly fine without. A little more code would be
needed, not a big issue.
Thanks,
Paolo.
///////////////////////
/cp
2013-05-18 Paolo Carlini <paolo.carlini< at >oracle.com>
PR c++/10207
* parser.c (cp_parser_postfix_expression): Use cp_parser_braced_list
instead of cp_parser_initializer_list for compound-literals.
/testsuite
2013-05-18 Paolo Carlini <paolo.carlini< at >oracle.com>
PR c++/10207
* g++.dg/ext/complit13.C: New.
Index: cp/parser.c
===================================================================
--- cp/parser.c(revision 199043)
+++ cp/parser.c(working copy)
< at >< at > -5719,7 +5719,7 < at >< at > cp_parser_postfix_expression (cp_parser *parser, b
if (cp_parser_allow_gnu_extensions_p (parser)
&& cp_lexer_next_token_is (parser->lexer, CPP_OPEN_PAREN))
{
- vec<constructor_elt, va_gc> *initializer_list = NULL;
+ tree initializer = NULL_TREE;
bool saved_in_type_id_in_expr_p;
cp_parser_parse_tentatively (parser);
< at >< at > -5732,21 +5732,19 < at >< at > cp_parser_postfix_expression (cp_parser *parser, b
parser->in_type_id_in_expr_p = saved_in_type_id_in_expr_p;
/* Look for the `)'. */
cp_parser_require (parser, CPP_CLOSE_PAREN, RT_CLOSE_PAREN);
- /* Look for the `{'. */
- cp_parser_require (parser, CPP_OPEN_BRACE, RT_OPEN_BRACE);
/* If things aren't going well, there's no need to
keep going. */
if (!cp_parser_error_occurred (parser))
{
-bool non_constant_p;
-/* Parse the initializer-list. */
-initializer_list
- = cp_parser_initializer_list (parser, &non_constant_p);
-/* Allow a trailing `,'. */
-if (cp_lexer_next_token_is (parser->lexer, CPP_COMMA))
- cp_lexer_consume_token (parser->lexer);
-/* Look for the final `}'. */
-cp_parser_require (parser, CPP_CLOSE_BRACE, RT_CLOSE_BRACE);
+if (cp_lexer_next_token_is (parser->lexer, CPP_OPEN_BRACE))
+ {
+ bool non_constant_p;
+ /* Parse the brace-enclosed initializer list. */
+ initializer = cp_parser_braced_list (parser,
+ &non_constant_p);
+ }
+else
+ cp_parser_simulate_error (parser);
}
/* If that worked, we're definitely looking at a
compound-literal expression. */
< at >< at > -5754,7 +5752,8 < at >< at > cp_parser_postfix_expression (cp_parser *parser, b
{
/* Warn the user that a compound literal is not
allowed in standard C++. */
-pedwarn (input_location, OPT_Wpedantic, "ISO C++ forbids compound-literals");
+pedwarn (input_location, OPT_Wpedantic,
+ "ISO C++ forbids compound-literals");
/* For simplicity, we disallow compound literals in
constant-expressions. We could
allow compound literals of integer type, whose
< at >< at > -5772,10 +5771,8 < at >< at > cp_parser_postfix_expression (cp_parser *parser, b
}
/* Form the representation of the compound-literal. */
postfix_expression
- = (finish_compound_literal
- (type, build_constructor (init_list_type_node,
- initializer_list),
- tf_warning_or_error));
+ = (finish_compound_literal (type, initializer,
+ tf_warning_or_error));
break;
}
}
Index: testsuite/g++.dg/ext/complit13.C
===================================================================
--- testsuite/g++.dg/ext/complit13.C(revision 0)
+++ testsuite/g++.dg/ext/complit13.C(working copy)
< at >< at > -0,0 +1,11 < at >< at >
+// PR c++/10207
+// { dg-options "" }
+
+typedef struct { } EmptyStruct;
+typedef struct { EmptyStruct Empty; } DemoStruct;
+
+void Func()
+{
+ DemoStruct Demo;
+ Demo.Empty = (EmptyStruct) {};
+}
</pre>Paolo Carlini2013-05-18T02:14:12Fix infinite loop in lto-partition.c
http://comments.gmane.org/gmane.comp.gcc.patches/286060
<pre>Hi,
privatize_symbol_name skips privatizing of symbols where we know for some reason
that it is needed. Loop in rename_statics however expect privatize_symbol_name
to always rename the var and it can get into an infinite loop.
Bootstrapped/regtested x86_64-linux, comitted.
Honza
* lto-partition.c (privatize_symbol_name): Return true when
privatizing happened.
(rename_statics): Do not go into infinite loop when privatizing
is not needed.
Index: lto-partition.c
===================================================================
--- lto-partition.c(revision 198936)
+++ lto-partition.c(working copy)
< at >< at > -766,7 +766,7 < at >< at > lto_balanced_map (void)
with symbols defined out of the LTO world.
*/
-static void
+static bool
privatize_symbol_name (symtab_node node)
{
tree decl = node->symbol.decl;
< at >< at > -781,7 +781,7 < at >< at > privatize_symbol_name (symtab_node node)
fprintf (cgraph_dump_file,
"Not privatizing symbol name: %s. It privatized already.\n",
name);
- return;
+ return false;
}
/* Avoid mangling of already mangled clones.
??? should have a flag whether a symbol has a 'private' name already,
< at >< at > -793,7 +793,7 < at >< at > privatize_symbol_name (symtab_node node)
fprintf (cgraph_dump_file,
"Not privatizing symbol name: %s. Has unique name.\n",
name);
- return;
+ return false;
}
change_decl_assembler_name (decl, clone_function_name (decl, "lto_priv"));
if (node->symbol.lto_file_data)
< at >< at > -804,6 +804,7 < at >< at > privatize_symbol_name (symtab_node node)
fprintf (cgraph_dump_file,
"Privatizing symbol name: %s -> %s\n",
name, IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)));
+ return true;
}
/* Promote variable VNODE to be static. */
< at >< at > -906,11 +907,12 < at >< at > rename_statics (lto_symtab_encoder_t enc
&& (!encoder
|| lto_symtab_encoder_lookup (encoder, s) != LCC_NOT_FOUND))
{
- privatize_symbol_name (s);
-/* Re-start from beggining since we do not know how many symbols changed a name. */
-s = symtab_node_for_asm (name);
+ if (privatize_symbol_name (s))
+ /* Re-start from beggining since we do not know how many symbols changed a name. */
+ s = symtab_node_for_asm (name);
+ else s = s->symbol.next_sharing_asm_name;
}
- else s = s->symbol.next_sharing_asm_name;
+ else s = s->symbol.next_sharing_asm_name;
}
/* Find out all static decls that need to be promoted to global because
</pre>Jan Hubicka2013-05-17T22:22:16[PATCH, i386]: Also pass mmx, 3dnow and sseX options with -march=native
http://comments.gmane.org/gmane.comp.gcc.patches/286053
<pre>Hello!
For some reason we didn't pass mmx, 3dnow and sseX options to cc1 with
-march=native. Passing these options will help older processors that
doesn't get detected through architecture recognition functionality to
get all their ISAs enabled.
2013-05-17 Uros Bizjak <ubizjak< at >gmail.com>
* config/i386/driver-i386.c (host_detect_local_cpu): Pass mmx, 3dnow,
sse, sse2, sse3, ssse3 and sse4a flags to options.
Tested on x86_64-pc-linux-gnu {,-m32} and committed to mainline.
Uros.
Index: config/i386/driver-i386.c
===================================================================
--- config/i386/driver-i386.c(revision 198989)
+++ config/i386/driver-i386.c(working copy)
< at >< at > -786,10 +786,17 < at >< at > const char *host_detect_local_cpu (int argc, const
if (arch)
{
+ const char *mmx = has_mmx ? " -mmmx" : " -mno-mmx";
+ const char *mmx3dnow = has_3dnow ? " -m3dnow" : " -mno-3dnow";
+ const char *sse = has_sse ? " -msse" : " -mno-sse";
+ const char *sse2 = has_sse2 ? " -msse2" : " -mno-sse2";
+ const char *sse3 = has_sse3 ? " -msse3" : " -mno-sse3";
+ const char *ssse3 = has_ssse3 ? " -mssse3" : " -mno-ssse3";
+ const char *sse4a = has_sse4a ? " -msse4a" : " -mno-sse4a";
const char *cx16 = has_cmpxchg16b ? " -mcx16" : " -mno-cx16";
const char *sahf = has_lahf_lm ? " -msahf" : " -mno-sahf";
const char *movbe = has_movbe ? " -mmovbe" : " -mno-movbe";
- const char *ase = has_aes ? " -maes" : " -mno-aes";
+ const char *aes = has_aes ? " -maes" : " -mno-aes";
const char *pclmul = has_pclmul ? " -mpclmul" : " -mno-pclmul";
const char *popcnt = has_popcnt ? " -mpopcnt" : " -mno-popcnt";
const char *abm = has_abm ? " -mabm" : " -mno-abm";
< at >< at > -817,7 +824,8 < at >< at > const char *host_detect_local_cpu (int argc, const
const char *xsave = has_xsave ? " -mxsave" : " -mno-xsave";
const char *xsaveopt = has_xsaveopt ? " -mxsaveopt" : " -mno-xsaveopt";
- options = concat (options, cx16, sahf, movbe, ase, pclmul,
+ options = concat (options, mmx, mmx3dnow, sse, sse2, sse3, ssse3,
+sse4a, cx16, sahf, movbe, aes, pclmul,
popcnt, abm, lwp, fma, fma4, xop, bmi, bmi2,
tbm, avx, avx2, sse4_2, sse4_1, lzcnt, rtm,
hle, rdrnd, f16c, fsgsbase, rdseed, prfchw, adx,
</pre>Uros Bizjak2013-05-17T20:13:50[patch] Cleanup the CFG after pro_and_epilogue pass
http://comments.gmane.org/gmane.comp.gcc.patches/286050
<pre>Hello,
Trying to dump the CFG as a graph fails after the pro_and_epilogue
pass because it leaves unreachable basic blocks. This patch fixes that
issue.
Will commit sometime next week if no-one objects.
Ciao!
Steven
* function.c (rest_of_handle_thread_prologue_and_epilogue):
Cleanup the CFG after thread_prologue_and_epilogue_insns.
Index: function.c
===================================================================
--- function.c (revision 199028)
+++ function.c (working copy)
< at >< at > -6976,6 +6976,9 < at >< at > rest_of_handle_thread_prologue_and_epilo
scheduling to operate in the epilogue. */
thread_prologue_and_epilogue_insns ();
+ /* The prologue and epilogue may have made some blocks unreachable. */
+ cleanup_cfg (0);
+
/* The stack usage info is finalized during prologue expansion. */
if (flag_stack_usage_info)
output_stack_usage ();
</pre>Steven Bosscher2013-05-17T19:49:55[PATCH, AArch64] Allow insv_imm to handle bigger immediates via masking to 16-bits
http://comments.gmane.org/gmane.comp.gcc.patches/286046
<pre>The MOVK instruction is currently not used when operand 2 is
more than 16 bits, which leads to sub-optimal code.
This patch improves those situations by removing the check and
instead masking down to 16 bits within the new "X" format specifier
I added recently.
OK for trunk?
Cheers,
Ian
2013-05-17 Ian Bolton <ian.bolton< at >arm.com>
* config/aarch64/aarch64.c (aarch64_print_operand): Change the X
format
specifier to only display bottom 16 bits.
* config/aarch64/aarch64.md (insv_imm<mode>): Allow any-sized
immediate
to match for operand 2, since it will be masked.diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index b57416c..1bdfd85 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
< at >< at > -3424,13 +3424,13 < at >< at > aarch64_print_operand (FILE *f, rtx x, char code)
break;
case 'X':
- /* Print integer constant in hex. */
+ /* Print bottom 16 bits of integer constant in hex. */
if (GET_CODE (x) != CONST_INT)
{
output_operand_lossage ("invalid operand for '%%%c'", code);
return;
}
- asm_fprintf (f, "0x%wx", UINTVAL (x));
+ asm_fprintf (f, "0x%wx", UINTVAL (x) & 0xffff);
break;
case 'w':
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index b27bcda..403d717 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
< at >< at > -858,9 +858,8 < at >< at >
(const_int 16)
(match_operand:GPI 1 "const_int_operand" "n"))
(match_operand:GPI 2 "const_int_operand" "n"))]
- "INTVAL (operands[1]) < GET_MODE_BITSIZE (<MODE>mode)
- && INTVAL (operands[1]) % 16 == 0
- && UINTVAL (operands[2]) <= 0xffff"
+ "UINTVAL (operands[1]) < GET_MODE_BITSIZE (<MODE>mode)
+ && UINTVAL (operands[1]) % 16 == 0"
"movk\\t%<w>0, %X2, lsl %1"
[(set_attr "v8type" "movk")
(set_attr "mode" "<MODE>")]
</pre>Ian Bolton2013-05-17T18:20:14[wwwdocs] gcc-4.8/changes.html: mention IRA and transactional memory
http://comments.gmane.org/gmane.comp.gcc.patches/286045
<pre>Errr, how did we miss this? Ok, I'm partly to blame for the lack of
transactional memory in changes.html, but something as big as getting
rid of reload?!
Would it be preferable to mention IRA in the target specific x86 section
instead? I figured it was an important enough change to warrant
front-page coverage.
Is this OK?
Index: htdocs/gcc-4.8/changes.html
===================================================================
RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-4.8/changes.html,v
retrieving revision 1.116
diff -u -r1.116 changes.html
--- htdocs/gcc-4.8/changes.html24 Apr 2013 15:14:26 -00001.116
+++ htdocs/gcc-4.8/changes.html17 May 2013 17:49:19 -0000
< at >< at > -143,6 +143,11 < at >< at >
<code>-fsanitize=thread</code>. Instructions will be instrumented to
detect data races. The ThreadSanitizer is available on x86-64
GNU/Linux.</li>
+ <li>A new local register allocator has been implemented, which
+ replaces the 26 year old reload pass and improves generated code
+ quality on ia32 and x86-64 targets.</li>
+ <li>Support for transactional memory has been implemented on
+ selected architectures.</li>
</ul>
</pre>Aldy Hernandez2013-05-17T17:53:09Add myself to MAINTAINERS as Write After Approval
http://comments.gmane.org/gmane.comp.gcc.patches/286044
<pre>Adding myself to the MAINTAINERS in the "Write After Approval" category
</pre>David Malcolm2013-05-17T15:59:11[PATCH] [tree-optimization/57124] Updated fix for 254.gap problems
http://comments.gmane.org/gmane.comp.gcc.patches/286043
<pre>As I believe I pointed out in a follow-up message, 254.gap is depending
on signed overflow semantics.
This patch avoids eliminating a cast feeding a conditional when the
SSA_NAME's range has overflowed unless -fstrict-overflow is in effect.
Thus 254.gap should be building with -fno-strict-overflow.
This patch also introduces a warning when the optimization is applied
and the ranges have overflowed.
Bootstrapped and regression tested on x86-unknown-linux-gnu.
OK for the trunk?
commit 62bbaa8de0e8d929eb3c63331b47950e9b09d801
Author: Jeff Law <law< at >redhat.com>
Date: Wed May 1 12:33:20 2013 -0600
PR tree-optimization/57124
* tree-vrp.c (simplify_cond_using_ranges): Only simplify a
conversion feeding a condition if the range has an overflow
if -fstrict-overflow. Add warnings for when we do make the
transformation.
PR tree-optimization/57124
* gcc.c-torture/execute/pr57124.c: New test.
* gcc.c-torture/execute/pr57124.x: Set -fno-strict-overflow.
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 8e92c44..9320f21 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
< at >< at > -1,3 +1,11 < at >< at >
+2013-05-17 Jeff Law <law< at >redhat.com>
+
+PR tree-optimization/57124
+* tree-vrp.c (simplify_cond_using_ranges): Only simplify a
+conversion feeding a condition if the range has an overflow
+if -fstrict-overflow. Add warnings for when we do make the
+transformation.
+
2013-05-16 Rainer Orth <ro< at >CeBiTec.Uni-Bielefeld.DE>
* reorg.c (link_cc0_insns): Wrap in #ifdef HAVE_cc0.
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 879b9bc..482151c 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
< at >< at > -1,3 +1,9 < at >< at >
+2013-05-17 Jeff Law <law< at >redhat.com>
+
+PR tree-optimization/57124
+* gcc.c-torture/execute/pr57124.c: New test.
+* gcc.c-torture/execute/pr57124.x: Set -fno-strict-overflow.
+
2013-05-16 Greta Yorsh <Greta.Yorsh< at >arm.com>
* gcc.target/arm/unaligned-memcpy-2.c: Adjust expected output.
diff --git a/gcc/testsuite/gcc.c-torture/execute/pr57124.c b/gcc/testsuite/gcc.c-torture/execute/pr57124.c
new file mode 100644
index 0000000..835d249
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/execute/pr57124.c
< at >< at > -0,0 +1,27 < at >< at >
+__attribute__ ((noinline))
+foo(short unsigned int *p1, short unsigned int *p2)
+{
+ short unsigned int x1, x4;
+ int x2, x3, x5, x6;
+ unsigned int x7;
+
+ x1 = *p1;
+ x2 = (int) x1;
+ x3 = x2 * 65536;
+ x4 = *p2;
+ x5 = (int) x4;
+ x6 = x3 + x4;
+ x7 = (unsigned int) x6;
+ if (x7 <= 268435455U)
+ abort ();
+ exit (0);
+}
+
+main()
+{
+ short unsigned int x, y;
+ x = -5;
+ y = -10;
+ foo (&x, &y);
+}
+
diff --git a/gcc/testsuite/gcc.c-torture/execute/pr57124.x b/gcc/testsuite/gcc.c-torture/execute/pr57124.x
new file mode 100644
index 0000000..d8cacbe
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/execute/pr57124.x
< at >< at > -0,0 +1,2 < at >< at >
+set additional_flags "-fno-strict-overflow"
+return 0
diff --git a/gcc/tree-vrp.c b/gcc/tree-vrp.c
index b5de683..b3eccf0 100644
--- a/gcc/tree-vrp.c
+++ b/gcc/tree-vrp.c
< at >< at > -8669,8 +8669,32 < at >< at > simplify_cond_using_ranges (gimple stmt)
&& range_fits_type_p (vr,
TYPE_PRECISION (TREE_TYPE (op0)),
TYPE_UNSIGNED (TREE_TYPE (op0)))
- && int_fits_type_p (op1, TREE_TYPE (innerop)))
+ && int_fits_type_p (op1, TREE_TYPE (innerop))
+ /* The range must not have overflowed, or if it did overflow
+ we must not be wrapping/trapping overflow and optimizing
+ with strict overflow semantics. */
+ && ((!is_negative_overflow_infinity (vr->min)
+ && !is_positive_overflow_infinity (vr->max))
+ || (!flag_wrapv && !flag_trapv && flag_strict_overflow)))
{
+ /* If the range overflowed and the user has asked for warnings
+ when strict overflow semantics were used to optimize code,
+ issue an appropriate warning. */
+ if ((is_negative_overflow_infinity (vr->min)
+ || is_positive_overflow_infinity (vr->max))
+ && issue_strict_overflow_warning (WARN_STRICT_OVERFLOW_CONDITIONAL))
+{
+ location_t location;
+
+ if (!gimple_has_location (stmt))
+ location = input_location;
+ else
+ location = gimple_location (stmt);
+ warning_at (location, OPT_Wstrict_overflow,
+ "assuming signed overflow does not occur when "
+ "simplifying conditional.");
+}
+
tree newconst = fold_convert (TREE_TYPE (innerop), op1);
gimple_cond_set_lhs (stmt, innerop);
gimple_cond_set_rhs (stmt, newconst);
</pre>Jeff Law2013-05-17T15:51:24Fix pr49146 - crash in unwinder
http://comments.gmane.org/gmane.comp.gcc.patches/286040
<pre>The rationale is captured in the comment in the first hunk.
Committed.
r~
PR target/49146
* unwind-dw2.c (UNWIND_COLUMN_IN_RANGE): New macro.
(execute_cfa_program): Use it when storing to fs->regs.
diff --git a/libgcc/unwind-dw2.c b/libgcc/unwind-dw2.c
index 80de5ab..041f9d5 100644
--- a/libgcc/unwind-dw2.c
+++ b/libgcc/unwind-dw2.c
< at >< at > -59,6 +59,35 < at >< at >
#define DWARF_REG_TO_UNWIND_COLUMN(REGNO) (REGNO)
#endif
+/* ??? For the public function interfaces, we tend to gcc_assert that the
+ column numbers are in range. For the dwarf2 unwind info this does happen,
+ although so far in a case that doesn't actually matter.
+
+ See PR49146, in which a call from x86_64 ms abi to x86_64 unix abi stores
+ the call-saved xmm registers and annotates them. We havn't bothered
+ providing support for the xmm registers for the x86_64 port primarily
+ because the 64-bit windows targets don't use dwarf2 unwind, using sjlj or
+ SEH instead. Adding the support for unix targets would generally be a
+ waste. However, some runtime libraries supplied with ICC do contain such
+ an unorthodox transition, as well as the unwind info to match. This loss
+ of register restoration doesn't matter in practice, because the exception
+ is caught in the native unix abi, where all of the xmm registers are
+ call clobbered.
+
+ Ideally, we'd record some bit to notice when we're failing to restore some
+ register recorded in the unwind info, but to do that we need annotation on
+ the unix->ms abi edge, so that we know when the register data may be
+ discarded. And since this edge is also within the ICC library, we're
+ unlikely to be able to get the new annotation.
+
+ Barring a magic solution to restore the ms abi defined 128-bit xmm registers
+ (as distictly opposed to the full runtime width) without causing extra
+ overhead for normal unix abis, the best solution seems to be to simply
+ ignore unwind data for unknown columns. */
+
+#define UNWIND_COLUMN_IN_RANGE(x) \
+ __builtin_expect((x) <= DWARF_FRAME_REGISTERS, 1)
+
#ifdef REG_VALUE_IN_UNWIND_CONTEXT
typedef _Unwind_Word _Unwind_Context_Reg_Val;
< at >< at > -939,14 +968,19 < at >< at > execute_cfa_program (const unsigned char *insn_ptr,
reg = insn & 0x3f;
insn_ptr = read_uleb128 (insn_ptr, &utmp);
offset = (_Unwind_Sword) utmp * fs->data_align;
- fs->regs.reg[DWARF_REG_TO_UNWIND_COLUMN (reg)].how
- = REG_SAVED_OFFSET;
- fs->regs.reg[DWARF_REG_TO_UNWIND_COLUMN (reg)].loc.offset = offset;
+ reg = DWARF_REG_TO_UNWIND_COLUMN (reg);
+ if (UNWIND_COLUMN_IN_RANGE (reg))
+ {
+ fs->regs.reg[reg].how = REG_SAVED_OFFSET;
+ fs->regs.reg[reg].loc.offset = offset;
+ }
}
else if ((insn & 0xc0) == DW_CFA_restore)
{
reg = insn & 0x3f;
- fs->regs.reg[DWARF_REG_TO_UNWIND_COLUMN (reg)].how = REG_UNSAVED;
+ reg = DWARF_REG_TO_UNWIND_COLUMN (reg);
+ if (UNWIND_COLUMN_IN_RANGE (reg))
+ fs->regs.reg[reg].how = REG_UNSAVED;
}
else switch (insn)
{
< at >< at > -977,26 +1011,35 < at >< at > execute_cfa_program (const unsigned char *insn_ptr,
insn_ptr = read_uleb128 (insn_ptr, &reg);
insn_ptr = read_uleb128 (insn_ptr, &utmp);
offset = (_Unwind_Sword) utmp * fs->data_align;
- fs->regs.reg[DWARF_REG_TO_UNWIND_COLUMN (reg)].how
- = REG_SAVED_OFFSET;
- fs->regs.reg[DWARF_REG_TO_UNWIND_COLUMN (reg)].loc.offset = offset;
+ reg = DWARF_REG_TO_UNWIND_COLUMN (reg);
+ if (UNWIND_COLUMN_IN_RANGE (reg))
+ {
+ fs->regs.reg[reg].how = REG_SAVED_OFFSET;
+ fs->regs.reg[reg].loc.offset = offset;
+ }
break;
case DW_CFA_restore_extended:
insn_ptr = read_uleb128 (insn_ptr, &reg);
/* FIXME, this is wrong; the CIE might have said that the
register was saved somewhere. */
- fs->regs.reg[DWARF_REG_TO_UNWIND_COLUMN(reg)].how = REG_UNSAVED;
+ reg = DWARF_REG_TO_UNWIND_COLUMN (reg);
+ if (UNWIND_COLUMN_IN_RANGE (reg))
+ fs->regs.reg[reg].how = REG_UNSAVED;
break;
case DW_CFA_same_value:
insn_ptr = read_uleb128 (insn_ptr, &reg);
- fs->regs.reg[DWARF_REG_TO_UNWIND_COLUMN(reg)].how = REG_UNSAVED;
+ reg = DWARF_REG_TO_UNWIND_COLUMN (reg);
+ if (UNWIND_COLUMN_IN_RANGE (reg))
+ fs->regs.reg[reg].how = REG_UNSAVED;
break;
case DW_CFA_undefined:
insn_ptr = read_uleb128 (insn_ptr, &reg);
- fs->regs.reg[DWARF_REG_TO_UNWIND_COLUMN(reg)].how = REG_UNDEFINED;
+ reg = DWARF_REG_TO_UNWIND_COLUMN (reg);
+ if (UNWIND_COLUMN_IN_RANGE (reg))
+ fs->regs.reg[reg].how = REG_UNDEFINED;
break;
case DW_CFA_nop:
< at >< at > -1007,9 +1050,12 < at >< at > execute_cfa_program (const unsigned char *insn_ptr,
_uleb128_t reg2;
insn_ptr = read_uleb128 (insn_ptr, &reg);
insn_ptr = read_uleb128 (insn_ptr, &reg2);
- fs->regs.reg[DWARF_REG_TO_UNWIND_COLUMN (reg)].how = REG_SAVED_REG;
- fs->regs.reg[DWARF_REG_TO_UNWIND_COLUMN (reg)].loc.reg =
- (_Unwind_Word)reg2;
+ reg = DWARF_REG_TO_UNWIND_COLUMN (reg);
+ if (UNWIND_COLUMN_IN_RANGE (reg))
+ {
+ fs->regs.reg[reg].how = REG_SAVED_REG;
+ fs->regs.reg[reg].loc.reg = (_Unwind_Word)reg2;
+ }
}
break;
< at >< at > -1067,8 +1113,12 < at >< at > execute_cfa_program (const unsigned char *insn_ptr,
case DW_CFA_expression:
insn_ptr = read_uleb128 (insn_ptr, &reg);
- fs->regs.reg[DWARF_REG_TO_UNWIND_COLUMN (reg)].how = REG_SAVED_EXP;
- fs->regs.reg[DWARF_REG_TO_UNWIND_COLUMN (reg)].loc.exp = insn_ptr;
+ reg = DWARF_REG_TO_UNWIND_COLUMN (reg);
+ if (UNWIND_COLUMN_IN_RANGE (reg))
+ {
+ fs->regs.reg[reg].how = REG_SAVED_EXP;
+ fs->regs.reg[reg].loc.exp = insn_ptr;
+ }
insn_ptr = read_uleb128 (insn_ptr, &utmp);
insn_ptr += utmp;
break;
< at >< at > -1078,9 +1128,12 < at >< at > execute_cfa_program (const unsigned char *insn_ptr,
insn_ptr = read_uleb128 (insn_ptr, &reg);
insn_ptr = read_sleb128 (insn_ptr, &stmp);
offset = stmp * fs->data_align;
- fs->regs.reg[DWARF_REG_TO_UNWIND_COLUMN (reg)].how
- = REG_SAVED_OFFSET;
- fs->regs.reg[DWARF_REG_TO_UNWIND_COLUMN (reg)].loc.offset = offset;
+ reg = DWARF_REG_TO_UNWIND_COLUMN (reg);
+ if (UNWIND_COLUMN_IN_RANGE (reg))
+ {
+ fs->regs.reg[reg].how = REG_SAVED_OFFSET;
+ fs->regs.reg[reg].loc.offset = offset;
+ }
break;
case DW_CFA_def_cfa_sf:
< at >< at > -1103,25 +1156,34 < at >< at > execute_cfa_program (const unsigned char *insn_ptr,
insn_ptr = read_uleb128 (insn_ptr, &reg);
insn_ptr = read_uleb128 (insn_ptr, &utmp);
offset = (_Unwind_Sword) utmp * fs->data_align;
- fs->regs.reg[DWARF_REG_TO_UNWIND_COLUMN (reg)].how
- = REG_SAVED_VAL_OFFSET;
- fs->regs.reg[DWARF_REG_TO_UNWIND_COLUMN (reg)].loc.offset = offset;
+ reg = DWARF_REG_TO_UNWIND_COLUMN (reg);
+ if (UNWIND_COLUMN_IN_RANGE (reg))
+ {
+ fs->regs.reg[reg].how = REG_SAVED_VAL_OFFSET;
+ fs->regs.reg[reg].loc.offset = offset;
+ }
break;
case DW_CFA_val_offset_sf:
insn_ptr = read_uleb128 (insn_ptr, &reg);
insn_ptr = read_sleb128 (insn_ptr, &stmp);
offset = stmp * fs->data_align;
- fs->regs.reg[DWARF_REG_TO_UNWIND_COLUMN (reg)].how
- = REG_SAVED_VAL_OFFSET;
- fs->regs.reg[DWARF_REG_TO_UNWIND_COLUMN (reg)].loc.offset = offset;
+ reg = DWARF_REG_TO_UNWIND_COLUMN (reg);
+ if (UNWIND_COLUMN_IN_RANGE (reg))
+ {
+ fs->regs.reg[reg].how = REG_SAVED_VAL_OFFSET;
+ fs->regs.reg[reg].loc.offset = offset;
+ }
break;
case DW_CFA_val_expression:
insn_ptr = read_uleb128 (insn_ptr, &reg);
- fs->regs.reg[DWARF_REG_TO_UNWIND_COLUMN (reg)].how
- = REG_SAVED_VAL_EXP;
- fs->regs.reg[DWARF_REG_TO_UNWIND_COLUMN (reg)].loc.exp = insn_ptr;
+ reg = DWARF_REG_TO_UNWIND_COLUMN (reg);
+ if (UNWIND_COLUMN_IN_RANGE (reg))
+ {
+ fs->regs.reg[reg].how = REG_SAVED_VAL_EXP;
+ fs->regs.reg[reg].loc.exp = insn_ptr;
+ }
insn_ptr = read_uleb128 (insn_ptr, &utmp);
insn_ptr += utmp;
break;
< at >< at > -1147,9 +1209,12 < at >< at > execute_cfa_program (const unsigned char *insn_ptr,
insn_ptr = read_uleb128 (insn_ptr, &reg);
insn_ptr = read_uleb128 (insn_ptr, &utmp);
offset = (_Unwind_Word) utmp * fs->data_align;
- fs->regs.reg[DWARF_REG_TO_UNWIND_COLUMN (reg)].how
- = REG_SAVED_OFFSET;
- fs->regs.reg[DWARF_REG_TO_UNWIND_COLUMN (reg)].loc.offset = -offset;
+ reg = DWARF_REG_TO_UNWIND_COLUMN (reg);
+ if (UNWIND_COLUMN_IN_RANGE (reg))
+ {
+ fs->regs.reg[reg].how = REG_SAVED_OFFSET;
+ fs->regs.reg[reg].loc.offset = -offset;
+ }
break;
default:
</pre>Richard Henderson2013-05-17T15:29:32Search EngineSearch the mailing list at Gmanequery
http://search.gmane.org/?group=$group=gmane.comp.gcc.patches