gmane.comp.bios.coreboot.seabios
http://blog.gmane.org/gmane.comp.bios.coreboot.seabios
hourly
1
1901-01-01T00:00+00:00
Gmane
http://gmane.org/img/gmane-25t.png
http://gmane.org
-
KVM call agenda for 2013-05-28
http://comments.gmane.org/gmane.comp.bios.coreboot.seabios/6255
<pre>Juan is not available now, and Anthony asked for
agenda to be sent early.
So here comes:
Agenda for the meeting Tue, May 28:
- Generating acpi tables
- Switching the call to a bi-weekly schedule
Please, send any topic that you are interested in covering.
Thanks, MST
</pre>
Michael S. Tsirkin
2013-05-23T12:41:32
-
DMI based quirks?
http://comments.gmane.org/gmane.comp.bios.coreboot.seabios/6243
<pre>Hi all.
Would it be possible to add some DMI based quirks? I have a device and
in coreboot I have
some detection code for it:
http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/mainboard/bachmann/ot200/mainboard.c;h=0ea053aad0c9e085bbd8ea36f14210404881edb7;hb=HEAD
Now it takes quite some time to load Grub in PIO mode even the device
could use DMA.
For the linux kernel I have added this patch:
https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=abf8f2b877846573f0e6498883fe43f08be5696d
What would be the best solution in seabios to use PIO for broken devices and DMA
for the others? The biggest problem is that the device supports DMA
but due a missing
resister I breaks in DMA.
thanks
--
Christian Gmeiner, MSc
</pre>
Christian Gmeiner
2013-05-21T09:02:50
-
seabios-1.7.2 stable changes
http://comments.gmane.org/gmane.comp.bios.coreboot.seabios/6242
<pre>Hi Gerd,
I just pulled your git branch at "git://git.kraxel.org/seabios
1.7.2-kraxel" into the seabios 1.7.2-stable branch. (I know my timing
isn't great.)
I did not pull the pvpanic changes as I'm reluctant to put a new
feature and change the acpi tables in a stable release.
If there are no other pressing changes, I'll tag 1.7.2.2.
-Kevin
</pre>
Kevin O'Connor
2013-05-21T01:59:27
-
another iasl update breaks seabios compilation again
http://comments.gmane.org/gmane.comp.bios.coreboot.seabios/6189
<pre>I'm not sure what happened yet, but I noticed that current seabios
does not build with 20130214-32 version of iasl.
Apparently, the listing file (-l) produced now does not contain
any comments from the original source, so tools/acpi_extract.py
produce nothing from these files.
Here's the diff between listing produced by two versions of iasl
for ssdt-pcihp:
----------------
--- out/ssdt-pcihp.lst-201005282013-05-09 17:55:43.872160687 +0400
+++ out/ssdt-pcihp.lst-20130214-322013-05-09 17:57:45.222803783 +0400
< at >< at > -1,84 +1,72 < at >< at >
Intel ACPI Component Architecture
-ASL Optimizing Compiler version 20100528 [Jul 2 2010]
-Copyright (c) 2000 - 2010 Intel Corporation
-Supports ACPI Specification Revision 4.0a
-
-Compilation of "out/ssdt-pcihp.dsl.i" - Thu May 9 17:55:43 2013
-
- 1....
- 2..../* ACPI_EXTRACT_ALL_CODE ssdp_pcihp_aml */
- 3....
- 4....DefinitionBlock ("ssdt-pcihp.aml", "SSDT", 0x01, "BXPC", "BXSSDTPCIHP", 0x1)
-
-00000000....53 53 44 54 58 00 00 00 "SSDTX..."
-00000008....01 77 42 58 50 43 00 00 ".wBXPC.."
-00000010....42 58 53 53 44 54 50 43 "BXSSDTPC"
-00000018....01 00 00 00 49 4E 54 4C "....INTL"
-00000020....28 05 10 20 ............ "(.. "
-
- 5....{
- 6.... External(\_SB.PCI0, DeviceObj)
- 7.... External(\_SB.PCI0.PCEJ, MethodObj)
- 8.... Scope(\_SB.PCI0) {
-
-00000024....10 33 5C 2E 5F 53 42 5F ".3\._SB_"
-0000002C....50 43 49 30 ............ "PCI0"
-
- 9....
- 10..../* ACPI_EXTRACT_DEVICE_START ssdt_pcihp_start */
- 11....
- 12....
- 13..../* ACPI_EXTRACT_DEVICE_END ssdt_pcihp_end */
- 14....
- 15....
- 16..../* ACPI_EXTRACT_DEVICE_STRING ssdt_pcihp_name */
- 17....
- 18.... Device(SAA) {
-
-00000030....5B 82 26 53 41 41 5F ... "[.&SAA_"
-
- 19....
- 20..../* ACPI_EXTRACT_NAME_BYTE_CONST ssdt_pcihp_id */
- 21....
- 22.... Name(_SUN, 0xAA)
-
-00000037....08 5F 53 55 4E 0A AA ... "._SUN.."
-
- 23....
- 24..../* ACPI_EXTRACT_NAME_DWORD_CONST ssdt_pcihp_adr */
- 25....
- 26.... Name(_ADR, 0xAA0000)
-
-0000003E....08 5F 41 44 52 0C 00 00 "._ADR..."
-00000046....AA 00 .................. ".."
-
- 27....
- 28..../* ACPI_EXTRACT_METHOD_STRING ssdt_pcihp_ej0 */
- 29....
- 30.... Method(_EJ0, 1) {
-
-00000048....14 0F 5F 45 4A 30 01 ... ".._EJ0."
-
- 31.... Return (PCEJ(_SUN))
-
-0000004F....A4 ..................... "."
-00000050....50 43 45 4A 5F 53 55 4E "PCEJ_SUN"
- 32.... }
- 33.... }
- 34.... }
- 35....}
- 36....
+ASL Optimizing Compiler version 20130214-32 [Apr 6 2013]
+Copyright (c) 2000 - 2013 Intel Corporation
+
+Compilation of "out/ssdt-pcihp.dsl.i" - Thu May 9 17:57:45 2013
+
+ 4: DefinitionBlock ("ssdt-pcihp.aml", "SSDT", 0x01, "BXPC", "BXSSDTPCIHP", 0x1)
+
+00000000: 53 53 44 54 58 00 00 00 "SSDTX..."
+00000008: 01 8B 42 58 50 43 00 00 "..BXPC.."
+00000010: 42 58 53 53 44 54 50 43 "BXSSDTPC"
+00000018: 01 00 00 00 49 4E 54 4C "....INTL"
+00000020: 14 02 13 20 ............ "... "
+
+ 5: {
+ 6: External(\_SB.PCI0, DeviceObj)
+ 7: External(\_SB.PCI0.PCEJ, MethodObj)
+ 8: Scope(\_SB.PCI0) {
+
+00000024: 10 33 5C 2E 5F 53 42 5F ".3\._SB_"
+0000002C: 50 43 49 30 ............ "PCI0"
+
+ 18: Device(SAA) {
+
+00000030: 5B 82 26 53 41 41 5F ... "[.&SAA_"
+
+ 22: Name(_SUN, 0xAA)
+
+00000037: 08 5F 53 55 4E 0A AA ... "._SUN.."
+
+ 26: Name(_ADR, 0xAA0000)
+
+0000003E: 08 5F 41 44 52 0C 00 00 "._ADR..."
+00000046: AA 00 .................. ".."
+
+ 30: Method(_EJ0, 1) {
+
+00000048: 14 0F 5F 45 4A 30 01 ... ".._EJ0."
+
+ 31: Return (PCEJ(_SUN))
+
+[****iasl****]
+out/ssdt-pcihp.dsl.i 31: Return (PCEJ(_SUN))
+Warning 1104 - ^ Reserved method should not return a value (_EJ0)
+
+
+
+0000004F: A4 ..................... "."
+00000050: 50 43 45 4A 5F 53 55 4E "PCEJ_SUN"
+ 32: }
+ 33: }
+ 34: }
+ 35: }
+
Summary of errors and warnings
+out/ssdt-pcihp.dsl.i 31: Return (PCEJ(_SUN))
+Warning 1104 - ^ Reserved method should not return a value (_EJ0)
-ASL Optimizing Compiler version 20100528 [Jul 2 2010]
-ASL Input: out/ssdt-pcihp.dsl.i - 37 lines, 767 bytes, 6 keywords
-AML Output: out/ssdt-pcihp.aml - 88 bytes, 5 named objects, 1 executable opcodes
+ASL Optimizing Compiler version 20130214-32 [Apr 6 2013]
-Compilation complete. 0 Errors, 0 Warnings, 0 Remarks, 0 Optimizations
+ASL Input: out/ssdt-pcihp.dsl.i - 37 lines, 359 bytes, 6 keywords
+AML Output: out/ssdt-pcihp.aml - 88 bytes, 5 named objects, 1 executable opcodes
+Listing File: out/ssdt-pcihp.lst - 2016 bytes
+Hex Dump: out/ssdt-pcihp.hex - 228 bytes
+Compilation complete. 0 Errors, 1 Warnings, 0 Remarks, 0 Optimizations
----------------
As you can see, there's no code comments anymore, so
nothing to output by acpi_extract.py
I haven't digged further yet -- just a heads-up for now.
Thanks,
/mjt
</pre>
Michael Tokarev
2013-05-09T14:29:40
-
another iasl update breaks seabios compilation again
http://comments.gmane.org/gmane.comp.bios.coreboot.seabios/6188
<pre>[Resending after being subscribed to the list]
I'm not sure what happened yet, but I noticed that current seabios
does not build with 20130214-32 version of iasl.
Apparently, the listing file (-l) produced now does not contain
any comments from the original source, so tools/acpi_extract.py
produce nothing from these files.
Here's the diff between listing produced by two versions of iasl
for ssdt-pcihp:
----------------
--- out/ssdt-pcihp.lst-201005282013-05-09 17:55:43.872160687 +0400
+++ out/ssdt-pcihp.lst-20130214-322013-05-09 17:57:45.222803783 +0400
< at >< at > -1,84 +1,72 < at >< at >
Intel ACPI Component Architecture
-ASL Optimizing Compiler version 20100528 [Jul 2 2010]
-Copyright (c) 2000 - 2010 Intel Corporation
-Supports ACPI Specification Revision 4.0a
-
-Compilation of "out/ssdt-pcihp.dsl.i" - Thu May 9 17:55:43 2013
-
- 1....
- 2..../* ACPI_EXTRACT_ALL_CODE ssdp_pcihp_aml */
- 3....
- 4....DefinitionBlock ("ssdt-pcihp.aml", "SSDT", 0x01, "BXPC", "BXSSDTPCIHP", 0x1)
-
-00000000....53 53 44 54 58 00 00 00 "SSDTX..."
-00000008....01 77 42 58 50 43 00 00 ".wBXPC.."
-00000010....42 58 53 53 44 54 50 43 "BXSSDTPC"
-00000018....01 00 00 00 49 4E 54 4C "....INTL"
-00000020....28 05 10 20 ............ "(.. "
-
- 5....{
- 6.... External(\_SB.PCI0, DeviceObj)
- 7.... External(\_SB.PCI0.PCEJ, MethodObj)
- 8.... Scope(\_SB.PCI0) {
-
-00000024....10 33 5C 2E 5F 53 42 5F ".3\._SB_"
-0000002C....50 43 49 30 ............ "PCI0"
-
- 9....
- 10..../* ACPI_EXTRACT_DEVICE_START ssdt_pcihp_start */
- 11....
- 12....
- 13..../* ACPI_EXTRACT_DEVICE_END ssdt_pcihp_end */
- 14....
- 15....
- 16..../* ACPI_EXTRACT_DEVICE_STRING ssdt_pcihp_name */
- 17....
- 18.... Device(SAA) {
-
-00000030....5B 82 26 53 41 41 5F ... "[.&SAA_"
-
- 19....
- 20..../* ACPI_EXTRACT_NAME_BYTE_CONST ssdt_pcihp_id */
- 21....
- 22.... Name(_SUN, 0xAA)
-
-00000037....08 5F 53 55 4E 0A AA ... "._SUN.."
-
- 23....
- 24..../* ACPI_EXTRACT_NAME_DWORD_CONST ssdt_pcihp_adr */
- 25....
- 26.... Name(_ADR, 0xAA0000)
-
-0000003E....08 5F 41 44 52 0C 00 00 "._ADR..."
-00000046....AA 00 .................. ".."
-
- 27....
- 28..../* ACPI_EXTRACT_METHOD_STRING ssdt_pcihp_ej0 */
- 29....
- 30.... Method(_EJ0, 1) {
-
-00000048....14 0F 5F 45 4A 30 01 ... ".._EJ0."
-
- 31.... Return (PCEJ(_SUN))
-
-0000004F....A4 ..................... "."
-00000050....50 43 45 4A 5F 53 55 4E "PCEJ_SUN"
- 32.... }
- 33.... }
- 34.... }
- 35....}
- 36....
+ASL Optimizing Compiler version 20130214-32 [Apr 6 2013]
+Copyright (c) 2000 - 2013 Intel Corporation
+
+Compilation of "out/ssdt-pcihp.dsl.i" - Thu May 9 17:57:45 2013
+
+ 4: DefinitionBlock ("ssdt-pcihp.aml", "SSDT", 0x01, "BXPC", "BXSSDTPCIHP", 0x1)
+
+00000000: 53 53 44 54 58 00 00 00 "SSDTX..."
+00000008: 01 8B 42 58 50 43 00 00 "..BXPC.."
+00000010: 42 58 53 53 44 54 50 43 "BXSSDTPC"
+00000018: 01 00 00 00 49 4E 54 4C "....INTL"
+00000020: 14 02 13 20 ............ "... "
+
+ 5: {
+ 6: External(\_SB.PCI0, DeviceObj)
+ 7: External(\_SB.PCI0.PCEJ, MethodObj)
+ 8: Scope(\_SB.PCI0) {
+
+00000024: 10 33 5C 2E 5F 53 42 5F ".3\._SB_"
+0000002C: 50 43 49 30 ............ "PCI0"
+
+ 18: Device(SAA) {
+
+00000030: 5B 82 26 53 41 41 5F ... "[.&SAA_"
+
+ 22: Name(_SUN, 0xAA)
+
+00000037: 08 5F 53 55 4E 0A AA ... "._SUN.."
+
+ 26: Name(_ADR, 0xAA0000)
+
+0000003E: 08 5F 41 44 52 0C 00 00 "._ADR..."
+00000046: AA 00 .................. ".."
+
+ 30: Method(_EJ0, 1) {
+
+00000048: 14 0F 5F 45 4A 30 01 ... ".._EJ0."
+
+ 31: Return (PCEJ(_SUN))
+
+[****iasl****]
+out/ssdt-pcihp.dsl.i 31: Return (PCEJ(_SUN))
+Warning 1104 - ^ Reserved method should not return a value (_EJ0)
+
+
+
+0000004F: A4 ..................... "."
+00000050: 50 43 45 4A 5F 53 55 4E "PCEJ_SUN"
+ 32: }
+ 33: }
+ 34: }
+ 35: }
+
Summary of errors and warnings
+out/ssdt-pcihp.dsl.i 31: Return (PCEJ(_SUN))
+Warning 1104 - ^ Reserved method should not return a value (_EJ0)
-ASL Optimizing Compiler version 20100528 [Jul 2 2010]
-ASL Input: out/ssdt-pcihp.dsl.i - 37 lines, 767 bytes, 6 keywords
-AML Output: out/ssdt-pcihp.aml - 88 bytes, 5 named objects, 1 executable opcodes
+ASL Optimizing Compiler version 20130214-32 [Apr 6 2013]
-Compilation complete. 0 Errors, 0 Warnings, 0 Remarks, 0 Optimizations
+ASL Input: out/ssdt-pcihp.dsl.i - 37 lines, 359 bytes, 6 keywords
+AML Output: out/ssdt-pcihp.aml - 88 bytes, 5 named objects, 1 executable opcodes
+Listing File: out/ssdt-pcihp.lst - 2016 bytes
+Hex Dump: out/ssdt-pcihp.hex - 228 bytes
+Compilation complete. 0 Errors, 1 Warnings, 0 Remarks, 0 Optimizations
----------------
As you can see, there's no code comments anymore, so
nothing to output by acpi_extract.py
I haven't digged further yet -- just a heads-up for now.
Thanks,
/mjt
</pre>
Michael Tokarev
2013-05-09T14:48:17
-
How to modify qemu-kvm bios.bin?
http://comments.gmane.org/gmane.comp.bios.coreboot.seabios/6161
<pre>I know qemu-kvm use seabios as pc bios.i just want let vm created by
qemu-kvm show a custom JPEG image during bootup. How to modify the file
bios.bin?
I see the following command on coreboot website，but i can't find
coreboot.rom file in /usr/share/qemu-kvm/ . maybe qemu-kvm use non-coreboot
uses,How do I do to reach my goal？
./build/cbfstool build/coreboot.rom add -f /path/to/image.jpg -n
bootsplash.jpg -t raw
_______________________________________________
SeaBIOS mailing list
SeaBIOS< at >seabios.org
http://www.seabios.org/mailman/listinfo/seabios
</pre>
li peter
2013-05-06T06:20:10
-
[PATCH] acpi: minor clean-up of 64 bit window logic
http://comments.gmane.org/gmane.comp.bios.coreboot.seabios/6156
<pre>Make 64 bit window detection logic a bit cleaner:
don't hardcode 0 address as invalid, instead
check start < end.
Signed-off-by: Michael S. Tsirkin <mst< at >redhat.com>
---
src/acpi.c | 2 +-
src/pciinit.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/acpi.c b/src/acpi.c
index b03b2ba..1037093 100644
--- a/src/acpi.c
+++ b/src/acpi.c
< at >< at > -355,7 +355,7 < at >< at > build_ssdt(void)
// store pci io windows
*(u32*)&ssdt_ptr[acpi_pci32_start[0]] = cpu_to_le32(pcimem_start);
*(u32*)&ssdt_ptr[acpi_pci32_end[0]] = cpu_to_le32(pcimem_end - 1);
- if (pcimem64_start) {
+ if (pcimem64_start < pcimem64_end) {
ssdt_ptr[acpi_pci64_valid[0]] = 1;
*(u64*)&ssdt_ptr[acpi_pci64_start[0]] = cpu_to_le64(pcimem64_start);
*(u64*)&ssdt_ptr[acpi_pci64_end[0]] = cpu_to_le64(pcimem64_end - 1);
diff --git a/src/pciinit.c b/src/pciinit.c
index a4a5bf5..fdf1362 100644
--- a/src/pciinit.c
+++ b/src/pciinit.c
< at >< at > -818,7 +818,7 < at >< at > static void pci_bios_map_devices(struct pci_bus *busses, struct pci_mem *mem)
pci_region_map_entries(busses, &r64_pref);
} else if (!mem) {
// no bars mapped high -> drop 64bit window (see dsdt)
- pcimem64_start = 0;
+ pcimem64_end = pcimem64_start = 0;
}
// Map regions on each device.
int bus;
</pre>
Michael S. Tsirkin
2013-04-30T10:36:33
-
[PATCHv2] pci: load memory window setup from host
http://comments.gmane.org/gmane.comp.bios.coreboot.seabios/6154
<pre>Load memory window setup for pci from host.
This makes it possible for host to make sure
setup matches hardware exactly: especially important
for when ACPI tables are loaded from host.
This will also make it easier to add more chipsets
down the road.
Signed-off-by: Michael S. Tsirkin <mst< at >redhat.com>
---
Changes from v1:
- fix bug in 64 bit range check
- address Kevin's comments:
move file load into pciinit.c
dont reorder initialization
sizeof style fix
src/pciinit.c | 91 ++++++++++++++++++++++++++++++++++++++++++++++++-----------
1 file changed, 75 insertions(+), 16 deletions(-)
diff --git a/src/pciinit.c b/src/pciinit.c
index bb9355f..a4a5bf5 100644
--- a/src/pciinit.c
+++ b/src/pciinit.c
< at >< at > -13,6 +13,7 < at >< at >
#include "config.h" // CONFIG_*
#include "memmap.h" // add_e820
#include "paravirt.h" // RamSize
+#include "byteorder.h" // le64_to_cpu
#include "dev-q35.h"
/* PM Timer ticks per second (HZ) */
< at >< at > -61,6 +62,13 < at >< at > struct pci_bus {
struct pci_device *bus_dev;
};
+struct pci_mem {
+u64 start32;
+u64 end32;
+u64 start64;
+u64 end64;
+};
+
static u32 pci_bar(struct pci_device *pci, int region_num)
{
if (region_num != PCI_ROM_SLOT) {
< at >< at > -361,6 +369,8 < at >< at > static void pci_enable_default_vga(void)
void i440fx_mem_addr_setup(struct pci_device *dev, void *arg)
{
+ if (arg)
+/* use supplied memory */;
if (RamSize <= 0x80000000)
pcimem_start = 0x80000000;
else if (RamSize <= 0xc0000000)
< at >< at > -383,8 +393,9 < at >< at > void mch_mem_addr_setup(struct pci_device *dev, void *arg)
pci_config_writel(bdf, Q35_HOST_BRIDGE_PCIEXBAR, lower);
add_e820(addr, size, E820_RESERVED);
- /* setup pci i/o window (above mmconfig) */
- pcimem_start = addr + size;
+ /* unless done already, setup pci i/o window (above mmconfig) */
+ if (!arg)
+ pcimem_start = addr + size;
pci_slot_get_irq = mch_pci_slot_get_irq;
}
< at >< at > -397,11 +408,11 < at >< at > static const struct pci_device_id pci_platform_tbl[] = {
PCI_DEVICE_END
};
-static void pci_bios_init_platform(void)
+static void pci_bios_init_platform(struct pci_mem *mem)
{
struct pci_device *pci;
foreachpci(pci) {
- pci_init_device(pci_platform_tbl, pci, NULL);
+ pci_init_device(pci_platform_tbl, pci, mem);
}
}
< at >< at > -762,10 +773,14 < at >< at > static void pci_region_map_entries(struct pci_bus *busses, struct pci_region *r)
}
}
-static void pci_bios_map_devices(struct pci_bus *busses)
+static void pci_bios_map_devices(struct pci_bus *busses, struct pci_mem *mem)
{
if (pci_bios_init_root_regions(busses)) {
struct pci_region r64_mem, r64_pref;
+
+ if (mem && mem->start64 >= mem->end64)
+ panic("PCI: out of 32bit address space\n");
+
r64_mem.list = NULL;
r64_pref.list = NULL;
pci_region_migrate_64bit_entries(&busses[0].r[PCI_REGION_TYPE_MEM],
< at >< at > -781,14 +796,27 < at >< at > static void pci_bios_map_devices(struct pci_bus *busses)
u64 align_mem = pci_region_align(&r64_mem);
u64 align_pref = pci_region_align(&r64_pref);
- r64_mem.base = ALIGN(0x100000000LL + RamSizeOver4G, align_mem);
- r64_pref.base = ALIGN(r64_mem.base + sum_mem, align_pref);
- pcimem64_start = r64_mem.base;
- pcimem64_end = r64_pref.base + sum_pref;
+ if (mem) {
+ /*
+ * Non prefetcheable memory at start of the window,
+ * prefetcheable memory at the end.
+ * This way OS has the maximum flexibility for
+ * allocating the rest of the memory.
+ */
+ r64_mem.base = ALIGN(mem->start64, align_mem);
+ r64_pref.base = ALIGN_DOWN(mem->end64 - sum_pref + 1, align_pref);
+ if (sum_pref && r64_pref.base < r64_mem.base + sum_mem)
+ panic("PCI: out of 64bit address space\n");
+ } else {
+ r64_mem.base = ALIGN(0x100000000LL + RamSizeOver4G, align_mem);
+ r64_pref.base = ALIGN(r64_mem.base + sum_mem, align_pref);
+ pcimem64_start = r64_mem.base;
+ pcimem64_end = r64_pref.base + sum_pref;
+ }
pci_region_map_entries(busses, &r64_mem);
pci_region_map_entries(busses, &r64_pref);
- } else {
+ } else if (!mem) {
// no bars mapped high -> drop 64bit window (see dsdt)
pcimem64_start = 0;
}
< at >< at > -801,11 +829,28 < at >< at > static void pci_bios_map_devices(struct pci_bus *busses)
}
}
+static
+struct pci_mem *pci_mem_get(void)
+{
+ int psize;
+ struct pci_mem *mem = romfile_loadfile("etc/pci-info", &psize);
+ if (!mem)
+ return NULL;
+ if (psize < sizeof(*mem)) {
+ free(mem);
+ return NULL;
+ }
+ mem->start32 = le64_to_cpu(mem->start32);
+ mem->end32 = le64_to_cpu(mem->end32);
+ mem->start64 = le64_to_cpu(mem->start64);
+ mem->end64 = le64_to_cpu(mem->end64);
+ return mem;
+}
+
/****************************************************************
* Main setup code
****************************************************************/
-
void
pci_setup(void)
{
< at >< at > -823,25 +868,39 < at >< at > pci_setup(void)
dprintf(1, "=== PCI device probing ===\n");
pci_probe_devices();
- pcimem_start = RamSize;
- pci_bios_init_platform();
+ struct pci_mem *mem = pci_mem_get();
+
+ if (mem) {
+ pcimem_start = mem->start32;
+ pcimem_end = mem->end32;
+ pcimem64_start = mem->start64;
+ pcimem64_end = mem->end64;
+ } else {
+ pcimem_start = RamSize;
+ }
+
+ pci_bios_init_platform(mem);
dprintf(1, "=== PCI new allocation pass #1 ===\n");
struct pci_bus *busses = malloc_tmp(sizeof(*busses) * (MaxPCIBus + 1));
if (!busses) {
warn_noalloc();
- return;
+ goto done;
}
memset(busses, 0, sizeof(*busses) * (MaxPCIBus + 1));
if (pci_bios_check_devices(busses))
- return;
+ goto done;
dprintf(1, "=== PCI new allocation pass #2 ===\n");
- pci_bios_map_devices(busses);
+ pci_bios_map_devices(busses, mem);
pci_bios_init_devices();
free(busses);
pci_enable_default_vga();
+
+done:
+ if (mem)
+ free(mem);
}
</pre>
Michael S. Tsirkin
2013-04-30T06:34:55
-
[PATCH 0/2] paravirt: load pci window data from host
http://comments.gmane.org/gmane.comp.bios.coreboot.seabios/6145
<pre>This makes it possible to load pci window
data from host, when running on qemu.
This makes it possible for host to make sure
setup matches hardware exactly: especially important
for when ACPI tables are loaded from host.
This will also make it easier to add more chipsets
down the road.
Michael S. Tsirkin (2):
paravirt: init qemu cfg earlier
pci: load memory window setup from host
src/paravirt.c | 27 ++++++++++++++++++++++++++-
src/pciinit.c | 54 ++++++++++++++++++++++++++++++++++++++++--------------
src/post.c | 1 -
src/util.h | 8 +++++++-
4 files changed, 73 insertions(+), 17 deletions(-)
</pre>
Michael S. Tsirkin
2013-04-29T15:21:37
-
[PATCH] ps2: disable the keyboard and mouse beforeflushing the queue
http://comments.gmane.org/gmane.comp.bios.coreboot.seabios/6140
<pre>If SeaBIOS is run as a payload via coreboot (and presumably as a
CSM), then it's possible the keyboard or mouse will still be
enabled. This can lead to data being queued even after the flush
function attempts to clear the queue.
Disabling the keyboard/mouse prior to flushing is pretty standard
in DOS programming so it's not surprising that it's needed here.
I believe this problem manifests with the Chromebook Pixel. People
have reported that sometimes the 'ESC to Select Boot Devices'
doesn't work. I can reproduce this faithfully by holding 'Ctrl-L'
in the firmware screen during SeaBIOS initialization.
I can't test this fix on an actual Pixel because I don't know how
to update SeaBIOS but I have tested the patch under QEMU.
Signed-off-by: Anthony Liguori <aliguori< at >us.ibm.com>
---
src/ps2port.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/src/ps2port.c b/src/ps2port.c
index 9b760fd..2169171 100644
--- a/src/ps2port.c
+++ b/src/ps2port.c
< at >< at > -55,6 +55,12 < at >< at > static int
i8042_flush(void)
{
dprintf(7, "i8042_flush\n");
+
+ /* Disable the keyboard and mouse to prevent additional data from
+ * being queued. */
+ outb(0xad, PORT_PS2_STATUS);
+ outb(0xa7, PORT_PS2_STATUS);
+
int i;
for (i=0; i<I8042_BUFFER_SIZE; i++) {
u8 status = inb(PORT_PS2_STATUS);
</pre>
Anthony Liguori
2013-04-25T01:32:09
-
[RFC][PATCH 1/2] acpi: add ASL for Embedded Controller
http://comments.gmane.org/gmane.comp.bios.coreboot.seabios/6101
<pre>defined at ACPI SPEC v5 chapter 12:
"ACPI Embedded Controller Interface Specification"
Signed-off-by: liguang <lig.fnst< at >cn.fujitsu.com>
---
src/acpi-dsdt-ec.dsl | 106 ++++++++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 106 insertions(+), 0 deletions(-)
create mode 100644 src/acpi-dsdt-ec.dsl
diff --git a/src/acpi-dsdt-ec.dsl b/src/acpi-dsdt-ec.dsl
new file mode 100644
index 0000000..6bd8edd
--- /dev/null
+++ b/src/acpi-dsdt-ec.dsl
< at >< at > -0,0 +1,106 < at >< at >
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+Device (EC0)
+{
+Name (_HID, EISAID ("PNP0C09"))
+Name(_UID, 1)
+
+Method(_CRS, 0)
+ {
+ Name(BFFR, ResourceTemplate()
+ {
+ IO(Decode16, 0x62, 0x62, 0, 1) // ACPI DATA IN/OUT
+ IO(Decode16, 0x66, 0x66, 0, 1) // CMD/STS
+ IRQ(Edge, ActiveHigh, Exclusive) {0x0B}
+ })
+ Return(BFFR)
+ }
+
+ OperationRegion(ECF0, EmbeddedControl, 0, 0xFF)
+ Field(ECF2, ByteAcc, Lock, Preserve)
+ {
+Offset(1),
+STMP, 8, // 1, Sensor Temperature
+ACPW, 8, // 2, AC Power (AC Present = 1, else 0)
+LIDS, 8, // 3, Lid State (Lid Open = 1, else 0)
+PBNS, 8, // 4, Power Button State (Pressed = 1, else 0)
+BTST, 8, // 5, Battery Status
+BTCR, 8, // 6, Battery Current Rate
+BTCC, 8, // 7, Battery Current Capacity
+BTVT, 8, // 8, Battery Voltage
+offset(0x10),
+SPTR, 8, // 5, SMBus Protocol Register
+SSTS, 8, // 5, SMBus Status Register
+SADR, 8, // 6, SMBus Address Register
+SCMD, 8, // 7, SMBus Command Register
+SBFR, 256, // 8, SMBus Block Buffer
+SCNT, 8, // 40, SMBus Block Count
+ }
+
+Method(_REG, 2)
+{
+}
+
+/* AC status: present */
+Method(_Q01, 0, NotSerialized)
+{
+Notify (AC, 0x80)
+}
+
+/* AC status: dispear*/
+Method(_Q02, 0, NotSerialized)
+{
+Notify (AC, 0x80)
+}
+
+ Method(_Q04, 0, NotSerialized)
+ {
+ Notify(LID, 0x80)
+ }
+
+ Method(_Q04, 0, NotSerialized)
+ {
+ Notify(LID, 0x80)
+ }
+
+Device(AC)
+{
+Name(_HID, "ACPI0003")
+Name(_UID, 0x00)
+Name(_PCL, Package() { \_SB } )
+
+Method(_PSR, 0, NotSerialized)
+{
+return (ACPW)
+}
+
+Method(_STA, 0, NotSerialized)
+{
+Return (0x0f)
+}
+}
+
+Device(LID)
+{
+Name(_HID, "PNP0C0D")
+
+Method(_LID, 0, NotSerialized)
+{
+return (LIDS)
+}
+}
+}
</pre>
liguang
2013-04-17T07:22:59
-
[qemu PATCH 0/5] publish etc/acpi/APIC in fw_cfg
http://comments.gmane.org/gmane.comp.bios.coreboot.seabios/6091
<pre>This series exports the MADT (APIC) ACPI table under the new
"etc/acpi/APIC" fw_cfg file. I sought to follow the requirements set
forth in [1], the new table is only visible in the patched/patched case.
I cross-tested { master, patched } qemu with { master, patched } seabios
(the APIC, DSDT and RSDT tables) using guest acpidump and dmesg.
The -acpitable command line option is purposely ignored based on the
last paragraph of [2]; the user isn't supposed to pass APIC with that
option.
checkpatch.pl complains a little but (as last time) it's a false alarm.
The series is bisectable.
[1] http://thread.gmane.org/gmane.comp.emulators.qemu/202005/focus=202072
[2] http://thread.gmane.org/gmane.comp.bios.coreboot.seabios/5960/focus=6008
Laszlo Ersek (5):
refer to FWCfgState explicitly
hw/acpi: extract standard table headers as a standalone structure
hw/acpi: export default ACPI headers using the type just introduced
hw/acpi: export acpi_checksum()
i386/pc: build ACPI MADT (APIC) for fw_cfg clients
hw/acpi.h | 15 +++++
hw/loader.h | 3 +-
hw/multiboot.h | 4 +-
hw/pc.h | 20 ++++---
hw/acpi.c | 89 ++++++++++++++-------------
hw/acpi_piix4.c | 2 +-
hw/i386/multiboot.c | 2 +-
hw/i386/pc.c | 166 +++++++++++++++++++++++++++++++++++++++++++++++----
hw/i386/pc_piix.c | 4 +-
hw/i386/pc_q35.c | 10 ++-
hw/loader.c | 2 +-
hw/sparc/sun4m.c | 6 +-
hw/sparc64/sun4u.c | 2 +-
13 files changed, 248 insertions(+), 77 deletions(-)
</pre>
Laszlo Ersek
2013-04-08T13:13:18
-
[seabios PATCH] install the MADT from the "etc/acpi/APIC"fw_cfg file if it's available
http://comments.gmane.org/gmane.comp.bios.coreboot.seabios/6089
<pre>
Signed-off-by: Laszlo Ersek <lersek< at >redhat.com>
---
src/acpi.c | 29 ++++++++++++++++++++++++++++-
1 files changed, 28 insertions(+), 1 deletions(-)
diff --git a/src/acpi.c b/src/acpi.c
index bc4d8ea..9e128b2 100644
--- a/src/acpi.c
+++ b/src/acpi.c
< at >< at > -393,6 +393,33 < at >< at > build_madt(void)
return madt;
}
+static void*
+find_table(const char *sig, void *(*buildfn)(void))
+{
+ char buf[] = "etc/acpi/QUUX";
+ struct romfile_s *file;
+
+ snprintf(buf + (sizeof buf - 1 - 4), 4 + 1, "%s", sig);
+ file = romfile_find(buf);
+ if (file != NULL && file->size >= sizeof(struct acpi_table_header)) {
+ void *table;
+
+ table = malloc_high(file->size);
+ if (table == NULL)
+ warn_noalloc();
+ else {
+ if ((*file->copy)(file, table, file->size) == file->size) {
+ dprintf(4, "ACPI %s: using fw_cfg %s\n", sig, buf);
+ return table;
+ }
+ free(table);
+ }
+ }
+
+ dprintf(4, "ACPI %s: building default\n", sig);
+ return (*buildfn)();
+}
+
// Encode a hex value
static inline char getHex(u32 val) {
val &= 0x0f;
< at >< at > -792,7 +819,7 < at >< at > acpi_setup(void)
struct fadt_descriptor_rev1 *fadt = build_fadt(pci);
ACPI_INIT_TABLE(fadt);
ACPI_INIT_TABLE(build_ssdt());
- ACPI_INIT_TABLE(build_madt());
+ ACPI_INIT_TABLE(find_table("APIC", build_madt));
ACPI_INIT_TABLE(build_hpet());
ACPI_INIT_TABLE(build_srat());
if (pci->device == PCI_DEVICE_ID_INTEL_ICH9_LPC)
</pre>
Laszlo Ersek
2013-04-08T13:14:32
-
[PATCH 3/3] acpi: Use cpu_to_leXX() consistently.
http://comments.gmane.org/gmane.comp.bios.coreboot.seabios/6075
<pre>Audit the ACPI code and ensure that all multi-byte fields do proper
byte swabbing.
Signed-off-by: Kevin O'Connor <kevin< at >koconnor.net>
---
src/acpi.c | 47 +++++++++++++++++++++++------------------------
src/acpi.h | 4 ++--
2 files changed, 25 insertions(+), 26 deletions(-)
diff --git a/src/acpi.c b/src/acpi.c
index f8fc228..f39c232 100644
--- a/src/acpi.c
+++ b/src/acpi.c
< at >< at > -21,7 +21,7 < at >< at >
static void
build_header(struct acpi_table_header *h, u32 sig, int len, u8 rev)
{
- h->signature = sig;
+ h->signature = cpu_to_le32(sig);
h->length = cpu_to_le32(len);
h->revision = rev;
memcpy(h->oem_id, BUILD_APPNAME6, 6);
< at >< at > -123,7 +123,7 < at >< at > build_fadt(struct pci_device *pci)
/* FACS */
memset(facs, 0, sizeof(*facs));
- facs->signature = FACS_SIGNATURE;
+ facs->signature = cpu_to_le32(FACS_SIGNATURE);
facs->length = cpu_to_le32(sizeof(*facs));
/* FADT */
< at >< at > -181,8 +181,8 < at >< at > build_madt(void)
intsrcovr->type = APIC_XRUPT_OVERRIDE;
intsrcovr->length = sizeof(*intsrcovr);
intsrcovr->source = 0;
- intsrcovr->gsi = 2;
- intsrcovr->flags = 0; /* conforms to bus specifications */
+ intsrcovr->gsi = cpu_to_le32(2);
+ intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */
intsrcovr++;
}
for (i = 1; i < 16; i++) {
< at >< at > -193,8 +193,8 < at >< at > build_madt(void)
intsrcovr->type = APIC_XRUPT_OVERRIDE;
intsrcovr->length = sizeof(*intsrcovr);
intsrcovr->source = i;
- intsrcovr->gsi = i;
- intsrcovr->flags = 0xd; /* active high, level triggered */
+ intsrcovr->gsi = cpu_to_le32(i);
+ intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */
intsrcovr++;
}
< at >< at > -202,7 +202,7 < at >< at > build_madt(void)
local_nmi->type = APIC_LOCAL_NMI;
local_nmi->length = sizeof(*local_nmi);
local_nmi->processor_id = 0xff; /* all processors */
- local_nmi->flags = 0;
+ local_nmi->flags = cpu_to_le16(0);
local_nmi->lint = 1; /* LINT1 */
local_nmi++;
< at >< at > -340,13 +340,14 < at >< at > build_ssdt(void)
ssdt_ptr[acpi_s4_pkg[0] + 1] = ssdt[acpi_s4_pkg[0] + 3] = sys_states[4] & 127;
// store pci io windows
- *(u32*)&ssdt_ptr[acpi_pci32_start[0]] = pcimem_start;
- *(u32*)&ssdt_ptr[acpi_pci32_end[0]] = pcimem_end - 1;
+ *(u32*)&ssdt_ptr[acpi_pci32_start[0]] = cpu_to_le32(pcimem_start);
+ *(u32*)&ssdt_ptr[acpi_pci32_end[0]] = cpu_to_le32(pcimem_end - 1);
if (pcimem64_start) {
ssdt_ptr[acpi_pci64_valid[0]] = 1;
- *(u64*)&ssdt_ptr[acpi_pci64_start[0]] = pcimem64_start;
- *(u64*)&ssdt_ptr[acpi_pci64_end[0]] = pcimem64_end - 1;
- *(u64*)&ssdt_ptr[acpi_pci64_length[0]] = pcimem64_end - pcimem64_start;
+ *(u64*)&ssdt_ptr[acpi_pci64_start[0]] = cpu_to_le64(pcimem64_start);
+ *(u64*)&ssdt_ptr[acpi_pci64_end[0]] = cpu_to_le64(pcimem64_end - 1);
+ *(u64*)&ssdt_ptr[acpi_pci64_length[0]] = cpu_to_le64(
+ pcimem64_end - pcimem64_start);
} else {
ssdt_ptr[acpi_pci64_valid[0]] = 0;
}
< at >< at > -440,7 +441,7 < at >< at > build_hpet(void)
* emulated hpet
*/
hpet->timer_block_id = cpu_to_le32(0x8086a201);
- hpet->addr.address = cpu_to_le32(BUILD_HPET_ADDRESS);
+ hpet->addr.address = cpu_to_le64(BUILD_HPET_ADDRESS);
build_header((void*)hpet, HPET_SIGNATURE, sizeof(*hpet), 1);
return hpet;
< at >< at > -452,13 +453,11 < at >< at > acpi_build_srat_memory(struct srat_memory_affinity *numamem,
{
numamem->type = SRAT_MEMORY;
numamem->length = sizeof(*numamem);
- memset(numamem->proximity, 0 ,4);
+ memset(numamem->proximity, 0, 4);
numamem->proximity[0] = node;
numamem->flags = cpu_to_le32(!!enabled);
- numamem->base_addr_low = base & 0xFFFFFFFF;
- numamem->base_addr_high = base >> 32;
- numamem->length_low = len & 0xFFFFFFFF;
- numamem->length_high = len >> 32;
+ numamem->base_addr = cpu_to_le64(base);
+ numamem->range_length = cpu_to_le64(len);
}
static void *
< at >< at > -484,7 +483,7 < at >< at > build_srat(void)
}
memset(srat, 0, srat_size);
- srat->reserved1=1;
+ srat->reserved1=cpu_to_le32(1);
struct srat_processor_affinity *core = (void*)(srat + 1);
int i;
u64 curnode;
< at >< at > -567,8 +566,8 < at >< at > build_mcfg_q35(void)
return NULL;
}
memset(mcfg, 0, len);
- mcfg->allocation[0].address = Q35_HOST_BRIDGE_PCIEXBAR_ADDR;
- mcfg->allocation[0].pci_segment = Q35_HOST_PCIE_PCI_SEGMENT;
+ mcfg->allocation[0].address = cpu_to_le64(Q35_HOST_BRIDGE_PCIEXBAR_ADDR);
+ mcfg->allocation[0].pci_segment = cpu_to_le16(Q35_HOST_PCIE_PCI_SEGMENT);
mcfg->allocation[0].start_bus_number = Q35_HOST_PCIE_START_BUS_NUMBER;
mcfg->allocation[0].end_bus_number = Q35_HOST_PCIE_END_BUS_NUMBER;
< at >< at > -605,8 +604,8 < at >< at > acpi_setup(void)
#define ACPI_INIT_TABLE(X) \
do { \
- tables[tbl_idx] = (u32)(X); \
- if (tables[tbl_idx]) \
+ tables[tbl_idx] = cpu_to_le32((u32)(X)); \
+ if (le32_to_cpu(tables[tbl_idx])) \
tbl_idx++; \
} while(0)
< at >< at > -675,7 +674,7 < at >< at > acpi_setup(void)
return;
}
memset(rsdp, 0, sizeof(*rsdp));
- rsdp->signature = RSDP_SIGNATURE;
+ rsdp->signature = cpu_to_le64(RSDP_SIGNATURE);
memcpy(rsdp->oem_id, BUILD_APPNAME6, 6);
rsdp->rsdt_physical_address = cpu_to_le32((u32)rsdt);
rsdp->checksum -= checksum(rsdp, 20);
diff --git a/src/acpi.h b/src/acpi.h
index 43287d9..5d1e104 100644
--- a/src/acpi.h
+++ b/src/acpi.h
< at >< at > -254,8 +254,8 < at >< at > struct srat_memory_affinity
ACPI_SUB_HEADER_DEF
u8 proximity[4];
u16 reserved1;
- u32 base_addr_low,base_addr_high;
- u32 length_low,length_high;
+ u64 base_addr;
+ u64 range_length;
u32 reserved2;
u32 flags;
u32 reserved3[2];
</pre>
Kevin O'Connor
2013-03-30T15:51:04
-
[PATCH 2/3] acpi: Remove dead code with descriptions ofbit flags.
http://comments.gmane.org/gmane.comp.bios.coreboot.seabios/6074
<pre>Remove dead code from acpi table definitions - the ACPI specification
is the best place to get descriptions of the fields and tables anyway.
Signed-off-by: Kevin O'Connor <kevin< at >koconnor.net>
---
src/acpi.h | 26 +-------------------------
1 file changed, 1 insertion(+), 25 deletions(-)
diff --git a/src/acpi.h b/src/acpi.h
index 097cc75..43287d9 100644
--- a/src/acpi.h
+++ b/src/acpi.h
< at >< at > -97,20 +97,7 < at >< at > struct fadt_descriptor_rev1
u8 reserved4; /* Reserved */
u8 reserved4a; /* Reserved */
u8 reserved4b; /* Reserved */
-#if 0
- u32 wb_invd : 1; /* The wbinvd instruction works properly */
- u32 wb_invd_flush : 1; /* The wbinvd flushes but does not invalidate */
- u32 proc_c1 : 1; /* All processors support C1 state */
- u32 plvl2_up : 1; /* C2 state works on MP system */
- u32 pwr_button : 1; /* Power button is handled as a generic feature */
- u32 sleep_button : 1; /* Sleep button is handled as a generic feature, or not present */
- u32 fixed_rTC : 1; /* RTC wakeup stat not in fixed register space */
- u32 rtcs4 : 1; /* RTC wakeup stat not possible from S4 */
- u32 tmr_val_ext : 1; /* The tmr_val width is 32 bits (0 = 24 bits) */
- u32 reserved5 : 23; /* Reserved - must be zero */
-#else
u32 flags;
-#endif
} PACKED;
struct acpi_table_header /* ACPI common table header */
< at >< at > -140,8 +127,7 < at >< at > struct facs_descriptor_rev1
u32 hardware_signature; /* Hardware configuration signature */
u32 firmware_waking_vector; /* ACPI OS waking vector */
u32 global_lock; /* Global Lock */
- u32 S4bios_f : 1; /* Indicates if S4BIOS support is present */
- u32 reserved1 : 31; /* Must be 0 */
+ u32 flags;
u8 resverved3 [40]; /* Reserved - must be zero */
} PACKED;
< at >< at > -166,12 +152,7 < at >< at > struct multiple_apic_table
{
ACPI_TABLE_HEADER_DEF /* ACPI common table header */
u32 local_apic_address; /* Physical address of local APIC */
-#if 0
- u32 PCATcompat : 1; /* A one indicates system also has dual 8259s */
- u32 reserved1 : 31;
-#else
u32 flags;
-#endif
} PACKED;
/* Values for Type in APIC sub-headers */
< at >< at > -201,12 +182,7 < at >< at > struct madt_processor_apic
ACPI_SUB_HEADER_DEF
u8 processor_id; /* ACPI processor id */
u8 local_apic_id; /* Processor's local APIC id */
-#if 0
- u32 processor_enabled: 1; /* Processor is usable if set */
- u32 reserved2 : 31; /* Reserved, must be zero */
-#else
u32 flags;
-#endif
} PACKED;
struct madt_io_apic
</pre>
Kevin O'Connor
2013-03-30T15:50:39
-
[PATCH 1/3] acpi: Move ACPI table definitions from acpi.cto acpi.h.
http://comments.gmane.org/gmane.comp.bios.coreboot.seabios/6073
<pre>Signed-off-by: Kevin O'Connor <kevin< at >koconnor.net>
---
src/acpi.c | 188 +------------------------------------------------------------
src/acpi.h | 172 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 175 insertions(+), 185 deletions(-)
diff --git a/src/acpi.c b/src/acpi.c
index 55c7259..f8fc228 100644
--- a/src/acpi.c
+++ b/src/acpi.c
< at >< at > -16,189 +16,6 < at >< at >
#include "paravirt.h" // RamSize
#include "dev-q35.h"
-/****************************************************/
-/* ACPI tables init */
-
-/* Table structure from Linux kernel (the ACPI tables are under the
- BSD license) */
-
-struct acpi_table_header /* ACPI common table header */
-{
- ACPI_TABLE_HEADER_DEF
-} PACKED;
-
-/*
- * ACPI 1.0 Root System Description Table (RSDT)
- */
-#define RSDT_SIGNATURE 0x54445352 // RSDT
-struct rsdt_descriptor_rev1
-{
- ACPI_TABLE_HEADER_DEF /* ACPI common table header */
- u32 table_offset_entry[0]; /* Array of pointers to other */
- /* ACPI tables */
-} PACKED;
-
-/*
- * ACPI 1.0 Firmware ACPI Control Structure (FACS)
- */
-#define FACS_SIGNATURE 0x53434146 // FACS
-struct facs_descriptor_rev1
-{
- u32 signature; /* ACPI Signature */
- u32 length; /* Length of structure, in bytes */
- u32 hardware_signature; /* Hardware configuration signature */
- u32 firmware_waking_vector; /* ACPI OS waking vector */
- u32 global_lock; /* Global Lock */
- u32 S4bios_f : 1; /* Indicates if S4BIOS support is present */
- u32 reserved1 : 31; /* Must be 0 */
- u8 resverved3 [40]; /* Reserved - must be zero */
-} PACKED;
-
-
-/*
- * Differentiated System Description Table (DSDT)
- */
-#define DSDT_SIGNATURE 0x54445344 // DSDT
-
-/*
- * MADT values and structures
- */
-
-/* Values for MADT PCATCompat */
-
-#define DUAL_PIC 0
-#define MULTIPLE_APIC 1
-
-
-/* Master MADT */
-
-#define APIC_SIGNATURE 0x43495041 // APIC
-struct multiple_apic_table
-{
- ACPI_TABLE_HEADER_DEF /* ACPI common table header */
- u32 local_apic_address; /* Physical address of local APIC */
-#if 0
- u32 PCATcompat : 1; /* A one indicates system also has dual 8259s */
- u32 reserved1 : 31;
-#else
- u32 flags;
-#endif
-} PACKED;
-
-
-/* Values for Type in APIC sub-headers */
-
-#define APIC_PROCESSOR 0
-#define APIC_IO 1
-#define APIC_XRUPT_OVERRIDE 2
-#define APIC_NMI 3
-#define APIC_LOCAL_NMI 4
-#define APIC_ADDRESS_OVERRIDE 5
-#define APIC_IO_SAPIC 6
-#define APIC_LOCAL_SAPIC 7
-#define APIC_XRUPT_SOURCE 8
-#define APIC_RESERVED 9 /* 9 and greater are reserved */
-
-/*
- * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
- */
-#define ACPI_SUB_HEADER_DEF /* Common ACPI sub-structure header */\
- u8 type; \
- u8 length;
-
-/* Sub-structures for MADT */
-
-struct madt_processor_apic
-{
- ACPI_SUB_HEADER_DEF
- u8 processor_id; /* ACPI processor id */
- u8 local_apic_id; /* Processor's local APIC id */
-#if 0
- u32 processor_enabled: 1; /* Processor is usable if set */
- u32 reserved2 : 31; /* Reserved, must be zero */
-#else
- u32 flags;
-#endif
-} PACKED;
-
-struct madt_io_apic
-{
- ACPI_SUB_HEADER_DEF
- u8 io_apic_id; /* I/O APIC ID */
- u8 reserved; /* Reserved - must be zero */
- u32 address; /* APIC physical address */
- u32 interrupt; /* Global system interrupt where INTI
- * lines start */
-} PACKED;
-
-struct madt_intsrcovr {
- ACPI_SUB_HEADER_DEF
- u8 bus;
- u8 source;
- u32 gsi;
- u16 flags;
-} PACKED;
-
-struct madt_local_nmi {
- ACPI_SUB_HEADER_DEF
- u8 processor_id; /* ACPI processor id */
- u16 flags; /* MPS INTI flags */
- u8 lint; /* Local APIC LINT# */
-} PACKED;
-
-
-/*
- * HPET Description Table
- */
-struct acpi_20_hpet {
- ACPI_TABLE_HEADER_DEF /* ACPI common table header */
- u32 timer_block_id;
- struct acpi_20_generic_address addr;
- u8 hpet_number;
- u16 min_tick;
- u8 page_protect;
-} PACKED;
-
-#define HPET_ID 0x000
-#define HPET_PERIOD 0x004
-
-/*
- * SRAT (NUMA topology description) table
- */
-
-#define SRAT_PROCESSOR 0
-#define SRAT_MEMORY 1
-
-struct system_resource_affinity_table
-{
- ACPI_TABLE_HEADER_DEF
- u32 reserved1;
- u32 reserved2[2];
-} PACKED;
-
-struct srat_processor_affinity
-{
- ACPI_SUB_HEADER_DEF
- u8 proximity_lo;
- u8 local_apic_id;
- u32 flags;
- u8 local_sapic_eid;
- u8 proximity_hi[3];
- u32 reserved;
-} PACKED;
-
-struct srat_memory_affinity
-{
- ACPI_SUB_HEADER_DEF
- u8 proximity[4];
- u16 reserved1;
- u32 base_addr_low,base_addr_high;
- u32 length_low,length_high;
- u32 reserved2;
- u32 flags;
- u32 reserved3[2];
-} PACKED;
-
#include "acpi-dsdt.hex"
static void
< at >< at > -597,7 +414,9 < at >< at > build_ssdt(void)
return ssdt;
}
-#define HPET_SIGNATURE 0x54455048 // HPET
+#define HPET_ID 0x000
+#define HPET_PERIOD 0x004
+
static void*
build_hpet(void)
{
< at >< at > -642,7 +461,6 < at >< at > acpi_build_srat_memory(struct srat_memory_affinity *numamem,
numamem->length_high = len >> 32;
}
-#define SRAT_SIGNATURE 0x54415253 // SRAT
static void *
build_srat(void)
{
diff --git a/src/acpi.h b/src/acpi.h
index 7fbd082..097cc75 100644
--- a/src/acpi.h
+++ b/src/acpi.h
< at >< at > -113,6 +113,178 < at >< at > struct fadt_descriptor_rev1
#endif
} PACKED;
+struct acpi_table_header /* ACPI common table header */
+{
+ ACPI_TABLE_HEADER_DEF
+} PACKED;
+
+/*
+ * ACPI 1.0 Root System Description Table (RSDT)
+ */
+#define RSDT_SIGNATURE 0x54445352 // RSDT
+struct rsdt_descriptor_rev1
+{
+ ACPI_TABLE_HEADER_DEF /* ACPI common table header */
+ u32 table_offset_entry[0]; /* Array of pointers to other */
+ /* ACPI tables */
+} PACKED;
+
+/*
+ * ACPI 1.0 Firmware ACPI Control Structure (FACS)
+ */
+#define FACS_SIGNATURE 0x53434146 // FACS
+struct facs_descriptor_rev1
+{
+ u32 signature; /* ACPI Signature */
+ u32 length; /* Length of structure, in bytes */
+ u32 hardware_signature; /* Hardware configuration signature */
+ u32 firmware_waking_vector; /* ACPI OS waking vector */
+ u32 global_lock; /* Global Lock */
+ u32 S4bios_f : 1; /* Indicates if S4BIOS support is present */
+ u32 reserved1 : 31; /* Must be 0 */
+ u8 resverved3 [40]; /* Reserved - must be zero */
+} PACKED;
+
+/*
+ * Differentiated System Description Table (DSDT)
+ */
+#define DSDT_SIGNATURE 0x54445344 // DSDT
+
+/*
+ * MADT values and structures
+ */
+
+/* Values for MADT PCATCompat */
+
+#define DUAL_PIC 0
+#define MULTIPLE_APIC 1
+
+/* Master MADT */
+
+#define APIC_SIGNATURE 0x43495041 // APIC
+struct multiple_apic_table
+{
+ ACPI_TABLE_HEADER_DEF /* ACPI common table header */
+ u32 local_apic_address; /* Physical address of local APIC */
+#if 0
+ u32 PCATcompat : 1; /* A one indicates system also has dual 8259s */
+ u32 reserved1 : 31;
+#else
+ u32 flags;
+#endif
+} PACKED;
+
+/* Values for Type in APIC sub-headers */
+
+#define APIC_PROCESSOR 0
+#define APIC_IO 1
+#define APIC_XRUPT_OVERRIDE 2
+#define APIC_NMI 3
+#define APIC_LOCAL_NMI 4
+#define APIC_ADDRESS_OVERRIDE 5
+#define APIC_IO_SAPIC 6
+#define APIC_LOCAL_SAPIC 7
+#define APIC_XRUPT_SOURCE 8
+#define APIC_RESERVED 9 /* 9 and greater are reserved */
+
+/*
+ * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
+ */
+#define ACPI_SUB_HEADER_DEF /* Common ACPI sub-structure header */\
+ u8 type; \
+ u8 length;
+
+/* Sub-structures for MADT */
+
+struct madt_processor_apic
+{
+ ACPI_SUB_HEADER_DEF
+ u8 processor_id; /* ACPI processor id */
+ u8 local_apic_id; /* Processor's local APIC id */
+#if 0
+ u32 processor_enabled: 1; /* Processor is usable if set */
+ u32 reserved2 : 31; /* Reserved, must be zero */
+#else
+ u32 flags;
+#endif
+} PACKED;
+
+struct madt_io_apic
+{
+ ACPI_SUB_HEADER_DEF
+ u8 io_apic_id; /* I/O APIC ID */
+ u8 reserved; /* Reserved - must be zero */
+ u32 address; /* APIC physical address */
+ u32 interrupt; /* Global system interrupt where INTI
+ * lines start */
+} PACKED;
+
+struct madt_intsrcovr {
+ ACPI_SUB_HEADER_DEF
+ u8 bus;
+ u8 source;
+ u32 gsi;
+ u16 flags;
+} PACKED;
+
+struct madt_local_nmi {
+ ACPI_SUB_HEADER_DEF
+ u8 processor_id; /* ACPI processor id */
+ u16 flags; /* MPS INTI flags */
+ u8 lint; /* Local APIC LINT# */
+} PACKED;
+
+/*
+ * HPET Description Table
+ */
+#define HPET_SIGNATURE 0x54455048 // HPET
+struct acpi_20_hpet {
+ ACPI_TABLE_HEADER_DEF /* ACPI common table header */
+ u32 timer_block_id;
+ struct acpi_20_generic_address addr;
+ u8 hpet_number;
+ u16 min_tick;
+ u8 page_protect;
+} PACKED;
+
+/*
+ * SRAT (NUMA topology description) table
+ */
+
+#define SRAT_SIGNATURE 0x54415253 // SRAT
+struct system_resource_affinity_table
+{
+ ACPI_TABLE_HEADER_DEF
+ u32 reserved1;
+ u32 reserved2[2];
+} PACKED;
+
+#define SRAT_PROCESSOR 0
+#define SRAT_MEMORY 1
+
+struct srat_processor_affinity
+{
+ ACPI_SUB_HEADER_DEF
+ u8 proximity_lo;
+ u8 local_apic_id;
+ u32 flags;
+ u8 local_sapic_eid;
+ u8 proximity_hi[3];
+ u32 reserved;
+} PACKED;
+
+struct srat_memory_affinity
+{
+ ACPI_SUB_HEADER_DEF
+ u8 proximity[4];
+ u16 reserved1;
+ u32 base_addr_low,base_addr_high;
+ u32 length_low,length_high;
+ u32 reserved2;
+ u32 flags;
+ u32 reserved3[2];
+} PACKED;
+
/* PCI fw r3.0 MCFG table. */
/* Subtable */
struct acpi_mcfg_allocation {
</pre>
Kevin O'Connor
2013-03-30T15:50:18
-
[PATCH] Use container_of on romfile entries.
http://comments.gmane.org/gmane.comp.bios.coreboot.seabios/6072
<pre>Create cbfs and fw_cfg specific romfile_s wrappers instead of using
private variables directly in romfile_s.
Signed-off-by: Kevin O'Connor <kevin< at >koconnor.net>
---
src/coreboot.c | 67 ++++++++++++++++++++++++++++++++++------------------------
src/paravirt.c | 29 +++++++++++++++----------
src/util.h | 5 -----
3 files changed, 57 insertions(+), 44 deletions(-)
diff --git a/src/coreboot.c b/src/coreboot.c
index c9ad2a8..120bc2e 100644
--- a/src/coreboot.c
+++ b/src/coreboot.c
< at >< at > -286,6 +286,13 < at >< at > struct cbfs_file {
char filename[0];
} PACKED;
+struct cbfs_romfile_s {
+ struct romfile_s file;
+ struct cbfs_file *fhdr;
+ void *data;
+ u32 rawsize, flags;
+};
+
// Copy a file to memory (uncompressing if necessary)
static int
cbfs_copyfile(struct romfile_s *file, void *dst, u32 maxlen)
< at >< at > -293,9 +300,11 < at >< at > cbfs_copyfile(struct romfile_s *file, void *dst, u32 maxlen)
if (!CONFIG_COREBOOT_FLASH)
return -1;
- u32 size = file->rawsize;
- void *src = file->data;
- if (file->flags) {
+ struct cbfs_romfile_s *cfile;
+ cfile = container_of(file, struct cbfs_romfile_s, file);
+ u32 size = cfile->rawsize;
+ void *src = cfile->data;
+ if (cfile->flags) {
// Compressed - copy to temp ram and uncompress it.
void *temp = malloc_tmphigh(size);
if (!temp) {
< at >< at > -333,35 +342,36 < at >< at > coreboot_cbfs_init(void)
}
dprintf(1, "Found CBFS header at %p\n", hdr);
- struct cbfs_file *cfile = (void *)(0 - be32_to_cpu(hdr->romsize)
- + be32_to_cpu(hdr->offset));
+ struct cbfs_file *fhdr = (void *)(0 - be32_to_cpu(hdr->romsize)
+ + be32_to_cpu(hdr->offset));
for (;;) {
- if (cfile < (struct cbfs_file *)(0xFFFFFFFF - be32_to_cpu(hdr->romsize)))
+ if (fhdr < (struct cbfs_file *)(0xFFFFFFFF - be32_to_cpu(hdr->romsize)))
break;
- u64 magic = cfile->magic;
+ u64 magic = fhdr->magic;
if (magic != CBFS_FILE_MAGIC)
break;
- struct romfile_s *file = malloc_tmp(sizeof(*file));
- if (!file) {
+ struct cbfs_romfile_s *cfile = malloc_tmp(sizeof(*cfile));
+ if (!cfile) {
warn_noalloc();
break;
}
- memset(file, 0, sizeof(*file));
- strtcpy(file->name, cfile->filename, sizeof(file->name));
- file->size = file->rawsize = be32_to_cpu(cfile->len);
- file->id = (u32)cfile;
- file->copy = cbfs_copyfile;
- file->data = (void*)cfile + be32_to_cpu(cfile->offset);
- int len = strlen(file->name);
- if (len > 5 && strcmp(&file->name[len-5], ".lzma") == 0) {
+ memset(cfile, 0, sizeof(*cfile));
+ strtcpy(cfile->file.name, fhdr->filename, sizeof(cfile->file.name));
+ cfile->file.size = cfile->rawsize = be32_to_cpu(fhdr->len);
+ cfile->fhdr = fhdr;
+ cfile->file.copy = cbfs_copyfile;
+ cfile->data = (void*)fhdr + be32_to_cpu(fhdr->offset);
+ int len = strlen(cfile->file.name);
+ if (len > 5 && strcmp(&cfile->file.name[len-5], ".lzma") == 0) {
// Using compression.
- file->flags = 1;
- file->name[len-5] = '\0';
- file->size = *(u32*)(file->data + LZMA_PROPERTIES_SIZE);
+ cfile->flags = 1;
+ cfile->file.name[len-5] = '\0';
+ cfile->file.size = *(u32*)(cfile->data + LZMA_PROPERTIES_SIZE);
}
- romfile_add(file);
+ romfile_add(&cfile->file);
- cfile = (void*)ALIGN((u32)file->data + file->size, be32_to_cpu(hdr->align));
+ fhdr = (void*)ALIGN((u32)cfile->data + cfile->file.size
+ , be32_to_cpu(hdr->align));
}
}
< at >< at > -385,12 +395,12 < at >< at > struct cbfs_payload {
};
void
-cbfs_run_payload(struct cbfs_file *file)
+cbfs_run_payload(struct cbfs_file *fhdr)
{
- if (!CONFIG_COREBOOT_FLASH || !file)
+ if (!CONFIG_COREBOOT_FLASH || !fhdr)
return;
- dprintf(1, "Run %s\n", file->filename);
- struct cbfs_payload *pay = (void*)file + be32_to_cpu(file->offset);
+ dprintf(1, "Run %s\n", fhdr->filename);
+ struct cbfs_payload *pay = (void*)fhdr + be32_to_cpu(fhdr->offset);
struct cbfs_payload_segment *seg = pay->segments;
for (;;) {
void *src = (void*)pay + be32_to_cpu(seg->offset);
< at >< at > -445,9 +455,10 < at >< at > cbfs_payload_setup(void)
file = romfile_findprefix("img/", file);
if (!file)
break;
+ struct cbfs_romfile_s *cfile;
+ cfile = container_of(file, struct cbfs_romfile_s, file);
const char *filename = file->name;
char *desc = znprintf(MAXDESCSIZE, "Payload [%s]", &filename[4]);
- boot_add_cbfs((void*)file->id, desc
- , bootprio_find_named_rom(filename, 0));
+ boot_add_cbfs(cfile->fhdr, desc, bootprio_find_named_rom(filename, 0));
}
}
diff --git a/src/paravirt.c b/src/paravirt.c
index ee6a86e..e5027d0 100644
--- a/src/paravirt.c
+++ b/src/paravirt.c
< at >< at > -166,13 +166,20 < at >< at > qemu_cfg_read_entry(void *buf, int e, int len)
qemu_cfg_read(buf, len);
}
+struct qemu_romfile_s {
+ struct romfile_s file;
+ int select, skip;
+};
+
static int
qemu_cfg_read_file(struct romfile_s *file, void *dst, u32 maxlen)
{
if (file->size > maxlen)
return -1;
- qemu_cfg_select(file->id);
- qemu_cfg_skip(file->rawsize);
+ struct qemu_romfile_s *qfile;
+ qfile = container_of(file, struct qemu_romfile_s, file);
+ qemu_cfg_select(qfile->select);
+ qemu_cfg_skip(qfile->skip);
qemu_cfg_read(dst, file->size);
return file->size;
}
< at >< at > -180,18 +187,18 < at >< at > qemu_cfg_read_file(struct romfile_s *file, void *dst, u32 maxlen)
static void
qemu_romfile_add(char *name, int select, int skip, int size)
{
- struct romfile_s *file = malloc_tmp(sizeof(*file));
- if (!file) {
+ struct qemu_romfile_s *qfile = malloc_tmp(sizeof(*qfile));
+ if (!qfile) {
warn_noalloc();
return;
}
- memset(file, 0, sizeof(*file));
- strtcpy(file->name, name, sizeof(file->name));
- file->id = select;
- file->rawsize = skip; // Use rawsize to indicate skip length.
- file->size = size;
- file->copy = qemu_cfg_read_file;
- romfile_add(file);
+ memset(qfile, 0, sizeof(*qfile));
+ strtcpy(qfile->file.name, name, sizeof(qfile->file.name));
+ qfile->file.size = size;
+ qfile->select = select;
+ qfile->skip = skip;
+ qfile->file.copy = qemu_cfg_read_file;
+ romfile_add(&qfile->file);
}
struct e820_reservation {
diff --git a/src/util.h b/src/util.h
index 99aff78..996c29a 100644
--- a/src/util.h
+++ b/src/util.h
< at >< at > -436,11 +436,6 < at >< at > struct romfile_s {
char name[128];
u32 size;
int (*copy)(struct romfile_s *file, void *dest, u32 maxlen);
-
- u32 id;
- u32 rawsize;
- u32 flags;
- void *data;
};
void romfile_add(struct romfile_s *file);
struct romfile_s *romfile_findprefix(const char *prefix, struct romfile_s *prev);
</pre>
Kevin O'Connor
2013-03-30T15:46:53
-
[Fwd: Re: [PATCH V3 WIP 3/3] disable vhost_verify_ring_mappings check]
http://comments.gmane.org/gmane.comp.bios.coreboot.seabios/6051
<pre>Forwarding to Kevin + seabios for their comments..
Thanks,
--nab
_______________________________________________
SeaBIOS mailing list
SeaBIOS< at >seabios.org
http://www.seabios.org/mailman/listinfo/seabios
</pre>
Nicholas A. Bellinger
2013-03-28T06:56:52
-
[PATCH] Cleanup QEMU_CFG_NUMA fw_cfg processing - split into two romfile entries.
http://comments.gmane.org/gmane.comp.bios.coreboot.seabios/6023
<pre>The QEMU_CFG_NUMA fw_cfg entry is actually two separate tables in one
fw_cfg entry - a table for cpu affinity and a table for the memory
map. Create two romfile entries to make that more clear.
Signed-off-by: Kevin O'Connor <kevin< at >koconnor.net>
---
src/acpi.c | 25 ++++++++++++++-----------
src/paravirt.c | 7 +++++--
2 files changed, 19 insertions(+), 13 deletions(-)
diff --git a/src/acpi.c b/src/acpi.c
index bc4d8ea..55c7259 100644
--- a/src/acpi.c
+++ b/src/acpi.c
< at >< at > -646,14 +646,13 < at >< at > acpi_build_srat_memory(struct srat_memory_affinity *numamem,
static void *
build_srat(void)
{
- int filesize;
- u64 *numadata = romfile_loadfile("etc/numa-nodes", &filesize);
- if (!numadata)
- return NULL;
- int max_cpu = romfile_loadint("etc/max-cpus", 0);
- int nb_numa_nodes = (filesize / sizeof(u64)) - max_cpu;
- if (!nb_numa_nodes)
- return NULL;
+ int numadatasize, numacpusize;
+ u64 *numadata = romfile_loadfile("etc/numa-nodes", &numadatasize);
+ u64 *numacpumap = romfile_loadfile("etc/numa-cpu-map", &numacpusize);
+ if (!numadata || !numacpumap)
+ goto fail;
+ int max_cpu = numacpusize / sizeof(u64);
+ int nb_numa_nodes = numadatasize / sizeof(u64);
struct system_resource_affinity_table *srat;
int srat_size = sizeof(*srat) +
< at >< at > -663,8 +662,7 < at >< at > build_srat(void)
srat = malloc_high(srat_size);
if (!srat) {
warn_noalloc();
- free(numadata);
- return NULL;
+ goto fail;
}
memset(srat, 0, srat_size);
< at >< at > -677,7 +675,7 < at >< at > build_srat(void)
core->type = SRAT_PROCESSOR;
core->length = sizeof(*core);
core->local_apic_id = i;
- curnode = *numadata++;
+ curnode = *numacpumap++;
core->proximity_lo = curnode;
memset(core->proximity_hi, 0, 3);
core->local_sapic_eid = 0;
< at >< at > -731,7 +729,12 < at >< at > build_srat(void)
build_header((void*)srat, SRAT_SIGNATURE, srat_size, 1);
free(numadata);
+ free(numacpumap);
return srat;
+fail:
+ free(numadata);
+ free(numacpumap);
+ return NULL;
}
static void *
diff --git a/src/paravirt.c b/src/paravirt.c
index 4a26c6e..ee6a86e 100644
--- a/src/paravirt.c
+++ b/src/paravirt.c
< at >< at > -223,8 +223,11 < at >< at > qemu_cfg_legacy(void)
// NUMA data
u64 numacount;
qemu_cfg_read_entry(&numacount, QEMU_CFG_NUMA, sizeof(numacount));
- numacount += romfile_loadint("etc/max-cpus", 0);
- qemu_romfile_add("etc/numa-nodes", QEMU_CFG_NUMA, sizeof(numacount)
+ int max_cpu = romfile_loadint("etc/max-cpus", 0);
+ qemu_romfile_add("etc/numa-cpu-map", QEMU_CFG_NUMA, sizeof(numacount)
+ , max_cpu*sizeof(u64));
+ qemu_romfile_add("etc/numa-nodes", QEMU_CFG_NUMA
+ , sizeof(numacount) + max_cpu*sizeof(u64)
, numacount*sizeof(u64));
// e820 data
</pre>
Kevin O'Connor
2013-03-23T15:47:42
-
[PATCH] README: document which config options to use
http://comments.gmane.org/gmane.comp.bios.coreboot.seabios/5989
<pre>In the interim of moving ACPI tables out of
seabios, developers should get the config from
QEMU tree to keep things in sync.
Signed-off-by: Michael S. Tsirkin <mst< at >redhat.com>
---
README | 16 ++++++++++++++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/README b/README
index a87a0ad..c6a2ee4 100644
--- a/README
+++ b/README
< at >< at > -1,9 +1,21 < at >< at >
This code implements an X86 legacy bios. It is intended to be
compiled using standard gnu tools (eg, gas and gcc).
-To build, one should be able to run "make" in the main directory. The
-resulting file "out/bios.bin" contains the processed bios image.
+To build, one should be able to run "make" in the main directory.
+QEMU might only need a part of the BIOS binary, and different QEMU versions
+might need different seabios configurations to work well. To build
+a bios for qemu, one needs to copy the config file from qemu source tree:
+
+cp $QEMU_DIR/roms/config.seabios $SEABIOS_DIR/.config
+
+(where $QEMU_DIR is the qemu source directory, $SEABIOS_DIR points to the
+seabios build directory); and then run make in the seabios main directory with
+this configuration:
+
+make olddefconfig
+
+The resulting file "out/bios.bin" contains the processed bios image.
Testing of images:
</pre>
Michael S. Tsirkin
2013-03-21T12:30:02
-
[PATCH] README: document which config options to use
http://comments.gmane.org/gmane.comp.bios.coreboot.seabios/5986
<pre>In the interim of moving ACPI tables out of
seabios, developers should get the config from
QEMU tree to keep things in sync.
Signed-off-by: Michael S. Tsirkin <mst< at >redhat.com>
---
README | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/README b/README
index a87a0ad..380fc80 100644
--- a/README
+++ b/README
< at >< at > -4,6 +4,12 < at >< at > compiled using standard gnu tools (eg, gas and gcc).
To build, one should be able to run "make" in the main directory. The
resulting file "out/bios.bin" contains the processed bios image.
+QEMU might only need a part of the BIOS binary, and different QEMU versions
+might need different seabios configurations to work well. To build
+a bios for qemu, one needs to copy the config file from qemu source tree:
+cp roms/config.seabios seabios/.config
+and then run make with this configuration:
+make -C seabios olddefconfig
Testing of images:
</pre>
Michael S. Tsirkin
2013-03-21T12:03:02
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