gmane.linux.ports.ppc64.devel

Re: [PATCH v1 0/2] powerpc/mpc512x: improve common platform code

Anatolij Gustschin — 2013-05-21T09:14:08

Hi Gerhard,

On Tue, 14 May 2013 16:40:52 +0200
Gerhard Sittig <gsi< at >denx.de> wrote:
...

Applied both patches for -next. Thanks!

Anatolij

Re: [PATCH] PowerPC: kernel: need return the related error code when failure occurs.

Paul Mackerras — 2013-05-21T08:10:31

Why?  When *ppos >= size, it should return 0 (end of file) in my opinion.
ESPIPE means that any seek would be ineffective, not that a particular
seek went out of bounds.

Paul.

[PATCH] PowerPC: kernel: need return the related error code when failure occurs.

Chen Gang — 2013-05-21T05:48:58

When error occurs, need return the related error code to let upper
caller know about it.

ppc_md.nvram_size() can return the error code (e.g. core99_nvram_size()
in 'arch/powerpc/platforms/powermac/nvram.c').

And when '*ppos >= size', need return -ESPIPE (Illegal seek)

The original related patch: "f9ce299 [PATCH] powerpc: fix large nvram
access"


Signed-off-by: Chen Gang <gang.chen< at >asianux.com>
---
 arch/powerpc/kernel/nvram_64.c |    9 +++++++--
 1 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/kernel/nvram_64.c b/arch/powerpc/kernel/nvram_64.c
index 48fbc2b..db2a636 100644
--- a/arch/powerpc/kernel/nvram_64.c
+++ b/arch/powerpc/kernel/nvram_64.c
< at >< at > -88,10 +88,15 < at >< at > static ssize_t dev_nvram_read(struct file *file, char __user *buf,
 if (!ppc_md.nvram_size)
 goto out;
 
-ret = 0;
 size = ppc_md.nvram_size();
-if (*ppos >= size || size < 0)
+if (size < 0) {
+ret = size;
 goto out;
+}
+if (*ppos >= size) {
+ret = -ESPIPE;
+goto out;
+}
 
 count = min_t(size_t,

Re: [PATCH 3/3] perf, x86, lbr: Demand proper privileges for PERF_SAMPLE_BRANCH_KERNEL

Michael Neuling — 2013-05-21T05:41:35


Peter,

Can we add your signed-off-by on this?

We are cleaning up our series for conditional branches and would like to
add this as part of the post.

Mikey

[PATCH] powerpc/powernv: Add an option to wipe PCI bridges on shutdown

Benjamin Herrenschmidt — 2013-05-21T04:58:47

Older kernels such as 3.6 used by Fedora 18 have a problem with
the way more recent kernels configure the PCI bridge windows due
to my crappy old resource allocation code (we now use the generic
code which is way better).

In order to be able to safely kexec into those earlier kernels
(which we may need to do in some circumstances to launch distro
installers), we need to cleanup the bridges to avoid tripping
that bug.

This adds an option to do that, which is expected to be enabled
on kernels used as kexec-based bootloaders.

Signed-off-by: Benjamin Herrenschmidt <benh< at >kernel.crashing.org>
---
 arch/powerpc/platforms/powernv/Kconfig    |    5 ++++
 arch/powerpc/platforms/powernv/pci-ioda.c |   42 +++++++++++++++++++++++++++++
 2 files changed, 47 insertions(+)

diff --git a/arch/powerpc/platforms/powernv/Kconfig b/arch/powerpc/platforms/powernv/Kconfig
index d3e840d..91bec0e 100644
--- a/arch/powerpc/platforms/powernv/Kconfig
+++ b/arch/powerpc/platforms/powernv/Kconfig
< at >< at > -19,3 +19,8 < at >< at > config PPC_POWERNV_R

[PATCH] powerpc/powernv: Fix condition for when to invalidate the TCE cache

Benjamin Herrenschmidt — 2013-05-21T03:25:15

We use two flags, one to indicate an invalidation is needed after
creating a new entry and one to indicate an invalidation is needed
after removing an entry. However we were testing the wrong flag
in the remove case.

Signed-off-by: Benjamin Herrenschmidt <benh< at >kernel.crashing.org>
---
 arch/powerpc/platforms/powernv/pci.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/powerpc/platforms/powernv/pci.c b/arch/powerpc/platforms/powernv/pci.c
index 163bd74..098d357 100644
--- a/arch/powerpc/platforms/powernv/pci.c
+++ b/arch/powerpc/platforms/powernv/pci.c
< at >< at > -367,7 +367,7 < at >< at > static void pnv_tce_free(struct iommu_table *tbl, long index, long npages)
 while (npages--)
 *(tcep++) = 0;
 
-if (tbl->it_type & TCE_PCI_SWINV_CREATE)
+if (tbl->it_type & TCE_PCI_SWINV_FREE)
 pnv_pci_ioda_tce_invalidate(tbl, tces, tcep - 1);
 }

[PATCH] powerpc/pci: Fix bogus message at boot about empty memory resources

Benjamin Herrenschmidt — 2013-05-21T03:24:39

The message is only meant to be displayed if resource 0 is empty,
but was displayed if any is.

Signed-off-by: Benjamin Herrenschmidt <benh< at >kernel.crashing.org>
---
 arch/powerpc/kernel/pci-common.c |    7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c
index 6053f03..e9acf50 100644
--- a/arch/powerpc/kernel/pci-common.c
+++ b/arch/powerpc/kernel/pci-common.c
< at >< at > -1520,9 +1520,10 < at >< at > static void pcibios_setup_phb_resources(struct pci_controller *hose,
 for (i = 0; i < 3; ++i) {
 res = &hose->mem_resources[i];
 if (!res->flags) {
-printk(KERN_ERR "PCI: Memory resource 0 not set for "
-       "host bridge %s (domain %d)\n",
-       hose->dn->full_name, hose->global_number);
+if (i == 0)
+printk(KERN_ERR "PCI: Memory resource 0 not set for "
+       "host bridge %s (domain %d)\n",
+       hose->dn->full_name, hose->global_number);
 continue;
 }
 offset = hose->mem_offset[i];

[PATCH] powerpc: Fix TLB cleanup at boot on POWER8

Benjamin Herrenschmidt — 2013-05-21T03:23:22

The TLB has 512 congruence classes (2048 entries 4 way set associative)
while P7 had 128

Signed-off-by: Benjamin Herrenschmidt <benh< at >kernel.crashing.org>
---
 arch/powerpc/kernel/cpu_setup_power.S |    8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S
index a283b64..18b5b9c 100644
--- a/arch/powerpc/kernel/cpu_setup_power.S
+++ b/arch/powerpc/kernel/cpu_setup_power.S
< at >< at > -135,8 +135,12 < at >< at > __init_HFSCR:
 blr
 
 __init_TLB:
-/* Clear the TLB */
-lir6,128
+/*
+ * Clear the TLB using the "IS 3" form of tlbiel instruction
+ * (invalidate by congruence class). P7 has 128 CCs, P8 has 512
+ * so we just always do 512
+ */
+lir6,512
 mtctrr6
 lir7,0xc00/* IS field = 0b11 */
 ptesync

[PATCH 0/4 v2] KVM: PPC: IOMMU in-kernel handling

Alexey Kardashevskiy — 2013-05-21T03:06:43

This accelerates IOMMU operations in real and virtual
mode in the host kernel for the KVM guest.

The first patch with multitce support is useful for emulated devices as is.

The other patches are designed for VFIO although this series
does not contain any VFIO related code as the connection between
VFIO and the new handlers is to be made in QEMU
via ioctl to the KVM fd.

The series was made and tested against v3.10-rc1.


Alexey Kardashevskiy (4):
  KVM: PPC: Add support for multiple-TCE hcalls
  powerpc: Prepare to support kernel handling of IOMMU map/unmap
  KVM: PPC: Add support for IOMMU in-kernel handling
  KVM: PPC: Add hugepage support for IOMMU in-kernel handling

 Documentation/virtual/kvm/api.txt        |   42 +++
 arch/powerpc/include/asm/kvm_host.h      |    7 +
 arch/powerpc/include/asm/kvm_ppc.h       |   40 ++-
 arch/powerpc/include/asm/pgtable-ppc64.h |    4 +
 arch/powerpc/include/uapi/asm/kvm.h      |    7 +
 arch/powerpc/kvm/book3s_64_vio.c         |  398 ++++++++++++++++++++++++-
 arch/p

RE: [PATCH 2/2 V8] powerpc/85xx: Add machine check handler to fix PCIe erratum on mpc85xx

Jia Hongtao-B38951 — 2013-05-21T02:07:52

Hi Ben and Kumar,

I'm really appreciate if you could help me to review this patches
for these patches were pending nearly a month.

Thanks.
-Hongtao

[PATCH v2] powerpc/tm: Abort transactions on emulation and alignment faults

Michael Neuling — 2013-05-21T01:48:05

If we are emulating an instruction inside an active user transaction that
touches memory, the kernel can't emulate it as it operates in transactional
suspend context.  We need to abort these transactions and send them back to
userspace for the hardware to rollback.

We can service these if the user transaction is in suspend mode, since the
kernel will operate in the same suspend context.

This adds a check to all alignment faults and to specific instruction
emulations (only string instructions for now).  If the user process is in an
active (non-suspended) transaction, we abort the transaction go back to
userspace allowing the HW to roll back the transaction and tell the user of the
failure.  This also adds new tm abort cause codes to report the reason of the
persistent error to the user.

Crappy test case here http://neuling.org/devel/junkcode/aligntm.c

Signed-off-by: Michael Neuling <mikey< at >neuling.org>
Cc: <stable< at >vger.kernel.org> # v3.9 only
---
v2:
  Split persistent bit of cause into separate bit
  Mark

Re: [PATCH v2 2/4] powerpc/cputable: advertise DSCR support on P7/P7+

Michael Neuling — 2013-05-20T23:41:45


Nice catch.  Thanks

Acked-by: Michael Neuling <mikey< at >neuling.org>

Build failure with 3.9.3 (Regression 3.9.2->3.9.3)

Adam Lackorzynski — 2013-05-20T15:14:11

Hi,

3.9.3 introduced the following build failure:

  CC      arch/powerpc/kernel/rtas.o
arch/powerpc/kernel/rtas.c: In function ‘rtas_cpu_state_change_mask’:
arch/powerpc/kernel/rtas.c:843:4: error: implicit declaration of function ‘cpu_down’ [-Werror=implicit-function-declaration]
cc1: all warnings being treated as errors
make[1]: *** [arch/powerpc/kernel/rtas.o] Error 1
make: *** [arch/powerpc/kernel] Error 2

My kernel config has CONFIG_HOTPLUG_CPU off, that's why cpu_down is not
defined. Shall CONFIG_HOTPLUG_CPU just be enabled or should the code in
rtas.c be adapted?


Thanks,
Adam

Re: [PATCH v2 2/4] powerpc/cputable: advertise DSCR support on P7/P7+

Will Schmidt — 2013-05-20T15:04:18

^ Oops here, I think.    Please consider applying this on top.
Untested, but seems obvious.

Fix a typo in setting COMMON_USER2_POWER7 bits to .cpu_user_features2
cpu specs table.

Signed-off-by: Will Schmidt <will_schmidt< at >vnet.ibm.com>


diff --git a/arch/powerpc/kernel/cputable.c
b/arch/powerpc/kernel/cputable.c
index c60bbec..51eecb5 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
< at >< at > -482,7 +482,7 < at >< at > static struct cpu_spec __initdata cpu_specs[] = {
                .cpu_name               = "POWER7+ (raw)",
                .cpu_features           = CPU_FTRS_POWER7,
                .cpu_user_features      = COMMON_USER_POWER7,
-               .cpu_user_features      = COMMON_USER2_POWER7,
+               .cpu_user_features2     = COMMON_USER2_POWER7,
                .mmu_features           = MMU_FTRS_POWER7,
                .icache_bsize           = 128,
                .dcache_bsize           = 128,

[PATCH] powerpc/tm: Abort transactions on emulation and alignment faults

Michael Neuling — 2013-05-20T11:07:54

If we are emulating an instruction inside an active user transaction that
touches memory, the kernel can't emulate it as it operates in transactional
suspend context.  We need to abort these transactions and send them back to
userspace for the hardware to rollback.

We can service these if the user transaction is in suspend mode, since the
kernel will operate in the same suspend context.

This adds a check to all alignment faults and to specific instruction
emulations (only string instructions for now).  If the user process is in an
active (non-suspended) transaction, we abort the transaction go back to
userspace allowing the HW to roll back the transaction and tell the user of the
failure.  This also adds new tm abort cause codes to report the reason of the
persistent error to the user.

Crappy test case here http://neuling.org/devel/junkcode/aligntm.c

Signed-off-by: Michael Neuling <mikey< at >neuling.org>

diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index a613651..2f20a40 1006

Re: [PATCH 1/2] powerpc: use smp_rmb when looking at deposisted pgtable to store hash index

Aneesh Kumar K.V — 2013-05-20T09:26:18


Will update the commit message. Some of that smb_wmb() are in the
core THP, and the others in ppc64 code. Will update with more info.

When we deposit pgtable we use pgtable_trans_huge_deposit that calls
related smb_wmb(). When we read pgtable via pgtable_trans_huge_withdraw,
core THP code does the related smb_wmb() after setting the right
PTE information in the pgtable.

-aneesh

Re: [PATCH 1/2] powerpc: use smp_rmb when looking at deposisted pgtable to store hash index

Benjamin Herrenschmidt — 2013-05-20T06:28:38

Note that any patch that adds such a rmb should have a very clear
description of what is the corresponding wmb. It's almost never right to
have one without the other. IE. What is it that you are ordering
against.

Cheers,
Ben.

Re: [PATCH 1/2] powerpc: use smp_rmb when looking at deposisted pgtable to store hash index

Aneesh Kumar K.V — 2013-05-20T04:27:38


No the changes are not yet upstream. hpte_slot_array changes are in the
THP series. I didn't want to post the entire series again with the 
above two patches. 

-aneesh

Re: [PATCH 1/2] powerpc: use smp_rmb when looking at deposisted pgtable to store hash index

Michael Neuling — 2013-05-20T01:18:46


Does this need to go back into the stable series?

Mikey

Re: [PATCH 3/3] perf, x86, lbr: Demand proper privileges for PERF_SAMPLE_BRANCH_KERNEL

Michael Neuling — 2013-05-17T22:14:52


OK.  I don't have a good handle on what's useful for compilers or JITs
right now.  I'm just plumbing through what's possible.

Mikey

Re: [PATCH] powerpc/cell: Only iterate over online nodes in cbe_init_pm_irq()

Dennis Schridde — 2013-05-17T15:45:05

Hello!

Just wanted to remind you: The patchto fix cbe_init_pm_irq() that Michael and 
Grant sent me is still not included in Linux 3.8.12.

--Dennis

Am Dienstag, 23. April 2013, 22:14:51 schrieb Michael Ellerman:
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