http://permalink.gmane.org/gmane.linux.kernel.samsung-soc hourly 1 1901-01-01T00:00+00:00 http://gmane.org/img/gmane-25t.png http://gmane.org http://permalink.gmane.org/gmane.linux.kernel.samsung-soc/19761 <pre>Thanks Kukjin. I will address the comments and resend. -- with warm regards, Chander Kashyap </pre> Chander Kashyap 2013-06-18T04:28:08 http://permalink.gmane.org/gmane.linux.kernel.samsung-soc/19759 <pre>This is the max cpu frequency. This property is used in "parse_dt_topology" in arch/arm/kernel/topology.c" to calculate cpu capacity. -- with warm regards, Chander Kashyap </pre> Chander Kashyap 2013-06-18T04:21:14 http://permalink.gmane.org/gmane.linux.kernel.samsung-soc/19758 <pre>I have listed the parent clock first, then the child clocks, to maintain readability. I didn't get your point? Thanks. -- with warm regards, Chander Kashyap </pre> Chander Kashyap 2013-06-18T04:09:00 http://permalink.gmane.org/gmane.linux.kernel.samsung-soc/19757 <pre>Thanks for pointing out. I will fix it and resend. -- with warm regards, Chander Kashyap </pre> Chander Kashyap 2013-06-18T04:11:33 http://permalink.gmane.org/gmane.linux.kernel.samsung-soc/19756 <pre>I am not adding new hard-coded address. I have simply removed the unnecessary previously existing check. Thanks. -- with warm regards, Chander Kashyap </pre> Chander Kashyap 2013-06-18T04:10:51 http://permalink.gmane.org/gmane.linux.kernel.samsung-soc/19754 <pre> Looks good. You want it to get via samsung tree or cpufreq? I think all cpufreq related patches should go through cpufreq unless there is a real dependency on samsung tree. </pre> Viresh Kumar 2013-06-18T03:18:41 http://permalink.gmane.org/gmane.linux.kernel.samsung-soc/19752 <pre> Loan Syndicacion Am AFG Guaranty Trust Bank, zu strukturieren wir Kreditlinien treffen Sie unsere Kunden spezifischen geschäftlichen Anforderungen und einen deutlichen Mehrwert für unsere Kunden Unternehmen. eine Division der AFG Finance und Private Bank plc. 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Als Bank mit internationaler Reichweite, sind wir gekommen, um Darlehen zu identifizieren Syndizierungen als Teil unseres Kerngeschäfts und durch spitzte diese Zeile aggressiv sind wir an einem Punkt, wo wir kommen, um als erkannt haben Hauptakteur in diesem Bereich. öffnen Sie ein Girokonto heute mit einem Minimum Bankguthaben von 500 £ und Getup zu £ 10.000 als Darlehen und auch den Hauch einer Chance und gewann die Sterne Preis von £ 500.000 in die sparen und gewinnen promo in may.aply jetzt. mit dem Folowin</pre> AFG GTBANK LOAN 2013-06-17T19:28:00 http://permalink.gmane.org/gmane.linux.kernel.samsung-soc/19751 <pre>Applied, thanks. - Kukjin </pre> Kukjin Kim 2013-06-17T21:59:22 http://permalink.gmane.org/gmane.linux.kernel.samsung-soc/19750 <pre>Hi Thierry, On Monday 17 of June 2013 22:29:11 Thierry Reding wrote: OK. OK. OK, this should be better indeed. OK. There are few registers shared with samsung_pwm_timer clocksource driver and so normally the spinlock is exported from it. However on on some platforms (namely Exynos &gt;=4x12) kernel can be compiled without that driver, so the lock must be defined locally, just to synchronize multiple PWM channels, as they share registers as well. OK. Nope. Fixed in v2 that I'm going to send soon. OK. I have almost completely reworked this function in v2 and it needs just 5 variables here. Sure. OK. polarity) Hmm, might make sense to put this into a function indeed. Basically this is a trick to work around broken bit layout in TCON register. OK. val) samsung,pwm-outputs __func__); Let me see what I can do about it. OK. specified\n"); Generally output_mask is board-dependent and is passed inside a variant struct using platform_data pointer. Same platform data is used in samsun</pre> Tomasz Figa 2013-06-17T20:50:40 http://permalink.gmane.org/gmane.linux.kernel.samsung-soc/19749 <pre> Sorry for jumping in so late, I've been busy with other things lately. Nit: this line can be dropped. It serves no purpose. Nit: the */ should align with the * above. The new driver for Renesas did something similar, but I want to discourage storing per-channel data within the chip structure. The PWM framework provides a way to store this information along with the PWM device (see pwm_{set,get}_chip_data()). Can you turn this into a static inline function please? Why is this lock global? Shouldn't it more correctly be part of samsung_pwm_chip? Nit: please align arguments on subsequent lines with the first argument of the first line. There's many more of these but I haven't mentioned them all explicitly. Any particular reason for making this inline? Many of these unsigned long variable could be declared on a single line to make the function shorter. Can you turn these into proper block-style comments? Like so: /* * We currently... * ... * by 32 bits. */ Note that technically yo</pre> Thierry Reding 2013-06-17T20:29:11 http://permalink.gmane.org/gmane.linux.kernel.samsung-soc/19748 <pre> I believe the UM says that 64 &lt;= m &lt;= 511. Although the above seems to work on 5250 and 5420, it might be better to use a table that conforms to the constraint on m: PLL_36XX_RATE(192000000, 64, 2, 2, 0), PLL_36XX_RATE(180633600, 90, 3, 2, 20762), PLL_36XX_RATE(180000000, 90, 3, 2, 0), PLL_36XX_RATE(73728000, 98, 2, 4, 19923), PLL_36XX_RATE(67737600, 90, 2, 4, 20762), PLL_36XX_RATE(49152000, 98, 3, 4, 19923), PLL_36XX_RATE(45158400, 90, 3, 4, 20762), PLL_36XX_RATE(32768000, 131, 3, 5, 4719) Thanks, Andrew </pre> Andrew Bresticker 2013-06-17T20:08:13 http://permalink.gmane.org/gmane.linux.kernel.samsung-soc/19746 <pre> The patch is correct, but generally speaking I think we should get away from having the drivers get configured per SoC on such a fine-grained level. Better make this driver (and others) always work on all exynos variants. Arnd </pre> Arnd Bergmann 2013-06-17T19:59:15 http://permalink.gmane.org/gmane.linux.kernel.samsung-soc/19742 <pre> OK. Let me do it this way and see how it turns out. However keep in mind that next patch adds further dependencies on access to vendor_data struct, so there is nothing sure. Best regards, Tomasz </pre> Tomasz Figa 2013-06-17T19:02:26 http://permalink.gmane.org/gmane.linux.kernel.samsung-soc/19740 <pre> Spot the unfixed up merge error... </pre> Russell King - ARM Linux 2013-06-17T18:56:18 http://permalink.gmane.org/gmane.linux.kernel.samsung-soc/19739 <pre> It isn't anything important. I just thought that this is a better solution to store more than just two flags. Initially I had more of them added in further patches, but final version ended with just one, so this can be dropped. Best regards, Tomasz </pre> Tomasz Figa 2013-06-17T18:56:06 http://permalink.gmane.org/gmane.linux.kernel.samsung-soc/19737 <pre> I'd suggest doing this a different way. Instead of having to pass around two pointers everywhere in order to access this register, add to struct pl08x_phy_chan a void __iomem *reg_config; member, and initialize that to base + vd-&gt;config_offset. Then use ch-&gt;reg_cfg instead of ch-&gt;base + PL080_CH_CONFIG. This has the benefit that you won't have to modify a whole load of functions to pass another argument, which costs not only an additional register, but also storage to keep it around. </pre> Russell King - ARM Linux 2013-06-17T18:52:23 http://permalink.gmane.org/gmane.linux.kernel.samsung-soc/19736 <pre> Please explain why this is better over the existing system, and why it is not just churn for code modification's sake. </pre> Russell King - ARM Linux 2013-06-17T18:48:56 http://permalink.gmane.org/gmane.linux.kernel.samsung-soc/19731 <pre>This patch defines a common rate_table which will contain recommended p, m, s, k values for supported rates that needs to be changed for changing corresponding PLL's rate. Reviewed-by: Doug Anderson &lt;dianders&lt; at &gt;chromium.org&gt; Signed-off-by: Yadwinder Singh Brar &lt;yadi.brar&lt; at &gt;samsung.com&gt; --- drivers/clk/samsung/clk-exynos4.c | 8 ++++---- drivers/clk/samsung/clk-exynos5250.c | 14 +++++++------- drivers/clk/samsung/clk-pll.c | 22 ++++++++++++++++++++-- drivers/clk/samsung/clk-pll.h | 27 +++++++++++++++++++++++++++ drivers/clk/samsung/clk.h | 14 +++++++++----- 5 files changed, 67 insertions(+), 18 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index ba25a1b..ceee66c 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c &lt; at &gt;&lt; at &gt; -997,13 +997,13 &lt; at &gt;&lt; at &gt; static __initdata struct of_device_id ext_clk_match[] = { struct __initdata samsung_pll_clock exynos4_plls[nr_plls] = { [apll] = PLL_A(pll_35xx, fo</pre> Yadwinder Singh Brar 2013-06-08T17:34:18 http://permalink.gmane.org/gmane.linux.kernel.samsung-soc/19730 <pre>From: Vikas Sajjan &lt;vikas.sajjan&lt; at &gt;linaro.org&gt; This patch adds set_rate and round_rate clk_ops for PLL36xx Reviewed-by: Tomasz Figa &lt;t.figa&lt; at &gt;samsung.com&gt; Reviewed-by: Doug Anderson &lt;dianders&lt; at &gt;chromium.org&gt; Signed-off-by: Vikas Sajjan &lt;vikas.sajjan&lt; at &gt;linaro.org&gt; --- drivers/clk/samsung/clk-pll.c | 78 ++++++++++++++++++++++++++++++++++++++++- 1 files changed, 77 insertions(+), 1 deletions(-) diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index df419aa..2adf761 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c &lt; at &gt;&lt; at &gt; -159,6 +159,8 &lt; at &gt;&lt; at &gt; static const struct clk_ops samsung_pll35xx_clk_min_ops = { /* * PLL36xx Clock Type */ +/* Maximum lock time can be 3000 * PDIV cycles */ +#define PLL36XX_LOCK_FACTOR (3000) #define PLL36XX_KDIV_MASK(0xFFFF) #define PLL36XX_MDIV_MASK(0x1FF) &lt; at &gt;&lt; at &gt; -167,6 +169,8 &lt; at &gt;&lt; at &gt; static const struct clk_ops samsung_pll35xx_clk_min_ops = { #define PLL36XX_MDIV_SHIFT(16) #define PLL36XX_PDIV_SHIFT(8) #define PLL36XX_SDIV_SHIFT(0) </pre> Yadwinder Singh Brar 2013-06-08T17:34:20 http://permalink.gmane.org/gmane.linux.kernel.samsung-soc/19729 <pre>Adds the EPLL and VPLL freq table for exynos5250 SoC. Signed-off-by: Vikas Sajjan &lt;vikas.sajjan&lt; at &gt;linaro.org&gt; Signed-off-by: Yadwinder Singh Brar &lt;yadi.brar&lt; at &gt;samsung.com&gt; --- drivers/clk/samsung/clk-exynos5250.c | 38 ++++++++++++++++++++++++++++++++++ drivers/clk/samsung/clk.h | 2 + 2 files changed, 40 insertions(+), 0 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index 09da356..d2743f9 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c &lt; at &gt;&lt; at &gt; -492,6 +492,29 &lt; at &gt;&lt; at &gt; static __initdata struct of_device_id ext_clk_match[] = { { }, }; +static __initdata struct samsung_pll_rate_table vpll_24mhz_tbl[] = { +/* sorted in descending order */ +/* PLL_36XX_RATE(rate, m, p, s, k) */ +PLL_36XX_RATE(266000000, 266, 3, 3, 0), +/* Not in UM, but need for eDP on snow */ +PLL_36XX_RATE(70500000, 94, 2, 4, 0), +{ }, +}; + +static __initdata struct samsung_pll_rate_table epll_24mhz_tbl[] = { +/* sorted in desce</pre> Yadwinder Singh Brar 2013-06-08T17:34:22 http://permalink.gmane.org/gmane.linux.kernel.samsung-soc/19728 <pre>From: Vikas Sajjan &lt;vikas.sajjan&lt; at &gt;linaro.org&gt; While trying to get rate of "mout_vpllsrc" MUX (parent) for registering the "fout_vpll" (child), we found get rate was failing. So this patch moves the mout_vpllsrc MUX out of the existing common list and registers the mout_vpllsrc MUX before the PLL registrations. Reviewed-by: Tomasz Figa &lt;t.figa&lt; at &gt;samsung.com&gt; Signed-off-by: Vikas Sajjan &lt;vikas.sajjan&lt; at &gt;linaro.org&gt; Signed-off-by: Yadwinder Singh Brar &lt;yadi.brar&lt; at &gt;samsung.com&gt; --- drivers/clk/samsung/clk-exynos5250.c | 7 ++++++- 1 files changed, 6 insertions(+), 1 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index a025269..09da356 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c &lt; at &gt;&lt; at &gt; -227,6 +227,10 &lt; at &gt;&lt; at &gt; struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initdata = { FFACTOR(none, "fout_bplldiv2", "fout_bpll", 1, 2, 0), }; +struct samsung_mux_clock exynos5250_pll_pmux_clks[] __initdata = { +MUX</pre> Yadwinder Singh Brar 2013-06-08T17:34:21 Search the mailing list at Gmane query http://search.gmane.org/?group=$group=gmane.linux.kernel.samsung-soc