gmane.linux.kernel.commits.head

arch/tile: Allow tilegx to build with either 16K or 64K page size

Linux Kernel Mailing List — 2012-05-25T23:37:54

Gitweb:     http://git.kernel.org/linus/;a=commit;h=d5d14ed6f2db7287a5088e1350cf422bf72140b3
Commit:     d5d14ed6f2db7287a5088e1350cf422bf72140b3
Parent:     47d632f9f8f3ed62b21f725e98b726d65769b6d7
Author:     Chris Metcalf <cmetcalf< at >tilera.com>
AuthorDate: Thu Mar 29 13:58:43 2012 -0400
Committer:  Chris Metcalf <cmetcalf< at >tilera.com>
CommitDate: Fri May 25 12:48:24 2012 -0400

    arch/tile: Allow tilegx to build with either 16K or 64K page size
    
    This change introduces new flags for the hv_install_context()
    API that passes a page table pointer to the hypervisor.  Clients
    can explicitly request 4K, 16K, or 64K small pages when they
    install a new context.  In practice, the page size is fixed at
    kernel compile time and the same size is always requested every
    time a new page table is installed.
    
    The <hv/hypervisor.h> header changes so that it provides more abstract
    macros for managing "page" things like PFNs and page tables.  For
    example there is now a HV_DEFAULT_PAG

arch/tile: fix hardwall for tilegx and generalize for idn and ipi

Linux Kernel Mailing List — 2012-05-25T23:37:54

Gitweb:     http://git.kernel.org/linus/;a=commit;h=b8ace0833feb308b1cb69d8b33ab08e0602dd2d2
Commit:     b8ace0833feb308b1cb69d8b33ab08e0602dd2d2
Parent:     621b19551507c8fd9d721f4038509c5bb155a983
Author:     Chris Metcalf <cmetcalf< at >tilera.com>
AuthorDate: Fri Mar 30 16:01:48 2012 -0400
Committer:  Chris Metcalf <cmetcalf< at >tilera.com>
CommitDate: Fri May 25 12:48:27 2012 -0400

    arch/tile: fix hardwall for tilegx and generalize for idn and ipi
    
    The hardwall drain code was not properly implemented for tilegx,
    just tilepro, so you couldn't reliably restart an application that
    made use of the udn.
    
    In addition, the code was only applicable to the udn (user dynamic
    network).  On tilegx there is a second user network that is available
    (the "idn"), and there is support for having I/O shims deliver
    user-level interrupts to applications ("ipi") which functions in a
    very similar way to the inter-core permissions used for udn/idn.
    So this change also generalizes the code

x86/mce Add validation check before GHES error is recorded

Linux Kernel Mailing List — 2012-05-25T23:37:54

Gitweb:     http://git.kernel.org/linus/;a=commit;h=8571723a698dcc0ee16c1c63908aa99dd940ce5c
Commit:     8571723a698dcc0ee16c1c63908aa99dd940ce5c
Parent:     95022b8cf6ed7f3292b60c8e85fe59a12bfb1c9e
Author:     Chen Gong <gong.chen< at >linux.intel.com>
AuthorDate: Fri Apr 20 16:02:05 2012 -0700
Committer:  Tony Luck <tony.luck< at >intel.com>
CommitDate: Fri Apr 20 16:02:05 2012 -0700

    x86/mce Add validation check before GHES error is recorded
    
    When GHES error record is logged into mcelog kernel buffer, a validation
    check for physical address is necessary, which prevents reporting an
    invalid physical address.
    
    [Since physical address is the only useful element in this error record,
    we drop generating the record completely if we don't have a valid address]
    
    Signed-off-by: Chen Gong <gong.chen< at >linux.intel.com>
    Signed-off-by: Tony Luck <tony.luck< at >intel.com>
---
 arch/x86/kernel/cpu/mcheck/mce-apei.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/arc

tile/mm/fault.c: Port OOM changes to handle_page_fault

Linux Kernel Mailing List — 2012-05-25T23:37:54

Gitweb:     http://git.kernel.org/linus/;a=commit;h=4ce6bea220f1a40aba928bd5624ada833ee1c52b
Commit:     4ce6bea220f1a40aba928bd5624ada833ee1c52b
Parent:     c6f696f69ab352b17f5c97f721e646b53b91f643
Author:     Kautuk Consul <consul.kautuk< at >gmail.com>
AuthorDate: Sat Mar 31 08:05:39 2012 -0400
Committer:  Chris Metcalf <cmetcalf< at >tilera.com>
CommitDate: Fri May 25 12:48:29 2012 -0400

    tile/mm/fault.c: Port OOM changes to handle_page_fault
    
    Commit d065bd810b6deb67d4897a14bfe21f8eb526ba99
    (mm: retry page fault when blocking on disk transfer) and
    commit 37b23e0525d393d48a7d59f870b3bc061a30ccdb
    (x86,mm: make pagefault killable)
    
    The above commits introduced changes into the x86 pagefault handler
    for making the page fault handler retryable as well as killable.
    
    These changes reduce the mmap_sem hold time, which is crucial
    during OOM killer invocation.
    
    Port these changes to tile.
    
    Signed-off-by: Kautuk Consul <consul.kautuk< at >gmail.com>
    [cmetcalf< at >til

x86/mce: Fix check for processor context when machine check was taken.

Linux Kernel Mailing List — 2012-05-25T23:37:54

Gitweb:     http://git.kernel.org/linus/;a=commit;h=875e26648cf9b6db9d8dc07b7959d7c61fb3f49c
Commit:     875e26648cf9b6db9d8dc07b7959d7c61fb3f49c
Parent:     a129a7c84582629741e5fa6f40026efcd7a65bd4
Author:     Tony Luck <tony.luck< at >intel.com>
AuthorDate: Wed May 23 14:14:22 2012 -0700
Committer:  Tony Luck <tony.luck< at >intel.com>
CommitDate: Wed May 23 14:22:44 2012 -0700

    x86/mce: Fix check for processor context when machine check was taken.
    
    Linus pointed out that there was no value is checking whether m->ip
    was zero - because zero is a legimate value.  If we have a reliable
    (or faked in the VM86 case) "m->cs" we can use it to tell whether we
    were in user mode or kernelwhen the machine check hit.
    
    Reported-by: Linus Torvalds <torvalds< at >linuxfoundation.org>
    Cc: <stable< at >vger.kernel.org>
    Signed-off-by: Tony Luck <tony.luck< at >intel.com>
---
 arch/x86/kernel/cpu/mcheck/mce-severity.c |   16 ++++++++++------
 1 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/arch/

arch/tile: use interrupt critical sections less

Linux Kernel Mailing List — 2012-05-25T23:37:54

Gitweb:     http://git.kernel.org/linus/;a=commit;h=51007004f44c9588d70ffb77e1f52479bd5b0e37
Commit:     51007004f44c9588d70ffb77e1f52479bd5b0e37
Parent:     76e10d158efb6d4516018846f60c2ab5501900bc
Author:     Chris Metcalf <cmetcalf< at >tilera.com>
AuthorDate: Tue Mar 27 15:40:20 2012 -0400
Committer:  Chris Metcalf <cmetcalf< at >tilera.com>
CommitDate: Fri May 25 12:48:20 2012 -0400

    arch/tile: use interrupt critical sections less
    
    In general we want to avoid ever touching memory while within an
    interrupt critical section, since the page fault path goes through
    a different path from the hypervisor when in an interrupt critical
    section, and we carefully decided with tilegx that we didn't need
    to support this path in the kernel.  (On tilepro we did implement
    that path as part of supporting atomic instructions in software.)
    
    In practice we always need to touch the kernel stack, since that's
    where we store the interrupt state before releasing the critical
    section, but t

arch/tile: support multiple huge page sizes dynamically

Linux Kernel Mailing List — 2012-05-25T23:37:54

Gitweb:     http://git.kernel.org/linus/;a=commit;h=621b19551507c8fd9d721f4038509c5bb155a983
Commit:     621b19551507c8fd9d721f4038509c5bb155a983
Parent:     d9ed9faac283a3be73f0e11a2ef49ee55aece4db
Author:     Chris Metcalf <cmetcalf< at >tilera.com>
AuthorDate: Sun Apr 1 14:04:21 2012 -0400
Committer:  Chris Metcalf <cmetcalf< at >tilera.com>
CommitDate: Fri May 25 12:48:27 2012 -0400

    arch/tile: support multiple huge page sizes dynamically
    
    This change adds support for a new "super" bit in the PTE, using the new
    arch_make_huge_pte() method.  The Tilera hypervisor sees the bit set at a
    given level of the page table and gangs together 4, 16, or 64 consecutive
    pages from that level of the hierarchy to create a larger TLB entry.
    
    One extra "super" page size can be specified at each of the three levels
    of the page table hierarchy on tilegx, using the "hugepagesz" argument
    on the boot command line.  A new hypervisor API is added to allow Linux
    to tell the hypervisor how many PT

arch/tile: support kexec() for tilegx

Linux Kernel Mailing List — 2012-05-25T23:37:54

Gitweb:     http://git.kernel.org/linus/;a=commit;h=fc0c49f5db640b9dfc7bb801892b5cbb7508a76a
Commit:     fc0c49f5db640b9dfc7bb801892b5cbb7508a76a
Parent:     cd6f32aa088f4d328e676c35f51b440f2fe5b98c
Author:     Chris Metcalf <cmetcalf< at >tilera.com>
AuthorDate: Thu Mar 29 15:48:23 2012 -0400
Committer:  Chris Metcalf <cmetcalf< at >tilera.com>
CommitDate: Fri May 25 12:48:25 2012 -0400

    arch/tile: support kexec() for tilegx
    
    Signed-off-by: Chris Metcalf <cmetcalf< at >tilera.com>
---
 arch/tile/include/asm/kexec.h                      |   12 ++
 arch/tile/kernel/Makefile                          |    2 +-
 arch/tile/kernel/machine_kexec.c                   |   35 ++++-
 .../{relocate_kernel.S => relocate_kernel_32.S}    |    0
 .../{relocate_kernel.S => relocate_kernel_64.S}    |  150 +++++++++-----------
 5 files changed, 105 insertions(+), 94 deletions(-)

diff --git a/arch/tile/include/asm/kexec.h b/arch/tile/include/asm/kexec.h
index c11a6cc..fc98ccf 100644
--- a/arch/tile/include/asm/kexec.h
+++ b/arch/t

tile: fix bug where fls(0) was not returning 0

Linux Kernel Mailing List — 2012-05-25T23:37:54

Gitweb:     http://git.kernel.org/linus/;a=commit;h=9f1d62bed7f015d11b9164078b7fea433b474114
Commit:     9f1d62bed7f015d11b9164078b7fea433b474114
Parent:     acd1a19e002790dd127b3ff86f95a4d269e7f1d0
Author:     Chris Metcalf <cmetcalf< at >tilera.com>
AuthorDate: Fri May 25 12:32:09 2012 -0400
Committer:  Chris Metcalf <cmetcalf< at >tilera.com>
CommitDate: Fri May 25 15:00:43 2012 -0400

    tile: fix bug where fls(0) was not returning 0
    
    This is because __builtin_clz(0) returns 64 for the "undefined" case
    of 0, since the builtin just does a right-shift 32 and "clz" instruction.
    So, use the alpha approach of casting to u32 and using __builtin_clzll().
    
    Cc: stable< at >vger.kernel.org
    Signed-off-by: Chris Metcalf <cmetcalf< at >tilera.com>
---
 arch/tile/include/asm/bitops.h |   12 ++++++------
 1 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/tile/include/asm/bitops.h b/arch/tile/include/asm/bitops.h
index 16f1fa5..bd186c4 100644
--- a/arch/tile/include/asm/bitops.h
+++ b/arch/til

x86/mce: Add instruction recovery signatures to mce-severity table

Linux Kernel Mailing List — 2012-05-25T23:37:54

Gitweb:     http://git.kernel.org/linus/;a=commit;h=37c3459b67dd5a396a968e819cf4a86d24ac9ace
Commit:     37c3459b67dd5a396a968e819cf4a86d24ac9ace
Parent:     875e26648cf9b6db9d8dc07b7959d7c61fb3f49c
Author:     Tony Luck <tony.luck< at >intel.com>
AuthorDate: Thu May 10 11:12:14 2012 -0700
Committer:  Tony Luck <tony.luck< at >intel.com>
CommitDate: Wed May 23 14:24:11 2012 -0700

    x86/mce: Add instruction recovery signatures to mce-severity table
    
    Instruction recovery cases are very similar to the data recovery one
    we already have. Just trade out for a new MCACOD value.
    
    Signed-off-by: Tony Luck <tony.luck< at >intel.com>
---
 arch/x86/kernel/cpu/mcheck/mce-severity.c |   10 ++++++++++
 1 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/arch/x86/kernel/cpu/mcheck/mce-severity.c b/arch/x86/kernel/cpu/mcheck/mce-severity.c
index 1ccd453..413c2ce 100644
--- a/arch/x86/kernel/cpu/mcheck/mce-severity.c
+++ b/arch/x86/kernel/cpu/mcheck/mce-severity.c
< at >< at > -126,6 +126,16 < at >< at > static struct severit

tile: default to tilegx_defconfig for ARCH=tile

Linux Kernel Mailing List — 2012-05-25T23:37:54

Gitweb:     http://git.kernel.org/linus/;a=commit;h=1fcb78e9da714d96f65edd37b29dae3b1f7df508
Commit:     1fcb78e9da714d96f65edd37b29dae3b1f7df508
Parent:     9f1d62bed7f015d11b9164078b7fea433b474114
Author:     Chris Metcalf <cmetcalf< at >tilera.com>
AuthorDate: Sun May 20 15:15:34 2012 -0400
Committer:  Chris Metcalf <cmetcalf< at >tilera.com>
CommitDate: Fri May 25 15:02:43 2012 -0400

    tile: default to tilegx_defconfig for ARCH=tile
    
    There is no "ARCH=tile" (just like there is no "ARCH=x86") so we need
    to pick a default configuration, either tilepro or tilegx, when users
    specify ARCH=tile.  We'll use tilegx, since that's our current chip.
    
    Reported-by: Paul Gortmaker <paul.gortmaker< at >windriver.com>
    Signed-off-by: Chris Metcalf <cmetcalf< at >tilera.com>
---
 arch/tile/Makefile |    7 ++++++-
 1 files changed, 6 insertions(+), 1 deletions(-)

diff --git a/arch/tile/Makefile b/arch/tile/Makefile
index 9520bc5..e20b0a0 100644
--- a/arch/tile/Makefile
+++ b/arch/tile/Makefile
< at >< at > -34,7 +34,12 < at >

arch/tile: allow querying cpu module information from the hypervisor

Linux Kernel Mailing List — 2012-05-25T23:37:54

Gitweb:     http://git.kernel.org/linus/;a=commit;h=8703d6e0fcfdcc9323d5316a443882e790efc1a6
Commit:     8703d6e0fcfdcc9323d5316a443882e790efc1a6
Parent:     b8ace0833feb308b1cb69d8b33ab08e0602dd2d2
Author:     Chris Metcalf <cmetcalf< at >tilera.com>
AuthorDate: Fri Mar 30 16:21:17 2012 -0400
Committer:  Chris Metcalf <cmetcalf< at >tilera.com>
CommitDate: Fri May 25 12:48:28 2012 -0400

    arch/tile: allow querying cpu module information from the hypervisor
    
    This just adds a few more attributes to the information Linux
    can query from the hypervisor for the /sys/hypervisor/board/ directory,
    providing part, serial#, revision#, and description for cpu modules
    (as opposed to the board itself, or any mezzanine boards).
    
    Signed-off-by: Chris Metcalf <cmetcalf< at >tilera.com>
---
 arch/tile/include/hv/hypervisor.h |   14 +++++++++++++-
 arch/tile/kernel/sysfs.c          |    8 ++++++++
 2 files changed, 21 insertions(+), 1 deletions(-)

diff --git a/arch/tile/include/hv/hypervisor.h b/arch/tile/inc

mm: add new arch_make_huge_pte() method for tile support

Linux Kernel Mailing List — 2012-05-25T23:37:54

Gitweb:     http://git.kernel.org/linus/;a=commit;h=d9ed9faac283a3be73f0e11a2ef49ee55aece4db
Commit:     d9ed9faac283a3be73f0e11a2ef49ee55aece4db
Parent:     fc0c49f5db640b9dfc7bb801892b5cbb7508a76a
Author:     Chris Metcalf <cmetcalf< at >tilera.com>
AuthorDate: Sun Apr 1 14:01:34 2012 -0400
Committer:  Chris Metcalf <cmetcalf< at >tilera.com>
CommitDate: Fri May 25 12:48:26 2012 -0400

    mm: add new arch_make_huge_pte() method for tile support
    
    The tile support for multiple-size huge pages requires tagging
    the hugetlb PTE with a "super" bit for PTEs that are multiples of
    the basic size of a pagetable span.  To set that bit properly
    we need to tweak the PTe in make_huge_pte() based on the vma.
    
    This change provides the API for a subsequent tile-specific
    change to use.
    
    Reviewed-by: Hillf Danton <dhillf< at >gmail.com>
    Signed-off-by: Chris Metcalf <cmetcalf< at >tilera.com>
---
 include/linux/hugetlb.h |    8 ++++++++
 mm/hugetlb.c            |    1 +
 2 files changed, 9 insertions(

arch/tile: mark TILEGX as not EXPERIMENTAL

Linux Kernel Mailing List — 2012-05-25T23:37:54

Gitweb:     http://git.kernel.org/linus/;a=commit;h=acd1a19e002790dd127b3ff86f95a4d269e7f1d0
Commit:     acd1a19e002790dd127b3ff86f95a4d269e7f1d0
Parent:     4ce6bea220f1a40aba928bd5624ada833ee1c52b
Author:     Chris Metcalf <cmetcalf< at >tilera.com>
AuthorDate: Sat Apr 7 15:58:24 2012 -0400
Committer:  Chris Metcalf <cmetcalf< at >tilera.com>
CommitDate: Fri May 25 15:00:39 2012 -0400

    arch/tile: mark TILEGX as not EXPERIMENTAL
    
    Also create a TILEPRO config setting to use for #ifdefs where it
    is cleaner to do so, and make the 64BIT setting depend directly
    on the setting of TILEGX.
    
    Signed-off-by: Chris Metcalf <cmetcalf< at >tilera.com>
---
 arch/tile/Kconfig |   10 ++++------
 1 files changed, 4 insertions(+), 6 deletions(-)

diff --git a/arch/tile/Kconfig b/arch/tile/Kconfig
index cc56642..0294b21 100644
--- a/arch/tile/Kconfig
+++ b/arch/tile/Kconfig
< at >< at > -117,16 +117,14 < at >< at > config HVC_TILE
 select HVC_DRIVER
 def_bool y
 
-# Please note: TILE-Gx support is not yet finalized; this is
-# the

x86/mce: Avoid reading every machine check bank register twice.

Linux Kernel Mailing List — 2012-05-25T23:37:54

Gitweb:     http://git.kernel.org/linus/;a=commit;h=95022b8cf6ed7f3292b60c8e85fe59a12bfb1c9e
Commit:     95022b8cf6ed7f3292b60c8e85fe59a12bfb1c9e
Parent:     0034102808e0dbbf3a2394b82b1bb40b5778de9e
Author:     Tony Luck <tony.luck< at >intel.com>
AuthorDate: Wed Apr 18 15:19:40 2012 -0700
Committer:  Tony Luck <tony.luck< at >intel.com>
CommitDate: Thu Apr 19 09:12:43 2012 -0700

    x86/mce: Avoid reading every machine check bank register twice.
    
    Reading machine check bank registers is slow. There is a trend of
    increasing the number of banks, and the number of cores. The main section
    of do_machine_check() is a serialized section where each cpu in turn
    checks every bank. Even on a little two socket SandyBridge-EP system
    that multiplies out as:
    
    2 sockets * 8 cores * 2 hyperthreads * 20 banks = 640 MSRs
    
    We already scan the banks in parallel in mce_no_way_out() to see if there
    is a fatal error anywhere in the system. If we build a cache of VALID
    bits during this scan, w

MCE: Fix vm86 handling for 32bit mce handler

Linux Kernel Mailing List — 2012-05-25T23:37:54

Gitweb:     http://git.kernel.org/linus/;a=commit;h=a129a7c84582629741e5fa6f40026efcd7a65bd4
Commit:     a129a7c84582629741e5fa6f40026efcd7a65bd4
Parent:     8571723a698dcc0ee16c1c63908aa99dd940ce5c
Author:     Andi Kleen <andi< at >firstfloor.org>
AuthorDate: Fri Nov 19 13:16:22 2010 +0100
Committer:  Tony Luck <tony.luck< at >intel.com>
CommitDate: Wed May 23 14:22:37 2012 -0700

    MCE: Fix vm86 handling for 32bit mce handler
    
    When running on 32bit the mce handler could misinterpret
    vm86 mode as ring 0. This can affect whether it does recovery
    or not; it was possible to panic when recovery was actually
    possible.
    
    Fix this by always forcing vm86 to look like ring 3.
    
    Signed-off-by: Andi Kleen <ak< at >linux.intel.com>
    Cc: <stable< at >vger.kernel.org>
    Signed-off-by: Tony Luck <tony.luck< at >intel.com>
---
 arch/x86/kernel/cpu/mcheck/mce.c |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
i

arch/tile: optimize get_user/put_user and friends

Linux Kernel Mailing List — 2012-05-25T23:37:54

Gitweb:     http://git.kernel.org/linus/;a=commit;h=47d632f9f8f3ed62b21f725e98b726d65769b6d7
Commit:     47d632f9f8f3ed62b21f725e98b726d65769b6d7
Parent:     1efea40d4172a2a475ccb29b59d6221e9d0c174b
Author:     Chris Metcalf <cmetcalf< at >tilera.com>
AuthorDate: Thu Mar 29 13:39:51 2012 -0400
Committer:  Chris Metcalf <cmetcalf< at >tilera.com>
CommitDate: Fri May 25 12:48:23 2012 -0400

    arch/tile: optimize get_user/put_user and friends
    
    Use direct load/store for the get_user/put_user.
    
    Previously, we would call out to a helper routine that would do the
    appropriate thing and then return, handling the possible exception
    internally.  Now we inline the load or store, along with a "we succeeded"
    indication in a register; if the load or store faults, we write a
    "we failed" indication into the same register and then return to the
    following instruction.  This is more efficient and gives us more compact
    code, as well as being more in line with what other architectures do.

arch/tile: add descriptive text if the kernel reports a bad trap

Linux Kernel Mailing List — 2012-05-25T23:37:54

Gitweb:     http://git.kernel.org/linus/;a=commit;h=c6f696f69ab352b17f5c97f721e646b53b91f643
Commit:     c6f696f69ab352b17f5c97f721e646b53b91f643
Parent:     8703d6e0fcfdcc9323d5316a443882e790efc1a6
Author:     Chris Metcalf <cmetcalf< at >tilera.com>
AuthorDate: Fri Mar 30 16:31:08 2012 -0400
Committer:  Chris Metcalf <cmetcalf< at >tilera.com>
CommitDate: Fri May 25 12:48:28 2012 -0400

    arch/tile: add descriptive text if the kernel reports a bad trap
    
    If the kernel unexpectedly takes a bad trap, it's convenient to
    have it report the type of trap as part of the error.  This gives
    customers a bit more context before they call up customer support.
    
    Signed-off-by: Chris Metcalf <cmetcalf< at >tilera.com>
---
 arch/tile/kernel/traps.c |   30 ++++++++++++++++++++++++++++--
 1 files changed, 28 insertions(+), 2 deletions(-)

diff --git a/arch/tile/kernel/traps.c b/arch/tile/kernel/traps.c
index 73cff81..5b19a23 100644
--- a/arch/tile/kernel/traps.c
+++ b/arch/tile/kernel/traps.c
< at >< at > -195,6 +195,25 < at >< at >

arch/tile: allow building Linux with transparent huge pages enabled

Linux Kernel Mailing List — 2012-05-25T23:37:54

Gitweb:     http://git.kernel.org/linus/;a=commit;h=73636b1aacb1a07e6fbe0d25e560e69b024a8e25
Commit:     73636b1aacb1a07e6fbe0d25e560e69b024a8e25
Parent:     51007004f44c9588d70ffb77e1f52479bd5b0e37
Author:     Chris Metcalf <cmetcalf< at >tilera.com>
AuthorDate: Wed Mar 28 13:59:18 2012 -0400
Committer:  Chris Metcalf <cmetcalf< at >tilera.com>
CommitDate: Fri May 25 12:48:21 2012 -0400

    arch/tile: allow building Linux with transparent huge pages enabled
    
    The change adds some infrastructure for managing tile pmd's more generally,
    using pte_pmd() and pmd_pte() methods to translate pmd values to and
    from ptes, since on TILEPro a pmd is really just a nested structure
    holding a pgd (aka pte).  Several existing pmd methods are moved into
    this framework, and a whole raft of additional pmd accessors are defined
    that are used by the transparent hugepage framework.
    
    The tile PTE now has a "client2" bit.  The bit is used to indicate a
    transparent huge page is in the process of being

intel-iommu: Add device info into list before doing context mapping

Linux Kernel Mailing List — 2012-05-25T23:37:54

Gitweb:     http://git.kernel.org/linus/;a=commit;h=e2ad23d04c1304431ab5176c89b7b476ded2d995
Commit:     e2ad23d04c1304431ab5176c89b7b476ded2d995
Parent:     da89fb165e5e51a2ec1ff8a0ff6bc052d1068184
Author:     David Woodhouse <dwmw2< at >infradead.org>
AuthorDate: Fri May 25 17:42:54 2012 +0100
Committer:  Linus Torvalds <torvalds< at >linux-foundation.org>
CommitDate: Fri May 25 15:50:29 2012 -0700

    intel-iommu: Add device info into list before doing context mapping
    
    Add device info into list before doing context mapping, because device
    info will be used by iommu_enable_dev_iotlb(). Without it, ATS won't get
    enabled as it should be.
    
    ATS, while a dubious decision from a security point of view, can be very
    important for performance.
    
    Signed-off-by: Xudong Hao <xudong.hao< at >intel.com>
    Signed-off-by: Xiantao Zhang <xiantao.zhang< at >intel.com>
    Acked-by: Chris Wright <chrisw< at >sous-sol.org>
    Signed-off-by: David Woodhouse <David.Woodhouse< at >intel.com>
    Cc: stable< at >kernel.org

arch/tile: support building big-endian kernel

Linux Kernel Mailing List — 2012-05-25T23:37:54

Gitweb:     http://git.kernel.org/linus/;a=commit;h=1efea40d4172a2a475ccb29b59d6221e9d0c174b
Commit:     1efea40d4172a2a475ccb29b59d6221e9d0c174b
Parent:     73636b1aacb1a07e6fbe0d25e560e69b024a8e25
Author:     Chris Metcalf <cmetcalf< at >tilera.com>
AuthorDate: Thu Mar 29 13:30:31 2012 -0400
Committer:  Chris Metcalf <cmetcalf< at >tilera.com>
CommitDate: Fri May 25 12:48:22 2012 -0400

    arch/tile: support building big-endian kernel
    
    The toolchain supports big-endian mode now, so add support for building
    the kernel to run big-endian as well.
    
    Signed-off-by: Chris Metcalf <cmetcalf< at >tilera.com>
---
 arch/tile/include/asm/byteorder.h |   20 ++++++++++++++++++++
 arch/tile/include/asm/elf.h       |    5 +++++
 arch/tile/include/hv/hypervisor.h |   16 ++++++++++++++++
 arch/tile/kernel/module.c         |   12 +++++++++++-
 arch/tile/kernel/single_step.c    |   16 ++++++++++++----
 arch/tile/lib/memchr_64.c         |    8 +++-----
 arch/tile/lib/memcpy_64.c         |   23 +++++++++++++++++++++--
 ar