http://permalink.gmane.org/gmane.linux.bios hourly 1 1901-01-01T00:00+00:00 http://gmane.org/img/gmane-25t.png http://gmane.org http://permalink.gmane.org/gmane.linux.bios/71492 <pre>the following patch was just integrated into master: commit ae114e94989a273015a758ffcd4260d88be8050f Author: Stefan Reinauer &lt;reinauer&lt; at &gt;chromium.org&gt; Date: Tue May 15 13:28:07 2012 -0700 Implement %zu / %zd in printk The SPI drivers from u-boot make heavy use of %zu/%zd (size_t/ssize_t). Implement this in our printk implementation so we get useful output. Change-Id: I91798ff4f28b9c3cd4db204c7ec503596d247dcd Signed-off-by: Stefan Reinauer &lt;reinauer&lt; at &gt;google.com&gt; Reviewed-By: Patrick Georgi &lt;patrick&lt; at &gt;georgi-clan.de&gt; at Sat May 26 07:16:39 2012, giving +2 See http://review.coreboot.org/1043 for details. -gerrit </pre> gerrit< at >coreboot.org 2012-05-26T05:16:43 http://permalink.gmane.org/gmane.linux.bios/71491 <pre>the following patch was just integrated into master: commit 1d0ab4d60b763fe740e4ae94d0dd4ca692286494 Author: Stefan Reinauer &lt;reinauer&lt; at &gt;chromium.org&gt; Date: Tue May 15 12:36:57 2012 -0700 Move subsystem IDs to devicetree.cb A while back coreboot was changed to read the subsystem IDs from devicetree.cb to allow each onboard PCI device to have its own subsystem id. When we originally branched, this was not the case, and the sandybridge/ivybridge mainboards have not been updated yet. Also, drop the subsystem ID from Emerald Lake 2, since it's not a Google device. Change-Id: Ie96fd67cd2ff65ad6ff725914e3bad843e78712e Signed-off-by: Stefan Reinauer &lt;reinauer&lt; at &gt;google.com&gt; Reviewed-By: Patrick Georgi &lt;patrick&lt; at &gt;georgi-clan.de&gt; at Sat May 26 07:16:00 2012, giving +2 See http://review.coreboot.org/1042 for details. -gerrit </pre> gerrit< at >coreboot.org 2012-05-26T05:16:02 http://permalink.gmane.org/gmane.linux.bios/71490 <pre>the following patch was just integrated into master: commit f394b77b035c83008bdc67a6ff532ae587267dd2 Author: Stefan Reinauer &lt;reinauer&lt; at &gt;chromium.org&gt; Date: Wed May 23 11:03:29 2012 -0700 Reduce default verbosity of SPI flash drivers Only print PP: lines if CONFIG_DEBUG_SPI_FLASH is enabled. Change-Id: If25e916ecb585f37c90d42980e933a6cd1a3d956 Signed-off-by: Stefan Reinauer &lt;reinauer&lt; at &gt;google.com&gt; Build-Tested: build bot (Jenkins) at Fri May 25 23:22:53 2012, giving +1 See http://review.coreboot.org/1045 for details. -gerrit </pre> gerrit< at >coreboot.org 2012-05-25T22:38:05 http://permalink.gmane.org/gmane.linux.bios/71489 <pre>the following patch was just integrated into master: commit 1ef774ab8232f66de72fb2dcd796ee819476b213 Author: Stefan Reinauer &lt;reinauer&lt; at &gt;chromium.org&gt; Date: Mon May 14 13:52:32 2012 -0700 Fix printk types in SPI flash drivers - use %zu instead of %zd for size_t (%zd is for ssize_t) - use %x instead of %lx for u32 - break some long lines to avoid commit hook trouble Change-Id: Idfad716523dbcd2a595d26317240e972b5253e8b Signed-off-by: Stefan Reinauer &lt;reinauer&lt; at &gt;google.com&gt; Build-Tested: build bot (Jenkins) at Fri May 25 23:08:15 2012, giving +1 See http://review.coreboot.org/1041 for details. -gerrit </pre> gerrit< at >coreboot.org 2012-05-25T22:37:34 http://permalink.gmane.org/gmane.linux.bios/71488 <pre>Stefan Reinauer (stefan.reinauer&lt; at &gt;coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1052 -gerrit commit 7993afd7b1bb29dd3bcbc4ea3f56232ff30998be Author: Stefan Reinauer &lt;reinauer&lt; at &gt;chromium.org&gt; Date: Wed May 23 14:20:18 2012 -0700 ChromeOS: Remove remnants of FDT support Originally, on ChromeBooks, coreboot would provide a modified u-boot device tree (FDT) to u-boot in CBMEM. However, u-boot can now create all the information it needs from the coreboot table and add it to its device tree itself. This means we can drop this (anyways unused) code. Change-Id: I4ab20bbb8525e7349b18764aa202bbe81958d06a Signed-off-by: Stefan Reinauer &lt;reinauer&lt; at &gt;google.com&gt; --- src/vendorcode/google/chromeos/gnvs.c | 42 --------------------------------- src/vendorcode/google/chromeos/gnvs.h | 1 - 2 files changed, 0 insertions(+), 43 deletions(-) diff --git a/src/vendorcode/google/chromeos/gnvs.c b/src/vendorcode/google/chromeo</pre> Stefan Reinauer 2012-05-25T20:01:19 http://permalink.gmane.org/gmane.linux.bios/71487 <pre>Stefan Reinauer (stefan.reinauer&lt; at &gt;coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1050 -gerrit commit a050f7eef23798440022face8181eb0598b4363e Author: Vadim Bendebury &lt;vbendeb&lt; at &gt;chromium.org&gt; Date: Thu May 17 17:21:27 2012 -0700 Fix full reset for Ivy Bridge platforms Experiments have shown that writing plain value of 6 at byte io address of 0xcf9 causes the systems to reset and reboot reliably. Change-Id: Ie900e4b4014cded868647372b027918b7ff72578 Signed-off-by: Vadim Bendebury &lt;vbendeb&lt; at &gt;chromium.org&gt; --- src/southbridge/intel/bd82x6x/reset.c | 9 --------- 1 files changed, 0 insertions(+), 9 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/reset.c b/src/southbridge/intel/bd82x6x/reset.c index 29b69ff..5324142 100644 --- a/src/southbridge/intel/bd82x6x/reset.c +++ b/src/southbridge/intel/bd82x6x/reset.c &lt; at &gt;&lt; at &gt; -26,16 +26,7 &lt; at &gt;&lt; at &gt; void soft_reset(void) outb(0x04, 0xcf9); } -#if 0 void hard_reset(void) { -</pre> Stefan Reinauer 2012-05-25T20:00:34 http://permalink.gmane.org/gmane.linux.bios/71486 <pre>Stefan Reinauer (stefan.reinauer&lt; at &gt;coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1049 -gerrit commit 3a99e2cd0443e017d6978930db98ad579af5a93f Author: Vadim Bendebury &lt;vbendeb&lt; at &gt;chromium.org&gt; Date: Tue May 15 14:18:59 2012 -0700 Provide functions to access arbitrary GPIO pins and vectors This change adds utility functions which allow to read any GPIO pin, as well as a vector of GPIO pin values. As presented, these functions will be available to Sandy Bridge and Ivy Bridge systems only. There is no error checking: trying to read GPIO pin number which exceeds actual number of pins will return zero, trying to read GPIO which is not actually configured as such will return unpredictable value. When reading a GPIO pin vector, the pin numbers are passed in an array, terminated by -1. For instance, to read GPIO pins 4, 2, 15 as a three bit number GPIO4 * 4 + GPIO2 * 2 + GPIO15 * 1, one should</pre> Stefan Reinauer 2012-05-25T20:00:05 http://permalink.gmane.org/gmane.linux.bios/71485 <pre>Stefan Reinauer (stefan.reinauer&lt; at &gt;coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1047 -gerrit commit a9f436fa6f13d46f9d4a2b9f4f849a3f828ab5cd Author: Stefan Reinauer &lt;reinauer&lt; at &gt;chromium.org&gt; Date: Fri May 11 16:30:54 2012 -0700 Drop config variable CPU_MODEL_INDEX It's only used in the ACPI generator for Sandybridge/Ivybridge CPUs and the code can easily be changed to not rely on any Kconfig magic. Change-Id: Ie2f92edfe8908f7eb2fda3088f77ad22f491ddcf Signed-off-by: Stefan Reinauer &lt;reinauer&lt; at &gt;google.com&gt; --- src/cpu/intel/model_206ax/Kconfig | 8 -------- src/cpu/intel/model_206ax/acpi.c | 11 ++--------- 2 files changed, 2 insertions(+), 17 deletions(-) diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index c11f21a..d2d4c73 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig &lt; at &gt;&lt; at &gt; -36,18 +36,10 &lt; at &gt;&lt; at &gt; if CPU_INTEL_MODEL_206AX config CPU_MODEL_NAME </pre> Stefan Reinauer 2012-05-25T19:59:24 http://permalink.gmane.org/gmane.linux.bios/71484 <pre>Stefan Reinauer (stefan.reinauer&lt; at &gt;coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1046 -gerrit commit 15606496889239bcfa231ed416b7a1f34033ccb7 Author: Stefan Reinauer &lt;reinauer&lt; at &gt;chromium.org&gt; Date: Wed May 23 11:21:10 2012 -0700 Sandybridge: Fix MRC cache calculation The MRC region is described by Kconfig variables, no further math or parsing is required at this point. Change-Id: I290d8788b69ef007e9ea2317ce55aefa2d791883 Signed-off-by: Stefan Reinauer &lt;reinauer&lt; at &gt;google.com&gt; --- src/northbridge/intel/sandybridge/mrccache.c | 6 ++---- 1 files changed, 2 insertions(+), 4 deletions(-) diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c index 5c4c382..aad2b91 100644 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ b/src/northbridge/intel/sandybridge/mrccache.c &lt; at &gt;&lt; at &gt; -65,8 +65,8 &lt; at &gt;&lt; at &gt; u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr) { u8 *mrc_regi</pre> Stefan Reinauer 2012-05-25T19:58:34 http://permalink.gmane.org/gmane.linux.bios/71483 <pre>Stefan Reinauer (stefan.reinauer&lt; at &gt;coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1051 -gerrit commit 63acdad535f94580b137661a97a99264c5d00541 Author: Stefan Reinauer &lt;reinauer&lt; at &gt;chromium.org&gt; Date: Wed May 23 14:16:47 2012 -0700 Sandybridge: Remove remnants of FDT support from MRC cache code Originally, ChromeBooks would get the offset of the MRC cache from an entry in the u-boot device tree. Not everyone wants to use u-boot on Sandybridge systems, however. Since the new code (based on Kconfig) is now fully working, we can drop the u-boot device tree remnants. Change-Id: I4e012ea981f16dce9a4d155254facd29874b28ef Signed-off-by: Stefan Reinauer &lt;reinauer&lt; at &gt;google.com&gt; --- src/northbridge/intel/sandybridge/mrccache.c | 80 ++++---------------------- 1 files changed, 11 insertions(+), 69 deletions(-) diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c index a</pre> Stefan Reinauer 2012-05-25T19:58:31 http://permalink.gmane.org/gmane.linux.bios/71482 <pre>Stefan Reinauer (stefan.reinauer&lt; at &gt;coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1044 -gerrit commit 3255dae09981daa753118fd3f9cd46dbd071001a Author: Stefan Reinauer &lt;reinauer&lt; at &gt;chromium.org&gt; Date: Tue May 22 15:24:51 2012 -0700 Fix compilation with CONFIG_DEBUG_SPI_FLASH enabled Right now coreboot compilation fails when SPI flash debugging is enabled. Fix it by using the right set of memory functions. Change-Id: I5e372c4a5df53b4d46aaed9e251e5205ff68cb5b Signed-off-by: Stefan Reinauer &lt;reinauer&lt; at &gt;google.com&gt; --- src/drivers/spi/spi_flash.c | 1 - src/southbridge/intel/bd82x6x/spi.c | 12 ++++++------ 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index 2c0f702..0b859f3 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c &lt; at &gt;&lt; at &gt; -264,7 +264,6 &lt; at &gt;&lt; at &gt; struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, #if</pre> Stefan Reinauer 2012-05-25T19:56:47 http://permalink.gmane.org/gmane.linux.bios/71481 <pre>Stefan Reinauer (stefan.reinauer&lt; at &gt;coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1048 -gerrit commit a770d5e34857f2641e973806f64aad6364ed6fbb Author: Stefan Reinauer &lt;reinauer&lt; at &gt;chromium.org&gt; Date: Wed May 23 11:18:35 2012 -0700 Add support for Panther Point to SPI driver Change-Id: I98b05d9e639eda880b6e8dc6398413d1f4f5e9c3 Signed-off-by: Stefan Reinauer &lt;reinauer&lt; at &gt;google.com&gt; --- src/include/device/pci_ids.h | 2 ++ src/southbridge/intel/bd82x6x/spi.c | 29 ++++++++++++++++++++--------- 2 files changed, 22 insertions(+), 9 deletions(-) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 1765293..4ebd572 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h &lt; at &gt;&lt; at &gt; -2504,6 +2504,8 &lt; at &gt;&lt; at &gt; #define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN0x1c41 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX0x1c5f +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN 0x1e41 +#define PCI_DEVICE_ID_IN</pre> Stefan Reinauer 2012-05-25T19:56:46 http://permalink.gmane.org/gmane.linux.bios/71480 <pre>Stefan Reinauer (stefan.reinauer&lt; at &gt;coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1042 -gerrit commit 1d0ab4d60b763fe740e4ae94d0dd4ca692286494 Author: Stefan Reinauer &lt;reinauer&lt; at &gt;chromium.org&gt; Date: Tue May 15 12:36:57 2012 -0700 Move subsystem IDs to devicetree.cb A while back coreboot was changed to read the subsystem IDs from devicetree.cb to allow each onboard PCI device to have its own subsystem id. When we originally branched, this was not the case, and the sandybridge/ivybridge mainboards have not been updated yet. Also, drop the subsystem ID from Emerald Lake 2, since it's not a Google device. Change-Id: Ie96fd67cd2ff65ad6ff725914e3bad843e78712e Signed-off-by: Stefan Reinauer &lt;reinauer&lt; at &gt;google.com&gt; --- src/mainboard/intel/emeraldlake2/Kconfig | 8 -------- src/mainboard/samsung/lumpy/Kconfig | 8 -------- src/mainboard/samsung/lumpy/devicetree.cb | 1 + src/mainboard/samsung/stum</pre> Stefan Reinauer 2012-05-25T19:54:08 http://permalink.gmane.org/gmane.linux.bios/71479 <pre>Stefan Reinauer (stefan.reinauer&lt; at &gt;coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1043 -gerrit commit ae114e94989a273015a758ffcd4260d88be8050f Author: Stefan Reinauer &lt;reinauer&lt; at &gt;chromium.org&gt; Date: Tue May 15 13:28:07 2012 -0700 Implement %zu / %zd in printk The SPI drivers from u-boot make heavy use of %zu/%zd (size_t/ssize_t). Implement this in our printk implementation so we get useful output. Change-Id: I91798ff4f28b9c3cd4db204c7ec503596d247dcd Signed-off-by: Stefan Reinauer &lt;reinauer&lt; at &gt;google.com&gt; --- src/console/vtxprintf.c | 5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-) diff --git a/src/console/vtxprintf.c b/src/console/vtxprintf.c index a370e5f..28c5a60 100644 --- a/src/console/vtxprintf.c +++ b/src/console/vtxprintf.c &lt; at &gt;&lt; at &gt; -170,7 +170,7 &lt; at &gt;&lt; at &gt; repeat: /* get the conversion qualifier */ qualifier = -1; -if (*fmt == 'h' || *fmt == 'l' || *fmt == 'L') { +if (*fmt == 'h' || *fmt == 'l' || *fmt =</pre> Stefan Reinauer 2012-05-25T19:52:24 http://permalink.gmane.org/gmane.linux.bios/71478 <pre>Stefan Reinauer (stefan.reinauer&lt; at &gt;coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1045 -gerrit commit f394b77b035c83008bdc67a6ff532ae587267dd2 Author: Stefan Reinauer &lt;reinauer&lt; at &gt;chromium.org&gt; Date: Wed May 23 11:03:29 2012 -0700 Reduce default verbosity of SPI flash drivers Only print PP: lines if CONFIG_DEBUG_SPI_FLASH is enabled. Change-Id: If25e916ecb585f37c90d42980e933a6cd1a3d956 Signed-off-by: Stefan Reinauer &lt;reinauer&lt; at &gt;google.com&gt; --- src/drivers/spi/eon.c | 2 ++ src/drivers/spi/macronix.c | 2 ++ src/drivers/spi/spansion.c | 2 ++ src/drivers/spi/stmicro.c | 2 ++ src/drivers/spi/winbond.c | 2 ++ 5 files changed, 10 insertions(+), 0 deletions(-) diff --git a/src/drivers/spi/eon.c b/src/drivers/spi/eon.c index b7c0630..7d9bc44 100644 --- a/src/drivers/spi/eon.c +++ b/src/drivers/spi/eon.c &lt; at &gt;&lt; at &gt; -85,9 +85,11 &lt; at &gt;&lt; at &gt; static int eon_write(struct spi_flash *flash, cmd[2] = page_addr; cmd[3] = byte_ad</pre> Stefan Reinauer 2012-05-25T19:50:02 http://permalink.gmane.org/gmane.linux.bios/71477 <pre>Stefan Reinauer (stefan.reinauer&lt; at &gt;coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1041 -gerrit commit 1ef774ab8232f66de72fb2dcd796ee819476b213 Author: Stefan Reinauer &lt;reinauer&lt; at &gt;chromium.org&gt; Date: Mon May 14 13:52:32 2012 -0700 Fix printk types in SPI flash drivers - use %zu instead of %zd for size_t (%zd is for ssize_t) - use %x instead of %lx for u32 - break some long lines to avoid commit hook trouble Change-Id: Idfad716523dbcd2a595d26317240e972b5253e8b Signed-off-by: Stefan Reinauer &lt;reinauer&lt; at &gt;google.com&gt; --- src/drivers/spi/eon.c | 2 +- src/drivers/spi/macronix.c | 7 ++++--- src/drivers/spi/spansion.c | 3 ++- src/drivers/spi/sst.c | 2 +- src/drivers/spi/stmicro.c | 3 ++- src/drivers/spi/winbond.c | 8 ++++---- 6 files changed, 14 insertions(+), 11 deletions(-) diff --git a/src/drivers/spi/eon.c b/src/drivers/spi/eon.c index 4056953..b7c0630 100644 --- a/src/drivers/spi/eon.c </pre> Stefan Reinauer 2012-05-25T19:49:22 http://permalink.gmane.org/gmane.linux.bios/71476 <pre>the following patch was just integrated into master: commit 6c323041f289d4453f3d97413ca402276f76f089 Author: Marc Jones &lt;marc.jones&lt; at &gt;se-eng.com&gt; Date: Fri May 25 12:20:10 2012 -0600 Fix typo on Persimmon #if CONFIG_HAVE_ACPI_RESUME Stupid typo: APCI instead of ACPI in Persimmon. Change-Id: I6fd7f091cf1f5c4c0e1b57c21553dab93b545eab Signed-off-by: Marc Jones &lt;marc.jones&lt; at &gt;se-eng.com&gt; Build-Tested: build bot (Jenkins) at Fri May 25 21:08:33 2012, giving +1 See http://review.coreboot.org/1054 for details. -gerrit </pre> gerrit< at >coreboot.org 2012-05-25T19:24:22 http://permalink.gmane.org/gmane.linux.bios/71475 <pre>Martin Roth (martin&lt; at &gt;se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1055 -gerrit commit 1a649e859f956360dbb01b1e5e10fc6ab99f4dbd Author: Martin Roth &lt;martin&lt; at &gt;se-eng.com&gt; Date: Fri May 25 12:23:32 2012 -0600 Update SB800 CIMX FADT - Add #define to allow the FADT PM Profile to be overridden. - Change the location of the PMA_CNT_BLOCK_ADDRESS to match current documentation. - cst_cnt should be 0 if smi_cmd == 0 - add a couple of default access sizes. - Add a couple of #define values for unsupported C2 &amp; C3 entries. - Add PM Profile override value into amd/persimmon platform. This does not use the #defines in acpi.h so that the files that include this don't all need to start including acpi.h. Change-Id: Ib11ef8f9346d42fcf653fae6e2752d62a40a3094 Signed-off-by: Martin L Roth &lt;martin&lt; at &gt;se-eng.com&gt; --- src/arch/x86/include/arch/acpi.h | 4 +++ src/mainboard/amd/persimmon/plat</pre> Martin Roth 2012-05-25T18:54:12 http://permalink.gmane.org/gmane.linux.bios/71474 <pre>Martin Roth (martin&lt; at &gt;se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1055 -gerrit commit 77659fd429a1aa44c5089995ebb9566cfce034dc Author: Martin Roth &lt;martin&lt; at &gt;se-eng.com&gt; Date: Fri May 25 12:23:32 2012 -0600 Update SB800 CIMX FADT - Add #define to allow the FADT PM Profile to be overridden. - Change the location of the PMA_CNT_BLOCK_ADDRESS to match current documentation. - cst_cnt should be 0 if smi_cmd == 0 - add a couple of default access sizes. - Add a couple of #define values for unsupported C2 &amp; C3 entries. - Add PM Profile override value into amd/persimmon platform. This does not use the #defines in acpi.h so that the files that include this don't all need to start including acpi.h. Change-Id: Ib11ef8f9346d42fcf653fae6e2752d62a40a3094 Signed-off-by: Martin L Roth &lt;martin&lt; at &gt;se-eng.com&gt; --- src/arch/x86/include/arch/acpi.h | 4 +++ src/mainboard/amd/persimmon/plat</pre> Martin Roth 2012-05-25T18:42:16 http://permalink.gmane.org/gmane.linux.bios/71473 <pre>Marc Jones (marcj303&lt; at &gt;gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1054 -gerrit commit 6c323041f289d4453f3d97413ca402276f76f089 Author: Marc Jones &lt;marc.jones&lt; at &gt;se-eng.com&gt; Date: Fri May 25 12:20:10 2012 -0600 Fix typo on Persimmon #if CONFIG_HAVE_ACPI_RESUME Stupid typo: APCI instead of ACPI in Persimmon. Change-Id: I6fd7f091cf1f5c4c0e1b57c21553dab93b545eab Signed-off-by: Marc Jones &lt;marc.jones&lt; at &gt;se-eng.com&gt; --- src/mainboard/amd/persimmon/agesawrapper.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mainboard/amd/persimmon/agesawrapper.c b/src/mainboard/amd/persimmon/agesawrapper.c index 195ff54..779e198 100644 --- a/src/mainboard/amd/persimmon/agesawrapper.c +++ b/src/mainboard/amd/persimmon/agesawrapper.c &lt; at &gt;&lt; at &gt; -253,7 +253,7 &lt; at &gt;&lt; at &gt; UINT32 GetHeapBase( { UINT32 heap; -#if CONFIG_HAVE_APCI_RESUME +#if CONFIG_HAVE_ACPI_RESUME /* Both romstage and ramstage has this S3 detect. */ if (acpi_get_sl</pre> Marc Jones 2012-05-25T18:34:30 http://permalink.gmane.org/gmane.linux.bios/71472 <pre>Marc Jones (marcj303&lt; at &gt;gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1054 -gerrit commit 4db66508c3410cce30f80af03cd82d5a4960a83b Author: Marc Jones &lt;marc.jones&lt; at &gt;se-eng.com&gt; Date: Fri May 25 12:20:10 2012 -0600 Fix typo on PennStation #if CONFIG_HAVE_ACPI_RESUME Stupid typo: APCI instead of ACPI in PennStation. Change-Id: I6fd7f091cf1f5c4c0e1b57c21553dab93b545eab Signed-off-by: Marc Jones &lt;marc.jones&lt; at &gt;se-eng.com&gt; --- src/mainboard/amd/persimmon/agesawrapper.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mainboard/amd/persimmon/agesawrapper.c b/src/mainboard/amd/persimmon/agesawrapper.c index 195ff54..779e198 100644 --- a/src/mainboard/amd/persimmon/agesawrapper.c +++ b/src/mainboard/amd/persimmon/agesawrapper.c &lt; at &gt;&lt; at &gt; -253,7 +253,7 &lt; at &gt;&lt; at &gt; UINT32 GetHeapBase( { UINT32 heap; -#if CONFIG_HAVE_APCI_RESUME +#if CONFIG_HAVE_ACPI_RESUME /* Both romstage and ramstage has this S3 detect. */ if (acpi_ge</pre> Marc Jones 2012-05-25T18:23:57 Search the mailing list at Gmane query http://search.gmane.org/?group=$group=gmane.linux.bios