http://blog.gmane.org/gmane.linux.uclinux.devel hourly 1 1901-01-01T00:00+00:00 http://gmane.org/img/gmane-25t.png http://gmane.org http://permalink.gmane.org/gmane.linux.uclinux.devel/20462 <pre>Hi Steven, On 24/05/12 07:35, Steven King wrote: I would probably group all the ColdFire defines together. But that is a pretty small detail really. Otherwise I am fine with this: Acked-by: Greg Ungerer &lt;gerg&lt; at &gt;uclinux.org&gt; Regards Greg </pre> Greg Ungerer 2012-05-25T06:08:25 http://permalink.gmane.org/gmane.linux.uclinux.devel/20461 <pre>Hi Steven, On 24/05/12 07:52, Steven King wrote: So I see that the iMX guys have used a device type prefix here for the fec name. Does it make any sense to use something like that for the 5441x as well? So "5441x-fec"? Or will we just not need to distinguish it this way? Otherwise the patch looks good. Regards Greg </pre> Greg Ungerer 2012-05-25T06:05:31 http://permalink.gmane.org/gmane.linux.uclinux.devel/20460 <pre>Hi Steven, On 23/05/12 12:03, Steven King wrote: What a wacky Soc. I wonder what people are using them in :-) This looks pretty good overall. Only a couple of comments below. Otherwise I'd like to commit it to the m68knommu git tree (after the current merge window closes). Maybe we should make this "depends on !MMU" until we really do have the MMU support in place. There is pretty much no way it will compile and work with the MMU enabled yet. I like clean ups... But they should go in separate patches of their own. What if the compiler supports neither -54455 or -mcfv4e? Admittedly it would have to be a old compiler. But the thinking here was that the second arg is the last resort fallback if the compiler doesn't support the ideal compiler switch. Regards Greg ------------------------------------------------------------------------ Greg Ungerer -- Principal Engineer EMAIL: gerg&lt; at &gt;snapgear.com SnapGear Group, McAfee PHONE: +61 7 3435 2888 8 Gardner Close FAX: +61 7 3217 5323 Milton, QLD, 4064, Australia WEB: http://www.SnapGear.com _______________________________________________ uClinux-dev mailing list uClinux-dev&lt; at &gt;uclinux.org http://mailman.uclinux.org/mailman/listinfo/uclinux-dev This message was resent by uclinux-dev&lt; at &gt;uclinux.org To unsubscribe see: http://mailman.uclinux.org/mailman/options/uclinux-dev </pre> Greg Ungerer 2012-05-25T05:55:32 http://permalink.gmane.org/gmane.linux.uclinux.devel/20458 <pre>The m5441x enet-fec aren't quite the same as the fec found on other Coldfire parts, so we need a quirk to help the fec do the right thing and on the twr-mcf5441x atleast, we need to force the phy into RMII mode. Signed-off-by: Steven King &lt;sfking&lt; at &gt;fdwdc.com&gt; --- arch/m68k/platform/coldfire/device.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/arch/m68k/platform/coldfire/device.c b/arch/m68k/platform/coldfire/device.c index 11ecd23..ab88b69 100644 --- a/arch/m68k/platform/coldfire/device.c +++ b/arch/m68k/platform/coldfire/device.c &lt; at &gt;&lt; at &gt; -13,6 +13,7 &lt; at &gt;&lt; at &gt; #include &lt;linux/io.h&gt; #include &lt;linux/spi/spi.h&gt; #include &lt;linux/gpio.h&gt; +#include &lt;linux/fec.h&gt; #include &lt;asm/traps.h&gt; #include &lt;asm/coldfire.h&gt; #include &lt;asm/mcfsim.h&gt; &lt; at &gt;&lt; at &gt; -89,6 +90,18 &lt; at &gt;&lt; at &gt; static struct platform_device mcf_uart = { }; #ifdef CONFIG_FEC + +#ifdef CONFIG_M5441x +#define FEC_NAME"enet-fec" +static struct fec_platform_data fec_pdata = { +.phy= PHY_INTERFACE_MODE_RMII, +}; +#define FEC_PDATA(&amp;fec_pdata) +#else +#define FEC_NAME"fec" +#define FEC_PDATANULL +#endif + /* *Some ColdFire cores contain the Fast Ethernet Controller (FEC) *block. It is Freescale's own hardware block. Some ColdFires &lt; at &gt;&lt; at &gt; -118,10 +131,11 &lt; at &gt;&lt; at &gt; static struct resource mcf_fec0_resources[] = { }; static struct platform_device mcf_fec0 = { -.name= "fec", +.name= FEC_NAME, .id= 0, .num_resources= ARRAY_SIZE(mcf_fec0_resources), .resource= mcf_fec0_resources, +.dev.platform_data= FEC_PDATA, }; #ifdef MCFFEC_BASE1 &lt; at &gt;&lt; at &gt; -149,10 +163,11 &lt; at &gt;&lt; at &gt; static struct resource mcf_fec1_resources[] = { }; static struct platform_device mcf_fec1 = { -.name= "fec", +.name= FEC_NAME, .id= 1, .num_resources= ARRAY_SIZE(mcf_fec1_resources), .resource= mcf_fec1_resources, +.dev.platform_data= FEC_PDATA, }; #endif /* MCFFEC_BASE1 */ #endif /* CONFIG_FEC */ _______________________________________________ uClinux-dev mailing list uClinux-dev&lt; at &gt;uclinux.org http://mailman.uclinux.org/mailman/listinfo/uclinux-dev This message was resent by uclinux-dev&lt; at &gt;uclinux.org To unsubscribe see: http://mailman.uclinux.org/mailman/options/uclinux-dev </pre> Steven King 2012-05-23T21:52:40 http://permalink.gmane.org/gmane.linux.uclinux.devel/20456 <pre> Ok, the 54xx fec drivers would not help then. Best regards Philippe _______________________________________________ uClinux-dev mailing list uClinux-dev&lt; at &gt;uclinux.org http://mailman.uclinux.org/mailman/listinfo/uclinux-dev This message was resent by uclinux-dev&lt; at &gt;uclinux.org To unsubscribe see: http://mailman.uclinux.org/mailman/options/uclinux-dev </pre> Philippe De Muyter 2012-05-23T08:55:04 http://permalink.gmane.org/gmane.linux.uclinux.devel/20455 <pre> Are they identical to the fec's of the 548x ? I have drivers for them (actually they came from the freescale port for 2.6.25, but I have cleaned them up, made them use phylib, and made them current for 2.6.37). I don't know if they still would be compatible with 3.5. Philippe _______________________________________________ uClinux-dev mailing list uClinux-dev&lt; at &gt;uclinux.org http://mailman.uclinux.org/mailman/listinfo/uclinux-dev This message was resent by uclinux-dev&lt; at &gt;uclinux.org To unsubscribe see: http://mailman.uclinux.org/mailman/options/uclinux-dev </pre> Philippe De Muyter 2012-05-23T07:38:46 http://permalink.gmane.org/gmane.linux.uclinux.devel/20454 <pre>The 5441x (54410/54415/54416/54417/54418) is similar to the 532x in the same way the 532x is similar to the 5208; it doesn't have either IPSBAR nor MBAR, instead everything resides at a fixed address. Many of the registers common between the 5441x and the 532x live at the same address as the 532x, but of course the 5441x has a v4e core, cache and mmu, along with 10 uarts! 6 i2c controllers, 4 dma capable spi controllers, usb and much more. This patch is just a quick and dirty hack to get it booting on the twr-mcf5441x board. Its currently nommu only (well, I havent even tried it with the mmu), It doesnt include support for the 2 fec controllers, the ones on the 5441x are just slightly different in some non obvious way so they dont quite work yet. Signed-off-by: Steven King &lt;sfking&lt; at &gt;fdwdc.com&gt; --- arch/m68k/Kconfig.cpu | 7 + arch/m68k/Kconfig.machine | 1 - arch/m68k/Makefile | 1 + arch/m68k/include/asm/gpio.h | 11 +- arch/m68k/include/asm/m5441xsim.h | 252 +++++++++++++++++++++++++++++++ arch/m68k/include/asm/m54xxacr.h | 4 + arch/m68k/include/asm/mcfsim.h | 2 + arch/m68k/include/asm/mcftimer.h | 2 +- arch/m68k/platform/coldfire/Makefile | 1 + arch/m68k/platform/coldfire/device.c | 38 ++++- arch/m68k/platform/coldfire/intc-simr.c | 24 ++- arch/m68k/platform/coldfire/m5441x.c | 51 +++++++ arch/m68k/platform/coldfire/timers.c | 2 +- 13 files changed, 382 insertions(+), 14 deletions(-) diff --git a/arch/m68k/Kconfig.cpu b/arch/m68k/Kconfig.cpu index 8a9c767..3221433 100644 --- a/arch/m68k/Kconfig.cpu +++ b/arch/m68k/Kconfig.cpu &lt; at &gt;&lt; at &gt; -252,6 +252,13 &lt; at &gt;&lt; at &gt; config M548x help Freescale ColdFire 5480/5481/5482/5483/5484/5485 processor support. +config M5441x +bool "MCF5441x" +select MMU_COLDFIRE if MMU +select HAVE_CACHE_CB +help + Freescale Coldfire 54410/54415/54416/54417/54418 processor support. + endif # COLDFIRE diff --git a/arch/m68k/Kconfig.machine b/arch/m68k/Kconfig.machine index 7cdf6b0..7031173 100644 --- a/arch/m68k/Kconfig.machine +++ b/arch/m68k/Kconfig.machine &lt; at &gt;&lt; at &gt; -428,7 +428,6 &lt; at &gt;&lt; at &gt; config SAVANTrosie1 help Support for the Savant Rosie1 board. - if !MMU || COLDFIRE comment "Machine Options" diff --git a/arch/m68k/Makefile b/arch/m68k/Makefile index 804f139..6940baf 100644 --- a/arch/m68k/Makefile +++ b/arch/m68k/Makefile &lt; at &gt;&lt; at &gt; -34,6 +34,7 &lt; at &gt;&lt; at &gt; cpuflags-$(CONFIG_M68030):= cpuflags-$(CONFIG_M68020):= cpuflags-$(CONFIG_M68360):= -m68332 cpuflags-$(CONFIG_M68000):= -m68000 +cpuflags-$(CONFIG_M5441x):= $(call cc-option,-mcpu=54455,-mcfv4e) cpuflags-$(CONFIG_M54xx):= $(call cc-option,-mcpu=5475,-m5200) cpuflags-$(CONFIG_M5407):= $(call cc-option,-mcpu=5407,-m5200) cpuflags-$(CONFIG_M532x):= $(call cc-option,-mcpu=532x,-m5307) diff --git a/arch/m68k/include/asm/gpio.h b/arch/m68k/include/asm/gpio.h index 00d0071..f5b462a 100644 --- a/arch/m68k/include/asm/gpio.h +++ b/arch/m68k/include/asm/gpio.h &lt; at &gt;&lt; at &gt; -37,7 +37,8 &lt; at &gt;&lt; at &gt; #if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \ defined(CONFIG_M520x) || defined(CONFIG_M523x) || \ defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ - defined(CONFIG_M532x) || defined(CONFIG_M54xx) + defined(CONFIG_M532x) || defined(CONFIG_M54xx) || \ + defined(CONFIG_M5441x) /* These parts have GPIO organized by 8 bit ports */ &lt; at &gt;&lt; at &gt; -70,7 +71,8 &lt; at &gt;&lt; at &gt; #define mcfgpio_port(gpio)((gpio) / MCFGPIO_PORTSIZE) #if defined(CONFIG_M520x) || defined(CONFIG_M523x) || \ - defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x) + defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ + defined(CONFIG_M532x) || defined(CONFIG_M5441x) /* * These parts have an 'Edge' Port module (external interrupt/GPIO) which uses * read-modify-write to change an output and a GPIO module which has separate &lt; at &gt;&lt; at &gt; -82,6 +84,11 &lt; at &gt;&lt; at &gt; * read-modify-write as well as those controlled by the EPORT and GPIO modules. */ #define MCFGPIO_SCR_START40 +#elif defined(CONFIG_M5441x) +/* + * The 5441x EPORT can't be used for GPIO. + */ +#define MCFGPIO_SCR_START0 #else #define MCFGPIO_SCR_START8 #endif diff --git a/arch/m68k/include/asm/m5441xsim.h b/arch/m68k/include/asm/m5441xsim.h new file mode 100644 index 0000000..a7900a5 --- /dev/null +++ b/arch/m68k/include/asm/m5441xsim.h &lt; at &gt;&lt; at &gt; -0,0 +1,252 &lt; at &gt;&lt; at &gt; +/* + *m5441xsim.h -- Coldfire 5441x register definitions + * + *(C) Copyright 2012, Steven King &lt;sfking&lt; at &gt;fdwdc.com&gt; +*/ + +#ifndef m5441xsim_h +#define m5441xsim_h + +#define CPU_NAME"COLDFIRE(m5441x)" +#define CPU_INSTR_PER_JIFFY2 +#define MCF_BUSCLK(MCF_CLK / 2) + +#include &lt;asm/m54xxacr.h&gt; + +/* + * Reset Controller Module. + */ + +#defineMCF_RCR0xFC0A0000 +#defineMCF_RSR0xFC0A0001 + +#defineMCF_RCR_SWRESET0x80/* Software reset bit */ +#defineMCF_RCR_FRCSTOUT0x40/* Force external reset */ + +/* + * Interrupt Controller Modules. + */ +/* the 5441x have 3 interrupt controllers, each control 64 interrupts */ +#define MCFINT_VECBASE64 +#define MCFINT0_VECBASEMCFINT_VECBASE +#define MCFINT1_VECBASE(MCFINT0_VECBASE + 64) +#define MCFINT2_VECBASE(MCFINT1_VECBASE + 64) + +/* interrupt controller 0 */ +#define MCFINTC0_SIMR0xfc04801c +#define MCFINTC0_CIMR0xfc04801d +#defineMCFINTC0_ICR00xfc048040 +/* interrupt controller 1 */ +#define MCFINTC1_SIMR0xfc04c01c +#define MCFINTC1_CIMR0xfc04c01d +#defineMCFINTC1_ICR00xfc04c040 +/* interrupt controller 2 */ +#define MCFINTC2_SIMR0xfc05001c +#define MCFINTC2_CIMR0xfc05001d +#defineMCFINTC2_ICR00xfc050040 + +/* on interrupt controller 0 */ +#define MCFINT0_EPORT01 +#define MCFINT0_UART026 +#define MCFINT0_UART127 +#define MCFINT0_UART228 +#define MCFINT0_UART329 +#define MCFINT0_I2C030 +#define MCFINT0_DSPI031 + +#define MCFINT0_TIMER032 +#define MCFINT0_TIMER133 +#define MCFINT0_TIMER234 +#define MCFINT0_TIMER335 + +#define MCFINT0_FECRX036 +#define MCFINT0_FECTX040 +#define MCFINT0_FECENTC042 + +#define MCFINT0_FECRX149 +#define MCFINT0_FECTX153 +#define MCFINT0_FECENTC155 + +/* on interrupt controller 1 */ +#define MCFINT1_UART448 +#define MCFINT1_UART549 +#define MCFINT1_UART650 +#define MCFINT1_UART751 +#define MCFINT1_UART852 +#define MCFINT1_UART953 +#define MCFINT1_DSPI154 +#define MCFINT1_DSPI255 +#define MCFINT1_DSPI356 +#define MCFINT1_I2C157 +#define MCFINT1_I2C258 +#define MCFINT1_I2C359 +#define MCFINT1_I2C460 +#define MCFINT1_I2C561 + +/* on interrupt controller 2 */ +#define MCFINTC2_RTC26 + +/* + * TIMER module. + */ +#define MCFTIMER_BASE10xFC070000/* Base address of TIMER1 */ +#define MCFTIMER_BASE20xFC074000/* Base address of TIMER2 */ +#define MCFTIMER_BASE30xFC078000/* Base address of TIMER3 */ +#define MCFTIMER_BASE40xFC07C000/* Base address of TIMER4 */ + +#define MCF_IRQ_TIMER(MCFINT0_VECBASE + MCFINT0_TIMER0) +#define MCF_IRQ_PROFILER(MCFINT0_VECBASE + MCFINT0_TIMER1) + +/* + * UART module. + */ +#define MCFUART_BASE00xfc060000/* Base address of UART0 */ +#define MCFUART_BASE10xfc064000/* Base address of UART1 */ +#define MCFUART_BASE20xfc068000/* Base address of UART2 */ +#define MCFUART_BASE30xfc06c000/* Base address of UART3 */ +#define MCFUART_BASE40xec060000/* Base address of UART4 */ +#define MCFUART_BASE50xec064000/* Base address of UART5 */ +#define MCFUART_BASE60xec068000/* Base address of UART6 */ +#define MCFUART_BASE70xec06c000/* Base address of UART7 */ +#define MCFUART_BASE80xec070000/* Base address of UART8 */ +#define MCFUART_BASE90xec074000/* Base address of UART9 */ + +#define MCF_IRQ_UART0(MCFINT0_VECBASE + MCFINT0_UART0) +#define MCF_IRQ_UART1(MCFINT0_VECBASE + MCFINT0_UART1) +#define MCF_IRQ_UART2(MCFINT0_VECBASE + MCFINT0_UART2) +#define MCF_IRQ_UART3(MCFINT0_VECBASE + MCFINT0_UART3) +#define MCF_IRQ_UART4(MCFINT1_VECBASE + MCFINT1_UART4) +#define MCF_IRQ_UART5(MCFINT1_VECBASE + MCFINT1_UART5) +#define MCF_IRQ_UART6(MCFINT1_VECBASE + MCFINT1_UART6) +#define MCF_IRQ_UART7(MCFINT1_VECBASE + MCFINT1_UART7) +#define MCF_IRQ_UART8(MCFINT1_VECBASE + MCFINT1_UART8) +#define MCF_IRQ_UART9(MCFINT1_VECBASE + MCFINT1_UART9) +/* + * FEC modules. + */ +#define MCFFEC_BASE00xfc0d4004 +#define MCFFEC_SIZE00x800 +#define MCF_IRQ_FECRX0(MCFINT0_VECBASE + MCFINT0_FECRX0) +#define MCF_IRQ_FECTX0(MCFINT0_VECBASE + MCFINT0_FECTX0) +#define MCF_IRQ_FECENTC0(MCFINT0_VECBASE + MCFINT0_FECENTC0) + +#define MCFFEC_BASE10xfc0d8004 +#define MCFFEC_SIZE10x800 +#define MCF_IRQ_FECRX1(MCFINT0_VECBASE + MCFINT0_FECRX1) +#define MCF_IRQ_FECTX1(MCFINT0_VECBASE + MCFINT0_FECTX1) +#define MCF_IRQ_FECENTC1(MCFINT0_VECBASE + MCFINT0_FECENTC1) +/* + * I2C modules. + */ +#define MCFI2C_BASE00xfc058000 +#define MCFI2C_SIZE00x20 +#define MCFI2C_BASE10xfc038000 +#define MCFI2C_SIZE10x20 +#define MCFI2C_BASE20xfc010000 +#define MCFI2C_SIZE20x20 +#define MCFI2C_BASE30xfc014000 +#define MCFI2C_SIZE30x20 +#define MCFI2C_BASE40xfc018000 +#define MCFI2C_SIZE40x20 +#define MCFI2C_BASE50xfc01c000 +#define MCFI2C_SIZE50x20 + +#define MCF_IRQ_I2C0(MCFINT0_VECBASE + MCFINT0_I2C0) +#define MCF_IRQ_I2C1(MCFINT1_VECBASE + MCFINT1_I2C1) +#define MCF_IRQ_I2C2(MCFINT1_VECBASE + MCFINT1_I2C2) +#define MCF_IRQ_I2C3(MCFINT1_VECBASE + MCFINT1_I2C3) +#define MCF_IRQ_I2C4(MCFINT1_VECBASE + MCFINT1_I2C4) +#define MCF_IRQ_I2C5(MCFINT1_VECBASE + MCFINT1_I2C5) +/* + * EPORT Module. + */ +#define MCFEPORT_EPPAR0xfc090000 +#define MCFEPORT_EPIER0xfc090003 +#define MCFEPORT_EPFR0xfc090006 + +/* + * GPIO Module. + */ +#define MCFGPIO_PODR_A0xec094000 +#define MCFGPIO_PODR_B0xec094001 +#define MCFGPIO_PODR_C0xec094002 +#define MCFGPIO_PODR_D0xec094003 +#define MCFGPIO_PODR_E0xec094004 +#define MCFGPIO_PODR_F0xec094005 +#define MCFGPIO_PODR_G0xec094006 +#define MCFGPIO_PODR_H0xec094007 +#define MCFGPIO_PODR_I0xec094008 +#define MCFGPIO_PODR_J0xec094009 +#define MCFGPIO_PODR_K0xec09400a + +#define MCFGPIO_PDDR_A0xec09400c +#define MCFGPIO_PDDR_B0xec09400d +#define MCFGPIO_PDDR_C0xec09400e +#define MCFGPIO_PDDR_D0xec09400f +#define MCFGPIO_PDDR_E0xec094010 +#define MCFGPIO_PDDR_F0xec094011 +#define MCFGPIO_PDDR_G0xec094012 +#define MCFGPIO_PDDR_H0xec094013 +#define MCFGPIO_PDDR_I0xec094014 +#define MCFGPIO_PDDR_J0xec094015 +#define MCFGPIO_PDDR_K0xec094016 + +#define MCFGPIO_PPDSDR_A0xec094018 +#define MCFGPIO_PPDSDR_B0xec094019 +#define MCFGPIO_PPDSDR_C0xec09401a +#define MCFGPIO_PPDSDR_D0xec09401b +#define MCFGPIO_PPDSDR_E0xec09401c +#define MCFGPIO_PPDSDR_F0xec09401d +#define MCFGPIO_PPDSDR_G0xec09401e +#define MCFGPIO_PPDSDR_H0xec09401f +#define MCFGPIO_PPDSDR_I0xec094020 +#define MCFGPIO_PPDSDR_J0xec094021 +#define MCFGPIO_PPDSDR_K0xec094022 + +#define MCFGPIO_PCLRR_A0xec094024 +#define MCFGPIO_PCLRR_B0xec094025 +#define MCFGPIO_PCLRR_C0xec094026 +#define MCFGPIO_PCLRR_D0xec094027 +#define MCFGPIO_PCLRR_E0xec094028 +#define MCFGPIO_PCLRR_F0xec094029 +#define MCFGPIO_PCLRR_G0xec09402a +#define MCFGPIO_PCLRR_H0xec09402b +#define MCFGPIO_PCLRR_I0xec09402c +#define MCFGPIO_PCLRR_J0xec09402d +#define MCFGPIO_PCLRR_K0xec09402e + +#define MCFGPIO_PAR_FBCTL0xec094048 +#define MCFGPIO_PAR_BE0xec094049 +#define MCFGPIO_PAR_CS0xec09404a +#define MCFGPIO_PAR_CANI2C0xec09404b +#define MCFGPIO_PAR_IRQ0H0xec09404c +#define MCFGPIO_PAR_IRQ0L0xec09404d +#define MCFGPIO_PAR_DSPIOWH0xec09404e +#define MCFGPIO_PAR_DSPIOWL0xec09404f +#define MCFGPIO_PAR_TIMER0xec094050 +#define MCFGPIO_PAR_UART20xec094051 +#define MCFGPIO_PAR_UART10xec094052 +#define MCFGPIO_PAR_UART00xec094053 +#define MCFGPIO_PAR_SDHCH0xec094054 +#define MCFGPIO_PAR_SDHCL0xec094055 +#define MCFGPIO_PAR_SIMP0H0xec094056 +#define MCFGPIO_PAR_SIMP0L0xec094057 +#define MCFGPIO_PAR_SSI0H0xec094058 +#define MCFGPIO_PAR_SSI0L0xec094059 +#define MCFGPIO_PAR_DEBUGH10xec09405a +#define MCFGPIO_PAR_DEBUGH00xec09405b +#define MCFGPIO_PAR_DEBUGl0xec09405c +#define MCFGPIO_PAR_FEC0xec09405e + +/* generalization for generic gpio support */ +#define MCFGPIO_PODRMCFGPIO_PODR_A +#define MCFGPIO_PDDRMCFGPIO_PDDR_A +#define MCFGPIO_PPDRMCFGPIO_PPDSDR_A +#define MCFGPIO_SETRMCFGPIO_PPDSDR_A +#define MCFGPIO_CLRRMCFGPIO_PCLRR_A + +#define MCFGPIO_IRQ_MAX8 +#define MCFGPIO_IRQ_VECBASEMCFINT_VECBASE +#define MCFGPIO_PIN_MAX112 + +#endif /* m5441xsim_h */ diff --git a/arch/m68k/include/asm/m54xxacr.h b/arch/m68k/include/asm/m54xxacr.h index 47906aa..192bbfe 100644 --- a/arch/m68k/include/asm/m54xxacr.h +++ b/arch/m68k/include/asm/m54xxacr.h &lt; at &gt;&lt; at &gt; -55,6 +55,10 &lt; at &gt;&lt; at &gt; #define ICACHE_SIZE 0x8000/* instruction - 32k */ #define DCACHE_SIZE 0x8000/* data - 32k */ +#elif defined(CONFIG_M5441x) + +#define ICACHE_SIZE 0x2000/* instruction - 8k */ +#define DCACHE_SIZE 0x2000/* data - 8k */ #endif #define CACHE_LINE_SIZE 0x0010/* 16 bytes */ diff --git a/arch/m68k/include/asm/mcfsim.h b/arch/m68k/include/asm/mcfsim.h index ebd0304..6e5a8cd 100644 --- a/arch/m68k/include/asm/mcfsim.h +++ b/arch/m68k/include/asm/mcfsim.h &lt; at &gt;&lt; at &gt; -43,6 +43,8 &lt; at &gt;&lt; at &gt; #include &lt;asm/mcfintc.h&gt; #elif defined(CONFIG_M54xx) #include &lt;asm/m54xxsim.h&gt; +#elif defined(CONFIG_M5441x) +#include &lt;asm/m5441xsim.h&gt; #endif /****************************************************************************/ diff --git a/arch/m68k/include/asm/mcftimer.h b/arch/m68k/include/asm/mcftimer.h index 351c272..da2fa43 100644 --- a/arch/m68k/include/asm/mcftimer.h +++ b/arch/m68k/include/asm/mcftimer.h &lt; at &gt;&lt; at &gt; -19,7 +19,7 &lt; at &gt;&lt; at &gt; #defineMCFTIMER_TRR0x04/* Timer Reference (r/w) */ #defineMCFTIMER_TCR0x08/* Timer Capture reg (r/w) */ #defineMCFTIMER_TCN0x0C/* Timer Counter reg (r/w) */ -#if defined(CONFIG_M532x) +#if defined(CONFIG_M532x) || defined(CONFIG_M5441x) #defineMCFTIMER_TER0x03/* Timer Event reg (r/w) */ #else #defineMCFTIMER_TER0x11/* Timer Event reg (r/w) */ diff --git a/arch/m68k/platform/coldfire/Makefile b/arch/m68k/platform/coldfire/Makefile index 76d389d..51e85e5 100644 --- a/arch/m68k/platform/coldfire/Makefile +++ b/arch/m68k/platform/coldfire/Makefile &lt; at &gt;&lt; at &gt; -27,6 +27,7 &lt; at &gt;&lt; at &gt; obj-$(CONFIG_M5307)+= m5307.o timers.o intc.o reset.o obj-$(CONFIG_M532x)+= m532x.o timers.o intc-simr.o reset.o obj-$(CONFIG_M5407)+= m5407.o timers.o intc.o reset.o obj-$(CONFIG_M54xx)+= m54xx.o sltimers.o intc-2.o +obj-$(CONFIG_M5441x)+= m5441x.o timers.o intc-simr.o reset.o obj-$(CONFIG_NETtel)+= nettel.o obj-$(CONFIG_CLEOPATRA)+= nettel.o diff --git a/arch/m68k/platform/coldfire/device.c b/arch/m68k/platform/coldfire/device.c index 3aa77dd..11ecd23 100644 --- a/arch/m68k/platform/coldfire/device.c +++ b/arch/m68k/platform/coldfire/device.c &lt; at &gt;&lt; at &gt; -20,7 +20,7 &lt; at &gt;&lt; at &gt; #include &lt;asm/mcfqspi.h&gt; /* - *All current ColdFire parts contain from 2, 3 or 4 UARTS. + *All current ColdFire parts contain from 2, 3, 4 or 10 UARTS. */ static struct mcf_platform_uart mcf_uart_platform_data[] = { { &lt; at &gt;&lt; at &gt; -43,6 +43,42 &lt; at &gt;&lt; at &gt; static struct mcf_platform_uart mcf_uart_platform_data[] = { .irq= MCF_IRQ_UART3, }, #endif +#ifdef MCFUART_BASE4 +{ +.mapbase= MCFUART_BASE4, +.irq= MCF_IRQ_UART4, +}, +#endif +#ifdef MCFUART_BASE5 +{ +.mapbase= MCFUART_BASE5, +.irq= MCF_IRQ_UART5, +}, +#endif +#ifdef MCFUART_BASE6 +{ +.mapbase= MCFUART_BASE6, +.irq= MCF_IRQ_UART6, +}, +#endif +#ifdef MCFUART_BASE7 +{ +.mapbase= MCFUART_BASE7, +.irq= MCF_IRQ_UART7, +}, +#endif +#ifdef MCFUART_BASE8 +{ +.mapbase= MCFUART_BASE8, +.irq= MCF_IRQ_UART8, +}, +#endif +#ifdef MCFUART_BASE9 +{ +.mapbase= MCFUART_BASE9, +.irq= MCF_IRQ_UART9, +}, +#endif { }, }; diff --git a/arch/m68k/platform/coldfire/intc-simr.c b/arch/m68k/platform/coldfire/intc-simr.c index 650d52e..81571fb 100644 --- a/arch/m68k/platform/coldfire/intc-simr.c +++ b/arch/m68k/platform/coldfire/intc-simr.c &lt; at &gt;&lt; at &gt; -59,16 +59,18 &lt; at &gt;&lt; at &gt; static unsigned int inline irq2ebit(unsigned int irq) #endif /* - *There maybe one or two interrupt control units, each has 64 - *interrupts. If there is no second unit then MCFINTC1_* defines - *will be 0 (and code for them optimized away). + *There maybe one, two or three interrupt control units, each has 64 + *interrupts. If there is no second or third unit then MCFINTC1_* or + *MCFINTC2_* defines will be 0 (and code for them optimized away). */ static void intc_irq_mask(struct irq_data *d) { unsigned int irq = d-&gt;irq - MCFINT_VECBASE; -if (MCFINTC1_SIMR &amp;&amp; (irq &gt; 64)) +if (MCFINTC2_SIMR &amp;&amp; (irq &gt; 128)) +__raw_writeb(irq - 128, MCFINTC2_SIMR); +else if (MCFINTC1_SIMR &amp;&amp; (irq &gt; 64)) __raw_writeb(irq - 64, MCFINTC1_SIMR); else __raw_writeb(irq, MCFINTC0_SIMR); &lt; at &gt;&lt; at &gt; -78,7 +80,9 &lt; at &gt;&lt; at &gt; static void intc_irq_unmask(struct irq_data *d) { unsigned int irq = d-&gt;irq - MCFINT_VECBASE; -if (MCFINTC1_CIMR &amp;&amp; (irq &gt; 64)) +if (MCFINTC2_SIMR &amp;&amp; (irq &gt; 128)) +__raw_writeb(irq - 128, MCFINTC2_SIMR); +else if (MCFINTC1_CIMR &amp;&amp; (irq &gt; 64)) __raw_writeb(irq - 64, MCFINTC1_CIMR); else __raw_writeb(irq, MCFINTC0_CIMR); &lt; at &gt;&lt; at &gt; -99,9 +103,11 &lt; at &gt;&lt; at &gt; static unsigned int intc_irq_startup(struct irq_data *d) unsigned int ebit = irq2ebit(irq); u8 v; +#if defined(MCFEPORT_EPDDR) /* Set EPORT line as input */ v = __raw_readb(MCFEPORT_EPDDR); __raw_writeb(v &amp; ~(0x1 &lt;&lt; ebit), MCFEPORT_EPDDR); +#endif /* Set EPORT line as interrupt source */ v = __raw_readb(MCFEPORT_EPIER); &lt; at &gt;&lt; at &gt; -109,12 +115,13 &lt; at &gt;&lt; at &gt; static unsigned int intc_irq_startup(struct irq_data *d) } irq -= MCFINT_VECBASE; -if (MCFINTC1_ICR0 &amp;&amp; (irq &gt; 64)) +if (MCFINTC2_ICR0 &amp;&amp; (irq &gt; 128)) +__raw_writeb(5, MCFINTC2_ICR0 + irq - 128); +else if (MCFINTC1_ICR0 &amp;&amp; (irq &gt; 64)) __raw_writeb(5, MCFINTC1_ICR0 + irq - 64); else __raw_writeb(5, MCFINTC0_ICR0 + irq); - intc_irq_unmask(d); return 0; } &lt; at &gt;&lt; at &gt; -176,7 +183,8 &lt; at &gt;&lt; at &gt; void __init init_IRQ(void) if (MCFINTC1_SIMR) __raw_writeb(0xff, MCFINTC1_SIMR); -eirq = MCFINT_VECBASE + 64 + (MCFINTC1_ICR0 ? 64 : 0); +eirq = MCFINT_VECBASE + 64 + (MCFINTC1_ICR0 ? 64 : 0) + +(MCFINTC2_ICR0 ? 64 : 0); for (irq = MCFINT_VECBASE; (irq &lt; eirq); irq++) { if ((irq &gt;= EINT1) &amp;&amp; (irq &lt;= EINT7)) irq_set_chip(irq, &amp;intc_irq_chip_edge_port); diff --git a/arch/m68k/platform/coldfire/m5441x.c b/arch/m68k/platform/coldfire/m5441x.c new file mode 100644 index 0000000..edffaff --- /dev/null +++ b/arch/m68k/platform/coldfire/m5441x.c &lt; at &gt;&lt; at &gt; -0,0 +1,51 &lt; at &gt;&lt; at &gt; +/* + *m5441x.c -- support for Coldfire m5441x processors + * + *(C) Copyright Steven King &lt;sfking&lt; at &gt;fdwdc.com&gt; + */ + +#include &lt;linux/kernel.h&gt; +#include &lt;linux/param.h&gt; +#include &lt;linux/init.h&gt; +#include &lt;linux/io.h&gt; +#include &lt;asm/machdep.h&gt; +#include &lt;asm/coldfire.h&gt; +#include &lt;asm/mcfsim.h&gt; +#include &lt;asm/mcfuart.h&gt; +#include &lt;asm/mcfdma.h&gt; +#include &lt;asm/mcfgpio.h&gt; + +struct mcf_gpio_chip mcf_gpio_chips[] = { +MCFGPF(A, 0, 8), +MCFGPF(B, 8, 8), +MCFGPF(C, 16, 8), +MCFGPF(D, 24, 8), +MCFGPF(E, 32, 8), +MCFGPF(F, 40, 8), +MCFGPF(G, 48, 8), +MCFGPF(H, 56, 8), +MCFGPF(I, 64, 8), +MCFGPF(J, 72, 8), +MCFGPF(K, 80, 8), +}; + +unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips); + +static void __init m5441x_uarts_init(void) +{ +__raw_writeb(0x0f, MCFGPIO_PAR_UART0); +__raw_writeb(0x00, MCFGPIO_PAR_UART1); +__raw_writeb(0x00, MCFGPIO_PAR_UART2); +} + +static void __init m5441x_fec_init(void) +{ +__raw_writeb(0x03, MCFGPIO_PAR_FEC); +} + +void __init config_BSP(char *commandp, int size) +{ +mach_sched_init = hw_timer_init; +m5441x_uarts_init(); +m5441x_fec_init(); +} diff --git a/arch/m68k/platform/coldfire/timers.c b/arch/m68k/platform/coldfire/timers.c index ed96ce5..0a273e7 100644 --- a/arch/m68k/platform/coldfire/timers.c +++ b/arch/m68k/platform/coldfire/timers.c &lt; at &gt;&lt; at &gt; -36,7 +36,7 &lt; at &gt;&lt; at &gt; */ void coldfire_profile_init(void); -#if defined(CONFIG_M532x) +#if defined(CONFIG_M532x) || defined(CONFIG_M5441x) #define__raw_readtrr__raw_readl #define__raw_writetrr__raw_writel #else _______________________________________________ uClinux-dev mailing list uClinux-dev&lt; at &gt;uclinux.org http://mailman.uclinux.org/mailman/listinfo/uclinux-dev This message was resent by uclinux-dev&lt; at &gt;uclinux.org To unsubscribe see: http://mailman.uclinux.org/mailman/options/uclinux-dev </pre> Steven King 2012-05-23T02:03:59 http://permalink.gmane.org/gmane.linux.uclinux.devel/20452 <pre>If we're not connecting external GPIO extenders via i2c or spi or whatever, we probably don't need GPIOLIB. If we provide an alternate implementation of the GPIOLIB functions to use when only on-chip GPIO is needed, we can change ARCH_REQUIRE_GPIOLIB to ARCH_WANTS_OPTIONAL_GPIOLIB so that GPIOLIB becomes optional. The downside is that in the GPIOLIB=n case, we lose all error checking done by gpiolib, ie multiply allocating the gpio, free'ing gpio etc., so that the only checking that can be done is if we reference a gpio on an external part. Targets that need the extra error checking can still select GPIOLIB=y. For the case where GPIOLIB=y, we can simplify the table of gpio chips to use a single chip, eliminating the tables of chips in the 5xxx.c files. The original motivation for the definition of multiple chips was to match the way many of the Coldfire variants defined their gpio as a spare array in memory. However, all this really gains us is some error checking when we request a gpio, gpiolib can check that it doesn't fall in one of the holes. If thats important, I think we can still come up with a better way of accomplishing that. Also in this patch is some general cleanup and reorganizing of the gpio header files (I'm sure I must have had a reason why I sometimes used a prefix of mcf_gpio and other times mcfgpio but for the life of me I can't think of it now). Signed-off-by: Steven King &lt;sfking&lt; at &gt;fdwdc.com&gt; --- arch/m68k/Kconfig.cpu | 2 +- arch/m68k/include/asm/gpio.h | 169 +---------------- arch/m68k/include/asm/mcfgpio.h | 329 +++++++++++++++++++++++++++------- arch/m68k/include/asm/pinmux.h | 30 ---- arch/m68k/platform/coldfire/Makefile | 2 +- arch/m68k/platform/coldfire/gpio.c | 172 +++++++++++------- arch/m68k/platform/coldfire/m5206.c | 9 - arch/m68k/platform/coldfire/m520x.c | 16 -- arch/m68k/platform/coldfire/m523x.c | 22 --- arch/m68k/platform/coldfire/m5249.c | 10 -- arch/m68k/platform/coldfire/m5272.c | 11 -- arch/m68k/platform/coldfire/m527x.c | 43 ----- arch/m68k/platform/coldfire/m528x.c | 33 +--- arch/m68k/platform/coldfire/m5307.c | 9 - arch/m68k/platform/coldfire/m532x.c | 25 --- arch/m68k/platform/coldfire/m5407.c | 9 - arch/m68k/platform/coldfire/m54xx.c | 7 - arch/m68k/platform/coldfire/pinmux.c | 28 --- 18 files changed, 375 insertions(+), 551 deletions(-) diff --git a/arch/m68k/Kconfig.cpu b/arch/m68k/Kconfig.cpu index 8a9c767..f468413 100644 --- a/arch/m68k/Kconfig.cpu +++ b/arch/m68k/Kconfig.cpu &lt; at &gt;&lt; at &gt; -23,7 +23,7 &lt; at &gt;&lt; at &gt; config M68KCLASSIC config COLDFIRE bool "Coldfire CPU family support" select GENERIC_GPIO -select ARCH_REQUIRE_GPIOLIB +select ARCH_WANT_OPTIONAL_GPIOLIB select CPU_HAS_NO_BITFIELDS select CPU_HAS_NO_MULDIV64 select GENERIC_CSUM diff --git a/arch/m68k/include/asm/gpio.h b/arch/m68k/include/asm/gpio.h index 00d0071..5308622 100644 --- a/arch/m68k/include/asm/gpio.h +++ b/arch/m68k/include/asm/gpio.h &lt; at &gt;&lt; at &gt; -17,170 +17,9 &lt; at &gt;&lt; at &gt; #define coldfire_gpio_h #include &lt;linux/io.h&gt; -#include &lt;asm-generic/gpio.h&gt; #include &lt;asm/coldfire.h&gt; #include &lt;asm/mcfsim.h&gt; - -/* - * The Freescale Coldfire family is quite varied in how they implement GPIO. - * Some parts have 8 bit ports, some have 16bit and some have 32bit; some have - * only one port, others have multiple ports; some have a single data latch - * for both input and output, others have a separate pin data register to read - * input; some require a read-modify-write access to change an output, others - * have set and clear registers for some of the outputs; Some have all the - * GPIOs in a single control area, others have some GPIOs implemented in - * different modules. - * - * This implementation attempts accommodate the differences while presenting - * a generic interface that will optimize to as few instructions as possible. - */ -#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \ - defined(CONFIG_M520x) || defined(CONFIG_M523x) || \ - defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ - defined(CONFIG_M532x) || defined(CONFIG_M54xx) - -/* These parts have GPIO organized by 8 bit ports */ - -#define MCFGPIO_PORTTYPEu8 -#define MCFGPIO_PORTSIZE8 -#define mcfgpio_read(port)__raw_readb(port) -#define mcfgpio_write(data, port)__raw_writeb(data, port) - -#elif defined(CONFIG_M5307) || defined(CONFIG_M5407) || defined(CONFIG_M5272) - -/* These parts have GPIO organized by 16 bit ports */ - -#define MCFGPIO_PORTTYPEu16 -#define MCFGPIO_PORTSIZE16 -#define mcfgpio_read(port)__raw_readw(port) -#define mcfgpio_write(data, port)__raw_writew(data, port) - -#elif defined(CONFIG_M5249) - -/* These parts have GPIO organized by 32 bit ports */ - -#define MCFGPIO_PORTTYPEu32 -#define MCFGPIO_PORTSIZE32 -#define mcfgpio_read(port)__raw_readl(port) -#define mcfgpio_write(data, port)__raw_writel(data, port) - -#endif - -#define mcfgpio_bit(gpio)(1 &lt;&lt; ((gpio) % MCFGPIO_PORTSIZE)) -#define mcfgpio_port(gpio)((gpio) / MCFGPIO_PORTSIZE) - -#if defined(CONFIG_M520x) || defined(CONFIG_M523x) || \ - defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x) -/* - * These parts have an 'Edge' Port module (external interrupt/GPIO) which uses - * read-modify-write to change an output and a GPIO module which has separate - * set/clr registers to directly change outputs with a single write access. - */ -#if defined(CONFIG_M528x) -/* - * The 528x also has GPIOs in other modules (GPT, QADC) which use - * read-modify-write as well as those controlled by the EPORT and GPIO modules. - */ -#define MCFGPIO_SCR_START40 -#else -#define MCFGPIO_SCR_START8 -#endif - -#define MCFGPIO_SETR_PORT(gpio)(MCFGPIO_SETR + \ -mcfgpio_port(gpio - MCFGPIO_SCR_START)) - -#define MCFGPIO_CLRR_PORT(gpio)(MCFGPIO_CLRR + \ -mcfgpio_port(gpio - MCFGPIO_SCR_START)) -#else - -#define MCFGPIO_SCR_STARTMCFGPIO_PIN_MAX -/* with MCFGPIO_SCR == MCFGPIO_PIN_MAX, these will be optimized away */ -#define MCFGPIO_SETR_PORT(gpio)0 -#define MCFGPIO_CLRR_PORT(gpio)0 - -#endif -/* - * Coldfire specific helper functions - */ - -/* return the port pin data register for a gpio */ -static inline u32 __mcf_gpio_ppdr(unsigned gpio) -{ -#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \ - defined(CONFIG_M5307) || defined(CONFIG_M5407) -return MCFSIM_PADAT; -#elif defined(CONFIG_M5272) -if (gpio &lt; 16) -return MCFSIM_PADAT; -else if (gpio &lt; 32) -return MCFSIM_PBDAT; -else -return MCFSIM_PCDAT; -#elif defined(CONFIG_M5249) -if (gpio &lt; 32) -return MCFSIM2_GPIOREAD; -else -return MCFSIM2_GPIO1READ; -#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \ - defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x) -if (gpio &lt; 8) -return MCFEPORT_EPPDR; -#if defined(CONFIG_M528x) -else if (gpio &lt; 16) -return MCFGPTA_GPTPORT; -else if (gpio &lt; 24) -return MCFGPTB_GPTPORT; -else if (gpio &lt; 32) -return MCFQADC_PORTQA; -else if (gpio &lt; 40) -return MCFQADC_PORTQB; -#endif -else -return MCFGPIO_PPDR + mcfgpio_port(gpio - MCFGPIO_SCR_START); -#else -return 0; -#endif -} - -/* return the port output data register for a gpio */ -static inline u32 __mcf_gpio_podr(unsigned gpio) -{ -#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \ - defined(CONFIG_M5307) || defined(CONFIG_M5407) -return MCFSIM_PADAT; -#elif defined(CONFIG_M5272) -if (gpio &lt; 16) -return MCFSIM_PADAT; -else if (gpio &lt; 32) -return MCFSIM_PBDAT; -else -return MCFSIM_PCDAT; -#elif defined(CONFIG_M5249) -if (gpio &lt; 32) -return MCFSIM2_GPIOWRITE; -else -return MCFSIM2_GPIO1WRITE; -#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \ - defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x) -if (gpio &lt; 8) -return MCFEPORT_EPDR; -#if defined(CONFIG_M528x) -else if (gpio &lt; 16) -return MCFGPTA_GPTPORT; -else if (gpio &lt; 24) -return MCFGPTB_GPTPORT; -else if (gpio &lt; 32) -return MCFQADC_PORTQA; -else if (gpio &lt; 40) -return MCFQADC_PORTQB; -#endif -else -return MCFGPIO_PODR + mcfgpio_port(gpio - MCFGPIO_SCR_START); -#else -return 0; -#endif -} - +#include &lt;asm/mcfgpio.h&gt; /* * The Generic GPIO functions * &lt; at &gt;&lt; at &gt; -191,7 +30,7 &lt; at &gt;&lt; at &gt; static inline u32 __mcf_gpio_podr(unsigned gpio) static inline int gpio_get_value(unsigned gpio) { if (__builtin_constant_p(gpio) &amp;&amp; gpio &lt; MCFGPIO_PIN_MAX) -return mcfgpio_read(__mcf_gpio_ppdr(gpio)) &amp; mcfgpio_bit(gpio); +return mcfgpio_read(__mcfgpio_ppdr(gpio)) &amp; mcfgpio_bit(gpio); else return __gpio_get_value(gpio); } &lt; at &gt;&lt; at &gt; -204,12 +43,12 &lt; at &gt;&lt; at &gt; static inline void gpio_set_value(unsigned gpio, int value) MCFGPIO_PORTTYPE data; local_irq_save(flags); -data = mcfgpio_read(__mcf_gpio_podr(gpio)); +data = mcfgpio_read(__mcfgpio_podr(gpio)); if (value) data |= mcfgpio_bit(gpio); else data &amp;= ~mcfgpio_bit(gpio); -mcfgpio_write(data, __mcf_gpio_podr(gpio)); +mcfgpio_write(data, __mcfgpio_podr(gpio)); local_irq_restore(flags); } else { if (value) diff --git a/arch/m68k/include/asm/mcfgpio.h b/arch/m68k/include/asm/mcfgpio.h index fe468ea..d982464 100644 --- a/arch/m68k/include/asm/mcfgpio.h +++ b/arch/m68k/include/asm/mcfgpio.h &lt; at &gt;&lt; at &gt; -16,82 +16,275 &lt; at &gt;&lt; at &gt; #ifndef mcfgpio_h #define mcfgpio_h -#include &lt;linux/io.h&gt; +#ifdef CONFIG_GPIOLIB #include &lt;asm-generic/gpio.h&gt; +#else + +int __mcfgpio_get_value(unsigned gpio); +void __mcfgpio_set_value(unsigned gpio, int value); +int __mcfgpio_direction_input(unsigned gpio); +int __mcfgpio_direction_output(unsigned gpio, int value); +int __mcfgpio_request(unsigned gpio); +void __mcfgpio_free(unsigned gpio); + +/* our alternate 'gpiolib' functions */ +static inline int __gpio_get_value(unsigned gpio) +{ +if (gpio &lt; MCFGPIO_PIN_MAX) +return __mcfgpio_get_value(gpio); +else +return -EINVAL; +} + +static inline void __gpio_set_value(unsigned gpio, int value) +{ +if (gpio &lt; MCFGPIO_PIN_MAX) +__mcfgpio_set_value(gpio, value); +} + +static inline int __gpio_cansleep(unsigned gpio) +{ +if (gpio &lt; MCFGPIO_PIN_MAX) +return 0; +else +return -EINVAL; +} + +static inline int __gpio_to_irq(unsigned gpio) +{ +return -EINVAL; +} + +static inline int gpio_direction_input(unsigned gpio) +{ +if (gpio &lt; MCFGPIO_PIN_MAX) +return __mcfgpio_direction_input(gpio); +else +return -EINVAL; +} + +static inline int gpio_direction_output(unsigned gpio, int value) +{ +if (gpio &lt; MCFGPIO_PIN_MAX) +return __mcfgpio_direction_output(gpio, value); +else +return -EINVAL; +} + +static inline int gpio_request(unsigned gpio, const char *label) +{ +if (gpio &lt; MCFGPIO_PIN_MAX) +return __mcfgpio_request(gpio); +else +return -EINVAL; +} + +static inline void gpio_free(unsigned gpio) +{ +if (gpio &lt; MCFGPIO_PIN_MAX) +__mcfgpio_free(gpio); +} + +#endif /* CONFIG_GPIOLIB */ -struct mcf_gpio_chip { -struct gpio_chip gpio_chip; -void __iomem *pddr; -void __iomem *podr; -void __iomem *ppdr; -void __iomem *setr; -void __iomem *clrr; -const u8 *gpio_to_pinmux; -}; - -extern struct mcf_gpio_chip mcf_gpio_chips[]; -extern unsigned int mcf_gpio_chips_size; - -int mcf_gpio_direction_input(struct gpio_chip *, unsigned); -int mcf_gpio_get_value(struct gpio_chip *, unsigned); -int mcf_gpio_direction_output(struct gpio_chip *, unsigned, int); -void mcf_gpio_set_value(struct gpio_chip *, unsigned, int); -void mcf_gpio_set_value_fast(struct gpio_chip *, unsigned, int); -int mcf_gpio_request(struct gpio_chip *, unsigned); -void mcf_gpio_free(struct gpio_chip *, unsigned); /* - *Define macros to ease the pain of setting up the GPIO tables. There - *are two cases we need to deal with here, they cover all currently - *available ColdFire GPIO hardware. There are of course minor differences - *in the layout and number of bits in each ColdFire part, but the macros - *take all that in. + * The Freescale Coldfire family is quite varied in how they implement GPIO. + * Some parts have 8 bit ports, some have 16bit and some have 32bit; some have + * only one port, others have multiple ports; some have a single data latch + * for both input and output, others have a separate pin data register to read + * input; some require a read-modify-write access to change an output, others + * have set and clear registers for some of the outputs; Some have all the + * GPIOs in a single control area, others have some GPIOs implemented in + * different modules. * - *Firstly is the conventional GPIO registers where we toggle individual - *bits in a register, preserving the other bits in the register. For - *lack of a better term I have called this the slow method. + * This implementation attempts accommodate the differences while presenting + * a generic interface that will optimize to as few instructions as possible. + */ +#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \ + defined(CONFIG_M520x) || defined(CONFIG_M523x) || \ + defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ + defined(CONFIG_M532x) || defined(CONFIG_M54xx) + +/* These parts have GPIO organized by 8 bit ports */ + +#define MCFGPIO_PORTTYPEu8 +#define MCFGPIO_PORTSIZE8 +#define mcfgpio_read(port)__raw_readb(port) +#define mcfgpio_write(data, port)__raw_writeb(data, port) + +#elif defined(CONFIG_M5307) || defined(CONFIG_M5407) || defined(CONFIG_M5272) + +/* These parts have GPIO organized by 16 bit ports */ + +#define MCFGPIO_PORTTYPEu16 +#define MCFGPIO_PORTSIZE16 +#define mcfgpio_read(port)__raw_readw(port) +#define mcfgpio_write(data, port)__raw_writew(data, port) + +#elif defined(CONFIG_M5249) + +/* These parts have GPIO organized by 32 bit ports */ + +#define MCFGPIO_PORTTYPEu32 +#define MCFGPIO_PORTSIZE32 +#define mcfgpio_read(port)__raw_readl(port) +#define mcfgpio_write(data, port)__raw_writel(data, port) + +#endif + +#define mcfgpio_bit(gpio)(1 &lt;&lt; ((gpio) % MCFGPIO_PORTSIZE)) +#define mcfgpio_port(gpio)((gpio) / MCFGPIO_PORTSIZE) + +#if defined(CONFIG_M520x) || defined(CONFIG_M523x) || \ + defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x) +/* + * These parts have an 'Edge' Port module (external interrupt/GPIO) which uses + * read-modify-write to change an output and a GPIO module which has separate + * set/clr registers to directly change outputs with a single write access. + */ +#if defined(CONFIG_M528x) +/* + * The 528x also has GPIOs in other modules (GPT, QADC) which use + * read-modify-write as well as those controlled by the EPORT and GPIO modules. */ -#defineMCFGPS(mlabel, mbase, mngpio, mpddr, mpodr, mppdr) \ -{ \ -.gpio_chip= { \ -.label= #mlabel, \ -.request= mcf_gpio_request, \ -.free= mcf_gpio_free, \ -.direction_input= mcf_gpio_direction_input, \ -.direction_output= mcf_gpio_direction_output,\ -.get= mcf_gpio_get_value, \ -.set= mcf_gpio_set_value, \ -.base= mbase, \ -.ngpio= mngpio, \ -}, \ -.pddr= (void __iomem *) mpddr, \ -.podr= (void __iomem *) mpodr, \ -.ppdr= (void __iomem *) mppdr, \ -} +#define MCFGPIO_SCR_START40 +#else +#define MCFGPIO_SCR_START8 +#endif + +#define MCFGPIO_SETR_PORT(gpio)(MCFGPIO_SETR + \ +mcfgpio_port(gpio - MCFGPIO_SCR_START)) + +#define MCFGPIO_CLRR_PORT(gpio)(MCFGPIO_CLRR + \ +mcfgpio_port(gpio - MCFGPIO_SCR_START)) +#else + +#define MCFGPIO_SCR_STARTMCFGPIO_PIN_MAX +/* with MCFGPIO_SCR == MCFGPIO_PIN_MAX, these will be optimized away */ +#define MCFGPIO_SETR_PORT(gpio)0 +#define MCFGPIO_CLRR_PORT(gpio)0 +#endif /* - *Secondly is the faster case, where we have set and clear registers - *that allow us to set or clear a bit with a single write, not having - *to worry about preserving other bits. + * Coldfire specific helper functions */ -#defineMCFGPF(mlabel, mbase, mngpio) \ -{ \ -.gpio_chip= { \ -.label= #mlabel, \ -.request= mcf_gpio_request, \ -.free= mcf_gpio_free, \ -.direction_input= mcf_gpio_direction_input, \ -.direction_output= mcf_gpio_direction_output,\ -.get= mcf_gpio_get_value, \ -.set= mcf_gpio_set_value_fast, \ -.base= mbase, \ -.ngpio= mngpio, \ -}, \ -.pddr= (void __iomem *) MCFGPIO_PDDR_##mlabel, \ -.podr= (void __iomem *) MCFGPIO_PODR_##mlabel, \ -.ppdr= (void __iomem *) MCFGPIO_PPDSDR_##mlabel, \ -.setr= (void __iomem *) MCFGPIO_PPDSDR_##mlabel, \ -.clrr= (void __iomem *) MCFGPIO_PCLRR_##mlabel, \ -} +/* return the port pin data register for a gpio */ +static inline u32 __mcfgpio_ppdr(unsigned gpio) +{ +#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \ + defined(CONFIG_M5307) || defined(CONFIG_M5407) +return MCFSIM_PADAT; +#elif defined(CONFIG_M5272) +if (gpio &lt; 16) +return MCFSIM_PADAT; +else if (gpio &lt; 32) +return MCFSIM_PBDAT; +else +return MCFSIM_PCDAT; +#elif defined(CONFIG_M5249) +if (gpio &lt; 32) +return MCFSIM2_GPIOREAD; +else +return MCFSIM2_GPIO1READ; +#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \ + defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x) +if (gpio &lt; 8) +return MCFEPORT_EPPDR; +#if defined(CONFIG_M528x) +else if (gpio &lt; 16) +return MCFGPTA_GPTPORT; +else if (gpio &lt; 24) +return MCFGPTB_GPTPORT; +else if (gpio &lt; 32) +return MCFQADC_PORTQA; +else if (gpio &lt; 40) +return MCFQADC_PORTQB; +#endif +else +return MCFGPIO_PPDR + mcfgpio_port(gpio - MCFGPIO_SCR_START); +#else +return 0; +#endif +} + +/* return the port output data register for a gpio */ +static inline u32 __mcfgpio_podr(unsigned gpio) +{ +#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \ + defined(CONFIG_M5307) || defined(CONFIG_M5407) +return MCFSIM_PADAT; +#elif defined(CONFIG_M5272) +if (gpio &lt; 16) +return MCFSIM_PADAT; +else if (gpio &lt; 32) +return MCFSIM_PBDAT; +else +return MCFSIM_PCDAT; +#elif defined(CONFIG_M5249) +if (gpio &lt; 32) +return MCFSIM2_GPIOWRITE; +else +return MCFSIM2_GPIO1WRITE; +#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \ + defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x) +if (gpio &lt; 8) +return MCFEPORT_EPDR; +#if defined(CONFIG_M528x) +else if (gpio &lt; 16) +return MCFGPTA_GPTPORT; +else if (gpio &lt; 24) +return MCFGPTB_GPTPORT; +else if (gpio &lt; 32) +return MCFQADC_PORTQA; +else if (gpio &lt; 40) +return MCFQADC_PORTQB; +#endif +else +return MCFGPIO_PODR + mcfgpio_port(gpio - MCFGPIO_SCR_START); +#else +return 0; #endif +} + +/* return the port direction data register for a gpio */ +static inline u32 __mcfgpio_pddr(unsigned gpio) +{ +#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \ + defined(CONFIG_M5307) || defined(CONFIG_M5407) +return MCFSIM_PADDR; +#elif defined(CONFIG_M5272) +if (gpio &lt; 16) +return MCFSIM_PADDR; +else if (gpio &lt; 32) +return MCFSIM_PBDDR; +else +return MCFSIM_PCDDR; +#elif defined(CONFIG_M5249) +if (gpio &lt; 32) +return MCFSIM2_GPIOENABLE; +else +return MCFSIM2_GPIO1ENABLE; +#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \ + defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x) +if (gpio &lt; 8) +return MCFEPORT_EPDDR; +#if defined(CONFIG_M528x) +else if (gpio &lt; 16) +return MCFGPTA_GPTDDR; +else if (gpio &lt; 24) +return MCFGPTB_GPTDDR; +else if (gpio &lt; 32) +return MCFQADC_DDRQA; +else if (gpio &lt; 40) +return MCFQADC_DDRQB; +#endif +else +return MCFGPIO_PDDR + mcfgpio_port(gpio - MCFGPIO_SCR_START); +#else +return 0; +#endif +} + +#endif /* mcfgpio_h */ diff --git a/arch/m68k/include/asm/pinmux.h b/arch/m68k/include/asm/pinmux.h deleted file mode 100644 index 119ee68..0000000 --- a/arch/m68k/include/asm/pinmux.h +++ /dev/null &lt; at &gt;&lt; at &gt; -1,30 +0,0 &lt; at &gt;&lt; at &gt; -/* - * Coldfire generic GPIO pinmux support. - * - * (C) Copyright 2009, Steven King &lt;sfking&lt; at &gt;fdwdc.com&gt; - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef pinmux_h -#define pinmux_h - -#define MCFPINMUX_NONE-1 - -extern int mcf_pinmux_request(unsigned, unsigned); -extern void mcf_pinmux_release(unsigned, unsigned); - -static inline int mcf_pinmux_is_valid(unsigned pinmux) -{ -return pinmux != MCFPINMUX_NONE; -} - -#endif - diff --git a/arch/m68k/platform/coldfire/Makefile b/arch/m68k/platform/coldfire/Makefile index 76d389d..69bc0ae 100644 --- a/arch/m68k/platform/coldfire/Makefile +++ b/arch/m68k/platform/coldfire/Makefile &lt; at &gt;&lt; at &gt; -32,5 +32,5 &lt; at &gt;&lt; at &gt; obj-$(CONFIG_NETtel)+= nettel.o obj-$(CONFIG_CLEOPATRA)+= nettel.o obj-$(CONFIG_FIREBEE)+= firebee.o -obj-y+= pinmux.o gpio.o +obj-y+= gpio.o extra-y := head.o diff --git a/arch/m68k/platform/coldfire/gpio.c b/arch/m68k/platform/coldfire/gpio.c index 4c8c424..9cd2b5c 100644 --- a/arch/m68k/platform/coldfire/gpio.c +++ b/arch/m68k/platform/coldfire/gpio.c &lt; at &gt;&lt; at &gt; -14,119 +14,161 &lt; at &gt;&lt; at &gt; */ #include &lt;linux/kernel.h&gt; +#include &lt;linux/module.h&gt; #include &lt;linux/init.h&gt; #include &lt;linux/device.h&gt; -#include &lt;asm/gpio.h&gt; -#include &lt;asm/pinmux.h&gt; +#include &lt;linux/io.h&gt; +#include &lt;asm/coldfire.h&gt; +#include &lt;asm/mcfsim.h&gt; #include &lt;asm/mcfgpio.h&gt; -#define MCF_CHIP(chip) container_of(chip, struct mcf_gpio_chip, gpio_chip) +int __mcfgpio_get_value(unsigned gpio) +{ +return mcfgpio_read(__mcfgpio_ppdr(gpio)) &amp; mcfgpio_bit(gpio); +} +EXPORT_SYMBOL(__mcfgpio_get_value); + +void __mcfgpio_set_value(unsigned gpio, int value) +{ +if (gpio &lt; MCFGPIO_SCR_START) { +unsigned long flags; +MCFGPIO_PORTTYPE data; + +local_irq_save(flags); +data = mcfgpio_read(__mcfgpio_podr(gpio)); +if (value) +data |= mcfgpio_bit(gpio); +else +data &amp;= ~mcfgpio_bit(gpio); +mcfgpio_write(data, __mcfgpio_podr(gpio)); +local_irq_restore(flags); +} else { +if (value) +mcfgpio_write(mcfgpio_bit(gpio), +MCFGPIO_SETR_PORT(gpio)); +else +mcfgpio_write(~mcfgpio_bit(gpio), +MCFGPIO_CLRR_PORT(gpio)); +} +} +EXPORT_SYMBOL(__mcfgpio_set_value); -int mcf_gpio_direction_input(struct gpio_chip *chip, unsigned offset) +int __mcfgpio_direction_input(unsigned gpio) { unsigned long flags; MCFGPIO_PORTTYPE dir; -struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip); local_irq_save(flags); -dir = mcfgpio_read(mcf_chip-&gt;pddr); -dir &amp;= ~mcfgpio_bit(chip-&gt;base + offset); -mcfgpio_write(dir, mcf_chip-&gt;pddr); +dir = mcfgpio_read(__mcfgpio_pddr(gpio)); +dir &amp;= ~mcfgpio_bit(gpio); +mcfgpio_write(dir, __mcfgpio_pddr(gpio)); local_irq_restore(flags); return 0; } +EXPORT_SYMBOL(__mcfgpio_direction_input); -int mcf_gpio_get_value(struct gpio_chip *chip, unsigned offset) -{ -struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip); - -return mcfgpio_read(mcf_chip-&gt;ppdr) &amp; mcfgpio_bit(chip-&gt;base + offset); -} - -int mcf_gpio_direction_output(struct gpio_chip *chip, unsigned offset, -int value) +int __mcfgpio_direction_output(unsigned gpio, int value) { unsigned long flags; MCFGPIO_PORTTYPE data; -struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip); local_irq_save(flags); -/* write the value to the output latch */ -data = mcfgpio_read(mcf_chip-&gt;podr); +data = mcfgpio_read(__mcfgpio_pddr(gpio)); if (value) -data |= mcfgpio_bit(chip-&gt;base + offset); +data |= mcfgpio_bit(gpio); else -data &amp;= ~mcfgpio_bit(chip-&gt;base + offset); -mcfgpio_write(data, mcf_chip-&gt;podr); - -/* now set the direction to output */ -data = mcfgpio_read(mcf_chip-&gt;pddr); -data |= mcfgpio_bit(chip-&gt;base + offset); -mcfgpio_write(data, mcf_chip-&gt;pddr); +data &amp;= mcfgpio_bit(gpio); +mcfgpio_write(data, __mcfgpio_pddr(gpio)); + +/* now set the data to output */ +if (gpio &lt; MCFGPIO_SCR_START) { +data = mcfgpio_read(__mcfgpio_podr(gpio)); +if (value) +data |= mcfgpio_bit(gpio); +else +data &amp;= ~mcfgpio_bit(gpio); +mcfgpio_write(data, __mcfgpio_podr(gpio)); +} else { + if (value) +mcfgpio_write(mcfgpio_bit(gpio), +MCFGPIO_SETR_PORT(gpio)); + else + mcfgpio_write(~mcfgpio_bit(gpio), + MCFGPIO_CLRR_PORT(gpio)); +} local_irq_restore(flags); +return 0; +} +EXPORT_SYMBOL(__mcfgpio_direction_output); +int __mcfgpio_request(unsigned gpio) +{ return 0; } +EXPORT_SYMBOL(__mcfgpio_request); -void mcf_gpio_set_value(struct gpio_chip *chip, unsigned offset, int value) +void __mcfgpio_free(unsigned gpio) { -struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip); +__mcfgpio_direction_input(gpio); +} +EXPORT_SYMBOL(__mcfgpio_free); -unsigned long flags; -MCFGPIO_PORTTYPE data; +#ifdef CONFIG_GPIOLIB -local_irq_save(flags); -data = mcfgpio_read(mcf_chip-&gt;podr); -if (value) -data |= mcfgpio_bit(chip-&gt;base + offset); -else -data &amp;= ~mcfgpio_bit(chip-&gt;base + offset); -mcfgpio_write(data, mcf_chip-&gt;podr); -local_irq_restore(flags); +int mcfgpio_direction_input(struct gpio_chip *chip, unsigned offset) +{ +return __mcfgpio_direction_input(offset); } -void mcf_gpio_set_value_fast(struct gpio_chip *chip, unsigned offset, int value) +int mcfgpio_get_value(struct gpio_chip *chip, unsigned offset) { -struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip); - -if (value) -mcfgpio_write(mcfgpio_bit(chip-&gt;base + offset), mcf_chip-&gt;setr); -else -mcfgpio_write(~mcfgpio_bit(chip-&gt;base + offset), mcf_chip-&gt;clrr); +return __mcfgpio_get_value(offset); } -int mcf_gpio_request(struct gpio_chip *chip, unsigned offset) +int mcfgpio_direction_output(struct gpio_chip *chip, unsigned offset, int value) { -struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip); - -return mcf_chip-&gt;gpio_to_pinmux ? -mcf_pinmux_request(mcf_chip-&gt;gpio_to_pinmux[offset], 0) : 0; +return __mcfgpio_direction_output(offset, value); } -void mcf_gpio_free(struct gpio_chip *chip, unsigned offset) +void mcfgpio_set_value(struct gpio_chip *chip, unsigned offset, int value) { -struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip); +__mcfgpio_set_value(offset, value); +} -mcf_gpio_direction_input(chip, offset); +int mcfgpio_request(struct gpio_chip *chip, unsigned offset) +{ +return __mcfgpio_request(offset); +} -if (mcf_chip-&gt;gpio_to_pinmux) -mcf_pinmux_release(mcf_chip-&gt;gpio_to_pinmux[offset], 0); +void mcfgpio_free(struct gpio_chip *chip, unsigned offset) +{ +__mcfgpio_free(offset); } -struct bus_type mcf_gpio_subsys = { +struct bus_type mcfgpio_subsys = { .name= "gpio", .dev_name= "gpio", }; -static int __init mcf_gpio_sysinit(void) -{ -unsigned int i = 0; +static struct gpio_chip mcfgpio_chip = { +.label= "mcfgpio", +.request= mcfgpio_request, +.free= mcfgpio_free, +.direction_input= mcfgpio_direction_input, +.direction_output= mcfgpio_direction_output, +.get= mcfgpio_get_value, +.set= mcfgpio_set_value, +.base= 0, +.ngpio= MCFGPIO_PIN_MAX, +}; -while (i &lt; mcf_gpio_chips_size) -gpiochip_add((struct gpio_chip *)&amp;mcf_gpio_chips[i++]); -return subsys_system_register(&amp;mcf_gpio_subsys, NULL); +static int __init mcfgpio_sysinit(void) +{ +gpiochip_add(&amp;mcfgpio_chip); +return subsys_system_register(&amp;mcfgpio_subsys, NULL); } -core_initcall(mcf_gpio_sysinit); +core_initcall(mcfgpio_sysinit); +#endif diff --git a/arch/m68k/platform/coldfire/m5206.c b/arch/m68k/platform/coldfire/m5206.c index a8b81df..6bfbeeb 100644 --- a/arch/m68k/platform/coldfire/m5206.c +++ b/arch/m68k/platform/coldfire/m5206.c &lt; at &gt;&lt; at &gt; -16,15 +16,6 &lt; at &gt;&lt; at &gt; #include &lt;asm/machdep.h&gt; #include &lt;asm/coldfire.h&gt; #include &lt;asm/mcfsim.h&gt; -#include &lt;asm/mcfgpio.h&gt; - -/***************************************************************************/ - -struct mcf_gpio_chip mcf_gpio_chips[] = { -MCFGPS(PP, 0, 8, MCFSIM_PADDR, MCFSIM_PADAT, MCFSIM_PADAT), -}; - -unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips); /***************************************************************************/ diff --git a/arch/m68k/platform/coldfire/m520x.c b/arch/m68k/platform/coldfire/m520x.c index 3264b88..09df4b8 100644 --- a/arch/m68k/platform/coldfire/m520x.c +++ b/arch/m68k/platform/coldfire/m520x.c &lt; at &gt;&lt; at &gt; -19,22 +19,6 &lt; at &gt;&lt; at &gt; #include &lt;asm/coldfire.h&gt; #include &lt;asm/mcfsim.h&gt; #include &lt;asm/mcfuart.h&gt; -#include &lt;asm/mcfgpio.h&gt; - -/***************************************************************************/ - -struct mcf_gpio_chip mcf_gpio_chips[] = { -MCFGPS(PIRQ, 0, 8, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR), -MCFGPF(CS, 9, 3), -MCFGPF(FECI2C, 16, 4), -MCFGPF(QSPI, 24, 4), -MCFGPF(TIMER, 32, 4), -MCFGPF(UART, 40, 8), -MCFGPF(FECH, 48, 8), -MCFGPF(FECL, 56, 8), -}; - -unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips); /***************************************************************************/ diff --git a/arch/m68k/platform/coldfire/m523x.c b/arch/m68k/platform/coldfire/m523x.c index 5d57a42..d47dfd8 100644 --- a/arch/m68k/platform/coldfire/m523x.c +++ b/arch/m68k/platform/coldfire/m523x.c &lt; at &gt;&lt; at &gt; -19,28 +19,6 &lt; at &gt;&lt; at &gt; #include &lt;asm/machdep.h&gt; #include &lt;asm/coldfire.h&gt; #include &lt;asm/mcfsim.h&gt; -#include &lt;asm/mcfgpio.h&gt; - -/***************************************************************************/ - -struct mcf_gpio_chip mcf_gpio_chips[] = { -MCFGPS(PIRQ, 1, 7, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR), -MCFGPF(ADDR, 13, 3), -MCFGPF(DATAH, 16, 8), -MCFGPF(DATAL, 24, 8), -MCFGPF(BUSCTL, 32, 8), -MCFGPF(BS, 40, 4), -MCFGPF(CS, 49, 7), -MCFGPF(SDRAM, 56, 6), -MCFGPF(FECI2C, 64, 4), -MCFGPF(UARTH, 72, 2), -MCFGPF(UARTL, 80, 8), -MCFGPF(QSPI, 88, 5), -MCFGPF(TIMER, 96, 8), -MCFGPF(ETPU, 104, 3), -}; - -unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips); /***************************************************************************/ diff --git a/arch/m68k/platform/coldfire/m5249.c b/arch/m68k/platform/coldfire/m5249.c index fdfa1ed..300e729 100644 --- a/arch/m68k/platform/coldfire/m5249.c +++ b/arch/m68k/platform/coldfire/m5249.c &lt; at &gt;&lt; at &gt; -16,16 +16,6 &lt; at &gt;&lt; at &gt; #include &lt;asm/machdep.h&gt; #include &lt;asm/coldfire.h&gt; #include &lt;asm/mcfsim.h&gt; -#include &lt;asm/mcfgpio.h&gt; - -/***************************************************************************/ - -struct mcf_gpio_chip mcf_gpio_chips[] = { -MCFGPS(GPIO0, 0, 32, MCFSIM2_GPIOENABLE, MCFSIM2_GPIOWRITE, MCFSIM2_GPIOREAD), -MCFGPS(GPIO1, 32, 32, MCFSIM2_GPIO1ENABLE, MCFSIM2_GPIO1WRITE, MCFSIM2_GPIO1READ), -}; - -unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips); /***************************************************************************/ diff --git a/arch/m68k/platform/coldfire/m5272.c b/arch/m68k/platform/coldfire/m5272.c index 43e3606..e68bc7a 100644 --- a/arch/m68k/platform/coldfire/m5272.c +++ b/arch/m68k/platform/coldfire/m5272.c &lt; at &gt;&lt; at &gt; -19,7 +19,6 &lt; at &gt;&lt; at &gt; #include &lt;asm/coldfire.h&gt; #include &lt;asm/mcfsim.h&gt; #include &lt;asm/mcfuart.h&gt; -#include &lt;asm/mcfgpio.h&gt; /***************************************************************************/ &lt; at &gt;&lt; at &gt; -31,16 +30,6 &lt; at &gt;&lt; at &gt; unsigned char ledbank = 0xff; /***************************************************************************/ -struct mcf_gpio_chip mcf_gpio_chips[] = { -MCFGPS(PA, 0, 16, MCFSIM_PADDR, MCFSIM_PADAT, MCFSIM_PADAT), -MCFGPS(PB, 16, 16, MCFSIM_PBDDR, MCFSIM_PBDAT, MCFSIM_PBDAT), -MCFGPS(Pc, 32, 16, MCFSIM_PCDDR, MCFSIM_PCDAT, MCFSIM_PCDAT), -}; - -unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips); - -/***************************************************************************/ - static void __init m5272_uarts_init(void) { u32 v; diff --git a/arch/m68k/platform/coldfire/m527x.c b/arch/m68k/platform/coldfire/m527x.c index 9b0b66a..b3cb378 100644 --- a/arch/m68k/platform/coldfire/m527x.c +++ b/arch/m68k/platform/coldfire/m527x.c &lt; at &gt;&lt; at &gt; -20,49 +20,6 &lt; at &gt;&lt; at &gt; #include &lt;asm/coldfire.h&gt; #include &lt;asm/mcfsim.h&gt; #include &lt;asm/mcfuart.h&gt; -#include &lt;asm/mcfgpio.h&gt; - -/***************************************************************************/ - -struct mcf_gpio_chip mcf_gpio_chips[] = { -#if defined(CONFIG_M5271) -MCFGPS(PIRQ, 1, 7, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR), -MCFGPF(ADDR, 13, 3), -MCFGPF(DATAH, 16, 8), -MCFGPF(DATAL, 24, 8), -MCFGPF(BUSCTL, 32, 8), -MCFGPF(BS, 40, 4), -MCFGPF(CS, 49, 7), -MCFGPF(SDRAM, 56, 6), -MCFGPF(FECI2C, 64, 4), -MCFGPF(UARTH, 72, 2), -MCFGPF(UARTL, 80, 8), -MCFGPF(QSPI, 88, 5), -MCFGPF(TIMER, 96, 8), -#elif defined(CONFIG_M5275) -MCFGPS(PIRQ, 1, 7, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR), -MCFGPF(BUSCTL, 8, 8), -MCFGPF(ADDR, 21, 3), -MCFGPF(CS, 25, 7), -MCFGPF(FEC0H, 32, 8), -MCFGPF(FEC0L, 40, 8), -MCFGPF(FECI2C, 48, 6), -MCFGPF(QSPI, 56, 7), -MCFGPF(SDRAM, 64, 8), -MCFGPF(TIMERH, 72, 4), -MCFGPF(TIMERL, 80, 4), -MCFGPF(UARTL, 88, 8), -MCFGPF(FEC1H, 96, 8), -MCFGPF(FEC1L, 104, 8), -MCFGPF(BS, 114, 2), -MCFGPF(IRQ, 121, 7), -MCFGPF(USBH, 128, 1), -MCFGPF(USBL, 136, 8), -MCFGPF(UARTH, 144, 4), -#endif -}; - -unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips); /***************************************************************************/ diff --git a/arch/m68k/platform/coldfire/m528x.c b/arch/m68k/platform/coldfire/m528x.c index 7ed1276b..f1319e5 100644 --- a/arch/m68k/platform/coldfire/m528x.c +++ b/arch/m68k/platform/coldfire/m528x.c &lt; at &gt;&lt; at &gt; -21,37 +21,6 &lt; at &gt;&lt; at &gt; #include &lt;asm/coldfire.h&gt; #include &lt;asm/mcfsim.h&gt; #include &lt;asm/mcfuart.h&gt; -#include &lt;asm/mcfgpio.h&gt; - -/***************************************************************************/ - -struct mcf_gpio_chip mcf_gpio_chips[] = { -MCFGPS(NQ, 1, 7, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR), -MCFGPS(TA, 8, 4, MCFGPTA_GPTDDR, MCFGPTA_GPTPORT, MCFGPTB_GPTPORT), -MCFGPS(TB, 16, 4, MCFGPTB_GPTDDR, MCFGPTB_GPTPORT, MCFGPTB_GPTPORT), -MCFGPS(QA, 24, 4, MCFQADC_DDRQA, MCFQADC_PORTQA, MCFQADC_PORTQA), -MCFGPS(QB, 32, 4, MCFQADC_DDRQB, MCFQADC_PORTQB, MCFQADC_PORTQB), -MCFGPF(A, 40, 8), -MCFGPF(B, 48, 8), -MCFGPF(C, 56, 8), -MCFGPF(D, 64, 8), -MCFGPF(E, 72, 8), -MCFGPF(F, 80, 8), -MCFGPF(G, 88, 8), -MCFGPF(H, 96, 8), -MCFGPF(J, 104, 8), -MCFGPF(DD, 112, 8), -MCFGPF(EH, 120, 8), -MCFGPF(EL, 128, 8), -MCFGPF(AS, 136, 6), -MCFGPF(QS, 144, 7), -MCFGPF(SD, 152, 6), -MCFGPF(TC, 160, 4), -MCFGPF(TD, 168, 4), -MCFGPF(UA, 176, 4), -}; - -unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips); /***************************************************************************/ &lt; at &gt;&lt; at &gt; -74,7 +43,7 &lt; at &gt;&lt; at &gt; static void __init m528x_uarts_init(void) /* make sure PUAPAR is set for UART0 and UART1 */ port = readb(MCF5282_GPIO_PUAPAR); port |= 0x03 | (0x03 &lt;&lt; 2); -writeb(port, MCF5282_GPIO_PUAPAR); +writeb(port, MCFGPIO_PUAPAR); } /***************************************************************************/ diff --git a/arch/m68k/platform/coldfire/m5307.c b/arch/m68k/platform/coldfire/m5307.c index 93b4849..a568d28 100644 --- a/arch/m68k/platform/coldfire/m5307.c +++ b/arch/m68k/platform/coldfire/m5307.c &lt; at &gt;&lt; at &gt; -16,7 +16,6 &lt; at &gt;&lt; at &gt; #include &lt;asm/machdep.h&gt; #include &lt;asm/coldfire.h&gt; #include &lt;asm/mcfsim.h&gt; -#include &lt;asm/mcfgpio.h&gt; #include &lt;asm/mcfwdebug.h&gt; /***************************************************************************/ &lt; at &gt;&lt; at &gt; -29,14 +28,6 &lt; at &gt;&lt; at &gt; unsigned char ledbank = 0xff; /***************************************************************************/ -struct mcf_gpio_chip mcf_gpio_chips[] = { -MCFGPS(PP, 0, 16, MCFSIM_PADDR, MCFSIM_PADAT, MCFSIM_PADAT), -}; - -unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips); - -/***************************************************************************/ - void __init config_BSP(char *commandp, int size) { #if defined(CONFIG_NETtel) || \ diff --git a/arch/m68k/platform/coldfire/m532x.c b/arch/m68k/platform/coldfire/m532x.c index 8e9476d..37082d0 100644 --- a/arch/m68k/platform/coldfire/m532x.c +++ b/arch/m68k/platform/coldfire/m532x.c &lt; at &gt;&lt; at &gt; -26,35 +26,10 &lt; at &gt;&lt; at &gt; #include &lt;asm/mcfsim.h&gt; #include &lt;asm/mcfuart.h&gt; #include &lt;asm/mcfdma.h&gt; -#include &lt;asm/mcfgpio.h&gt; #include &lt;asm/mcfwdebug.h&gt; /***************************************************************************/ -struct mcf_gpio_chip mcf_gpio_chips[] = { -MCFGPS(PIRQ, 0, 8, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR), -MCFGPF(FECH, 8, 8), -MCFGPF(FECL, 16, 8), -MCFGPF(SSI, 24, 5), -MCFGPF(BUSCTL, 32, 4), -MCFGPF(BE, 40, 4), -MCFGPF(CS, 49, 5), -MCFGPF(PWM, 58, 4), -MCFGPF(FECI2C, 64, 4), -MCFGPF(UART, 72, 8), -MCFGPF(QSPI, 80, 6), -MCFGPF(TIMER, 88, 4), -MCFGPF(LCDDATAH, 96, 2), -MCFGPF(LCDDATAM, 104, 8), -MCFGPF(LCDDATAL, 112, 8), -MCFGPF(LCDCTLH, 120, 1), -MCFGPF(LCDCTLL, 128, 8), -}; - -unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips); - -/***************************************************************************/ - #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) static void __init m532x_qspi_init(void) diff --git a/arch/m68k/platform/coldfire/m5407.c b/arch/m68k/platform/coldfire/m5407.c index faa6680..bb6c746 100644 --- a/arch/m68k/platform/coldfire/m5407.c +++ b/arch/m68k/platform/coldfire/m5407.c &lt; at &gt;&lt; at &gt; -16,15 +16,6 &lt; at &gt;&lt; at &gt; #include &lt;asm/machdep.h&gt; #include &lt;asm/coldfire.h&gt; #include &lt;asm/mcfsim.h&gt; -#include &lt;asm/mcfgpio.h&gt; - -/***************************************************************************/ - -struct mcf_gpio_chip mcf_gpio_chips[] = { -MCFGPS(PP, 0, 16, MCFSIM_PADDR, MCFSIM_PADAT, MCFSIM_PADAT), -}; - -unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips); /***************************************************************************/ diff --git a/arch/m68k/platform/coldfire/m54xx.c b/arch/m68k/platform/coldfire/m54xx.c index 20672da..2081c6c 100644 --- a/arch/m68k/platform/coldfire/m54xx.c +++ b/arch/m68k/platform/coldfire/m54xx.c &lt; at &gt;&lt; at &gt; -21,19 +21,12 &lt; at &gt;&lt; at &gt; #include &lt;asm/m54xxsim.h&gt; #include &lt;asm/mcfuart.h&gt; #include &lt;asm/m54xxgpt.h&gt; -#include &lt;asm/mcfgpio.h&gt; #ifdef CONFIG_MMU #include &lt;asm/mmu_context.h&gt; #endif /***************************************************************************/ -struct mcf_gpio_chip mcf_gpio_chips[] = { }; - -unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips); - -/***************************************************************************/ - static void __init m54xx_uarts_init(void) { /* enable io pins */ diff --git a/arch/m68k/platform/coldfire/pinmux.c b/arch/m68k/platform/coldfire/pinmux.c deleted file mode 100644 index 8c62b82..0000000 --- a/arch/m68k/platform/coldfire/pinmux.c +++ /dev/null &lt; at &gt;&lt; at &gt; -1,28 +0,0 &lt; at &gt;&lt; at &gt; -/* - * Coldfire generic GPIO pinmux support. - * - * (C) Copyright 2009, Steven King &lt;sfking&lt; at &gt;fdwdc.com&gt; - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include &lt;linux/kernel.h&gt; - -#include &lt;asm/pinmux.h&gt; - -int mcf_pinmux_request(unsigned pinmux, unsigned func) -{ -return 0; -} - -void mcf_pinmux_release(unsigned pinmux, unsigned func) -{ -} _______________________________________________ uClinux-dev mailing list uClinux-dev&lt; at &gt;uclinux.org http://mailman.uclinux.org/mailman/listinfo/uclinux-dev This message was resent by uclinux-dev&lt; at &gt;uclinux.org To unsubscribe see: http://mailman.uclinux.org/mailman/options/uclinux-dev </pre> Steven King 2012-05-21T20:10:19 http://permalink.gmane.org/gmane.linux.uclinux.devel/20450 <pre> Acked-by: Geert Uytterhoeven &lt;geert&lt; at &gt;linux-m68k.org&gt; Gr{oetje,eeting}s,                         Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert&lt; at &gt;linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.                                 -- Linus Torvalds _______________________________________________ uClinux-dev mailing list uClinux-dev&lt; at &gt;uclinux.org http://mailman.uclinux.org/mailman/listinfo/uclinux-dev This message was resent by uclinux-dev&lt; at &gt;uclinux.org To unsubscribe see: http://mailman.uclinux.org/mailman/options/uclinux-dev</pre> Geert Uytterhoeven 2012-05-20T09:22:01 http://permalink.gmane.org/gmane.linux.uclinux.devel/20448 <pre> Acked-by: Geert Uytterhoeven &lt;geert&lt; at &gt;linux-m68k.org&gt; Gr{oetje,eeting}s,                         Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert&lt; at &gt;linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.                                 -- Linus Torvalds _______________________________________________ uClinux-dev mailing list uClinux-dev&lt; at &gt;uclinux.org http://mailman.uclinux.org/mailman/listinfo/uclinux-dev This message was resent by uclinux-dev&lt; at &gt;uclinux.org To unsubscribe see: http://mailman.uclinux.org/mailman/options/uclinux-dev</pre> Geert Uytterhoeven 2012-05-20T09:15:44 http://permalink.gmane.org/gmane.linux.uclinux.devel/20446 <pre> Acked-by: Geert Uytterhoeven &lt;geert&lt; at &gt;linux-m68k.org&gt; Gr{oetje,eeting}s,                         Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert&lt; at &gt;linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.                                 -- Linus Torvalds _______________________________________________ uClinux-dev mailing list uClinux-dev&lt; at &gt;uclinux.org http://mailman.uclinux.org/mailman/listinfo/uclinux-dev This message was resent by uclinux-dev&lt; at &gt;uclinux.org To unsubscribe see: http://mailman.uclinux.org/mailman/options/uclinux-dev</pre> Geert Uytterhoeven 2012-05-20T09:01:27 http://permalink.gmane.org/gmane.linux.uclinux.devel/20442 <pre>Hi Luis, On 18/05/12 00:21, Luis Alves wrote: Yeah, interesting discussion :-) Well, I consider it a bug still (I will probably make some gcc people unhappy :-( The ABI change itself doesn't really have anything to do with it. If you use "gcc -m68000" to generate code that cannot work then it is a bug. I couldn't in good conscience call that a configuration error (though we know you can fix it by changing the that STRICT_ALIGNMENT setting). But that is just my take on it. Regards Greg </pre> Greg Ungerer 2012-05-18T05:17:34 http://permalink.gmane.org/gmane.linux.uclinux.devel/20437 <pre> gcc 4.3 at least change the size of floating point from 80 to 64bit on coldfire (and possibly on m68k in general, not sure), and also made some changes in other things. gcc 4.2 would fail to compile some programs for me, running out of space in the offset table as far as I can tell, while gcc 4.3 has never had any problems with that. My understanding is that gcc 4.3 switched to a different way of handling the GOT which works much better, but is almost certainly incompatible with the old method. gcc 4.3 also optimizes a lot more in m68k than 4.2 (I had to insert memory barriers in uboot to convince gcc 4.3 not to rearrange seemingly unrelated memory read and writes in the memory controller setup, where as gcc 4.2 did so little optimization that it never had any issue). gcc 4.3 didn't do anything wrong, the code simply wasn't specific enough about what it wanted. So I like the gcc 4.3 improvements over 4.2. </pre> Lennart Sorensen 2012-05-17T14:54:18 http://permalink.gmane.org/gmane.linux.uclinux.devel/20436 <pre>Hi Greg, Yes, that file exists in the sources gcc-&lt;version&gt;/gcc/config/m68k/uclinux.h I've changed those flags and it works (at least in a small test with the first pass gcc). But take a look at the comments in my bug report: http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53386 Someone says that it is related to the ABI change in gcc &gt;= 4.3.x and that I should use as target 'm68k-uclinuxoldabi' and --with-cpu=m68000. For now I've just changed the flags in the header file... maybe I'll try building it with that weird target (m68k-uclinuxoldabi). Regards, Luis Alves On Thu, May 17, 2012 at 2:59 PM, Greg Ungerer &lt;gerg&lt; at &gt;snapgear.com&gt; wrote: _______________________________________________ uClinux-dev mailing list uClinux-dev&lt; at &gt;uclinux.org http://mailman.uclinux.org/mailman/listinfo/uclinux-dev This message was resent by uclinux-dev&lt; at &gt;uclinux.org To unsubscribe see: http://mailman.uclinux.org/mailman/options/uclinux-dev </pre> Luis Alves 2012-05-17T14:21:12 http://permalink.gmane.org/gmane.linux.uclinux.devel/20435 <pre>Hi Luis, On 05/17/2012 12:58 PM, Luis Alves wrote: That is bad... Ouch, doesn't sound like much fun. The gcc compile options looked good to me. If you have -m68000 set the you should be getting code that is good for 68000. I guess the code generation is at least only using the correct set of 68000 instructions. Choosing a different optimization level may change the instruction/ addressing modes used. But really that would just be a work around. Otherwise I would suggest sticking with 4.2.4 if that works. Regards Greg </pre> Greg Ungerer 2012-05-17T06:45:07 http://permalink.gmane.org/gmane.linux.uclinux.devel/20434 <pre>Hi Greg, I've built a new toolchain using the latest tools and gcc-4.6.4 (gcc-4.7.0 is giving me compiler internal errors!). But unfortunately the results are the same (bad assembly code - It look it is producing 68020 code, since when I use the -m68020 flag, the resulting assembly code is equal!) I've downgraded gcc to 4.2.4 (the version I was using before this toolchain quest) and it works (produces correct assembly code). I don't know what is the latest working version for the 68000 targets. Maybe I'll go one by one until I find the broken one... I guess this is related to gcc so I've reported it as a bug it in the gcc bugzilla (Bug 53386). Do you have any further suggestion? Thanks and regards, Luis Alves On Wed, May 16, 2012 at 9:42 PM, Luis Alves &lt;ljalvs&lt; at &gt;gmail.com&gt; wrote: _______________________________________________ uClinux-dev mailing list uClinux-dev&lt; at &gt;uclinux.org http://mailman.uclinux.org/mailman/listinfo/uclinux-dev This message was resent by uclinux-dev&lt; at &gt;uclinux.org To unsubscribe see: http://mailman.uclinux.org/mailman/options/uclinux-dev </pre> Luis Alves 2012-05-17T02:58:34 http://permalink.gmane.org/gmane.linux.uclinux.devel/20433 <pre>D'oh! I really dropped the ball on this, but I figure better late than never ;-). Changes since V2: drivers/i2c/busses/i2c-coldfire.c: * As Ben suggested, making the interrupt handler do most of the message processing and wake the thread when its done vastly improves performance. * preliminary support for PM_RUNTIME; but as there isn't arch support for for PM_RUNTIME it doesn't do anything yet. * fixed a bug when the driver would hang on waiting for bus busy if the bus never went busy. drivers/i2c/busses/Kconfig: * its easier to list the Coldfire MCUs that don't have I2C. arch/m68k/include/asm/mcfi2c.h: * moved the defines for the various Coldfire MCUs to the specific header file for the various Coldfire MCUs. Support for the Freescale Coldfire I2C controller. Signed-off-by: Steven King &lt;sfking&lt; at &gt;fedc.com&gt; --- arch/m68k/include/asm/mcfi2c.h | 15 ++ drivers/i2c/busses/Kconfig | 10 + drivers/i2c/busses/Makefile | 1 + drivers/i2c/busses/i2c-coldfire.c | 497 +++++++++++++++++++++++++++++++++++++ 4 files changed, 523 insertions(+) diff --git a/arch/m68k/include/asm/mcfi2c.h b/arch/m68k/include/asm/mcfi2c.h new file mode 100644 index 0000000..24b0453 --- /dev/null +++ b/arch/m68k/include/asm/mcfi2c.h &lt; at &gt;&lt; at &gt; -0,0 +1,15 &lt; at &gt;&lt; at &gt; +/* + * Definitions for Coldfire I2C interface +*/ +#ifndef mcfi2c_h +#define mcfi2c_h + +/** + * struct mcfi2c_platform_data - platform data for the coldfire i2c driver + * &lt; at &gt;bitrate: bitrate to use for this i2c controller. +*/ +struct mcfi2c_platform_data { +u32bitrate; +}; + +#endif /* mcfi2c_h */ diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index d2c5095..159404e 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig &lt; at &gt;&lt; at &gt; -327,6 +327,16 &lt; at &gt;&lt; at &gt; config I2C_BLACKFIN_TWI_CLK_KHZ help The unit of the TWI clock is kHz. +config I2C_COLDFIRE +tristate "Freescale Coldfire I2C driver" +depends on !M5272 +help + This driver supports the I2C interface availible on most Freescale + Coldfire processors. + + This driver can be built as a module. If so, the module + will be called i2c-coldfire. + config I2C_CPM tristate "Freescale CPM1 or CPM2 (MPC8xx/826x)" depends on (CPM1 || CPM2) &amp;&amp; OF_I2C diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile index 569567b..2c88c4a 100644 --- a/drivers/i2c/busses/Makefile +++ b/drivers/i2c/busses/Makefile &lt; at &gt;&lt; at &gt; -31,6 +31,7 &lt; at &gt;&lt; at &gt; obj-$(CONFIG_I2C_POWERMAC)+= i2c-powermac.o obj-$(CONFIG_I2C_AT91)+= i2c-at91.o obj-$(CONFIG_I2C_AU1550)+= i2c-au1550.o obj-$(CONFIG_I2C_BLACKFIN_TWI)+= i2c-bfin-twi.o +obj-$(CONFIG_I2C_COLDFIRE)+= i2c-coldfire.o obj-$(CONFIG_I2C_CPM)+= i2c-cpm.o obj-$(CONFIG_I2C_DAVINCI)+= i2c-davinci.o obj-$(CONFIG_I2C_DESIGNWARE_PLATFORM)+= i2c-designware-platform.o diff --git a/drivers/i2c/busses/i2c-coldfire.c b/drivers/i2c/busses/i2c-coldfire.c new file mode 100644 index 0000000..97351c0 --- /dev/null +++ b/drivers/i2c/busses/i2c-coldfire.c &lt; at &gt;&lt; at &gt; -0,0 +1,497 &lt; at &gt;&lt; at &gt; +/* Freescale/Motorola Coldfire I2C driver. + * + * Copyright 2010, 2012 Steven King &lt;sfking&lt; at &gt;fdwdc.com&gt; + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include &lt;linux/kernel.h&gt; +#include &lt;linux/module.h&gt; +#include &lt;linux/interrupt.h&gt; +#include &lt;linux/errno.h&gt; +#include &lt;linux/platform_device.h&gt; +#include &lt;linux/io.h&gt; +#include &lt;linux/clk.h&gt; +#include &lt;linux/err.h&gt; +#include &lt;linux/i2c.h&gt; +#include &lt;linux/slab.h&gt; +#include &lt;linux/pm_runtime.h&gt; +#include &lt;asm/mcfi2c.h&gt; + +#defineDRIVER_NAME "mcfi2c" + +#defineMCFI2C_ADR0x00 +#defineMCFI2C_FDR0x04 +#defineMCFI2C_CR0x08 +#defineMCFI2C_CR_IEN0x80 +#defineMCFI2C_CR_IIEN0x40 +#defineMCFI2C_CR_MSTA0x20 +#defineMCFI2C_CR_MTX0x10 +#defineMCFI2C_CR_TXAK0x08 +#defineMCFI2C_CR_RSTA0x04 +#defineMCFI2C_DR0x10 +#defineMCFI2C_SR0x0C +#defineMCFI2C_SR_ICF0x80 +#defineMCFI2C_SR_IAAS0x40 +#defineMCFI2C_SR_IBB0x20 +#defineMCFI2C_SR_IAL0x10 +#defineMCFI2C_SR_SRW0x04 +#defineMCFI2C_SR_IIF0x02 +#defineMCFI2C_SR_RXAK0x01 + +#defineDEFAULT_I2C_BUS_SPEED100000 + +struct mcfi2c { +struct i2c_adapteradapter; +void __iomem*iobase; +intirq; +struct clk*clk; +struct completioncompletion; + +u8*buf; +u16flags; +u16len; +intmore; +intstatus; +}; + +static u8 mcfi2c_rd_cr(struct mcfi2c *mcfi2c) +{ +return readb(mcfi2c-&gt;iobase + MCFI2C_CR); +} + +static void mcfi2c_wr_cr(struct mcfi2c *mcfi2c, u8 val) +{ +writeb(val, mcfi2c-&gt;iobase + MCFI2C_CR); +} + +static u8 mcfi2c_rd_sr(struct mcfi2c *mcfi2c) +{ +return readb(mcfi2c-&gt;iobase + MCFI2C_SR); +} + +static void mcfi2c_wr_sr(struct mcfi2c *mcfi2c, u8 val) +{ +writeb(val, mcfi2c-&gt;iobase + MCFI2C_SR); +} + +static u8 mcfi2c_rd_dr(struct mcfi2c *mcfi2c) +{ +return readb(mcfi2c-&gt;iobase + MCFI2C_DR); +} + +static void mcfi2c_wr_dr(struct mcfi2c *mcfi2c, u8 val) +{ +writeb(val, mcfi2c-&gt;iobase + MCFI2C_DR); +} + +static void mcfi2c_start(struct mcfi2c *mcfi2c) +{ +mcfi2c_wr_cr(mcfi2c, MCFI2C_CR_IEN | MCFI2C_CR_IIEN | MCFI2C_CR_MSTA | + MCFI2C_CR_MTX); +} + +static void mcfi2c_repeat_start(struct mcfi2c *mcfi2c) +{ +mcfi2c_wr_cr(mcfi2c, MCFI2C_CR_IEN | MCFI2C_CR_IIEN | MCFI2C_CR_MSTA | + MCFI2C_CR_MTX | MCFI2C_CR_RSTA); +} + +static void mcfi2c_stop(struct mcfi2c *mcfi2c) +{ +mcfi2c_wr_cr(mcfi2c, MCFI2C_CR_IEN); +} + +static void mcfi2c_tx_ack(struct mcfi2c *mcfi2c) +{ +mcfi2c_wr_cr(mcfi2c, MCFI2C_CR_IEN | MCFI2C_CR_IIEN | MCFI2C_CR_MSTA); +} + +static void mcfi2c_tx_nak(struct mcfi2c *mcfi2c) +{ +mcfi2c_wr_cr(mcfi2c, MCFI2C_CR_IEN | MCFI2C_CR_IIEN | MCFI2C_CR_MSTA | + MCFI2C_CR_TXAK); +} + +static irqreturn_t mcfi2c_irq_handler(int this_irq, void *dev_id) +{ +struct mcfi2c *mcfi2c = dev_id; +u8 sr; + +if (pm_runtime_suspended(&amp;mcfi2c-&gt;adapter.dev)) +return IRQ_NONE; + +/* clear interrupt */ +mcfi2c_wr_sr(mcfi2c, 0); + +sr = mcfi2c_rd_sr(mcfi2c); +if (sr &amp; MCFI2C_SR_IAL) { +mcfi2c_wr_sr(mcfi2c, ~MCFI2C_SR_IAL); +mcfi2c-&gt;status = -EIO; +} else if (mcfi2c_rd_cr(mcfi2c) &amp; MCFI2C_CR_MTX) { +if (sr &amp; MCFI2C_SR_RXAK) { +mcfi2c_stop(mcfi2c); +mcfi2c-&gt;status = -EIO; +} else if (mcfi2c-&gt;flags &amp; I2C_M_RD) { +if (mcfi2c-&gt;len &gt; 1) +mcfi2c_tx_ack(mcfi2c); +else +mcfi2c_tx_nak(mcfi2c); +/* dummy read */ +mcfi2c_rd_dr(mcfi2c); +goto not_complete; + +} else if (mcfi2c-&gt;len--) { +mcfi2c_wr_dr(mcfi2c, *(mcfi2c-&gt;buf++)); +goto not_complete; +} else { +if (mcfi2c-&gt;more) +mcfi2c_repeat_start(mcfi2c); +else +mcfi2c_stop(mcfi2c); +} +} else if (--mcfi2c-&gt;len) { +if (!(mcfi2c-&gt;len &gt; 1)) +mcfi2c_tx_nak(mcfi2c); +*(mcfi2c-&gt;buf++) = mcfi2c_rd_dr(mcfi2c); +goto not_complete; +} else { +if (mcfi2c-&gt;more) +mcfi2c_repeat_start(mcfi2c); +else +mcfi2c_stop(mcfi2c); +*(mcfi2c-&gt;buf++) = mcfi2c_rd_dr(mcfi2c); +} +complete(&amp;mcfi2c-&gt;completion); +not_complete: +return IRQ_HANDLED; +} + +static void mcfi2c_reset(struct mcfi2c *mcfi2c) +{ +mcfi2c_wr_cr(mcfi2c, 0); +mcfi2c_wr_cr(mcfi2c, MCFI2C_CR_IEN | MCFI2C_CR_MSTA); +mcfi2c_rd_dr(mcfi2c); +mcfi2c_wr_sr(mcfi2c, 0); +mcfi2c_wr_cr(mcfi2c, 0); +mcfi2c_wr_cr(mcfi2c, MCFI2C_CR_IEN); +} + +static int mcfi2c_wait_for_bus_idle(struct mcfi2c *mcfi2c) +{ +unsigned long timeout = jiffies + HZ / 2; +while (mcfi2c_rd_sr(mcfi2c) &amp; MCFI2C_SR_IBB) { +if (time_after(jiffies, timeout)) +return -EIO; /* bus is busy, try again */ +cond_resched(); +} +return 0; +} + +static int mcfi2c_wait_for_bus_busy(struct mcfi2c *mcfi2c) +{ +unsigned long timeout = jiffies + HZ / 10; +u8 sr; +while (!((sr = mcfi2c_rd_sr(mcfi2c)) &amp; MCFI2C_SR_IBB)) { +if (sr &amp; MCFI2C_SR_IAL) +return -EIO; /* lost arbitration, try again */ +if (time_after(jiffies, timeout)) { +/* if we dont get bus busy and dont get an arbitration + * loss, then the bus is probably glitched, see if we + * can recover. +*/ +dev_dbg(&amp;mcfi2c-&gt;adapter.dev, +"unable to send START, trying to reset the bus\n"); +mcfi2c_reset(mcfi2c); +return -EIO; +} +cond_resched(); +} +return 0; +} + +static int mcfi2c_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, +int num) +{ +struct mcfi2c *mcfi2c = i2c_get_adapdata(adapter); +int cnt = 0; + +pm_runtime_get_sync(&amp;adapter-&gt;dev); + +while (num--) { +int retries = adapter-&gt;retries; +if (msgs-&gt;flags &amp; ~I2C_M_RD) { +mcfi2c-&gt;status = -EINVAL; +goto done; +} +do { +mcfi2c-&gt;flags = msgs-&gt;flags; +mcfi2c-&gt;buf = msgs-&gt;buf; +mcfi2c-&gt;len = msgs-&gt;len; +mcfi2c-&gt;more = num; +mcfi2c-&gt;status = 0; + +if (!(mcfi2c_rd_cr(mcfi2c) &amp; MCFI2C_CR_MSTA)) { +mcfi2c-&gt;status = + mcfi2c_wait_for_bus_idle(mcfi2c); +if (mcfi2c-&gt;status) +continue; + +INIT_COMPLETION(mcfi2c-&gt;completion); +mcfi2c_start(mcfi2c); + +mcfi2c-&gt;status = + mcfi2c_wait_for_bus_busy(mcfi2c); +if (mcfi2c-&gt;status) +continue; +} + +mcfi2c_wr_dr(mcfi2c, (msgs-&gt;addr &lt;&lt; 1) | +(msgs-&gt;flags &amp; I2C_M_RD)); +if (!wait_for_completion_timeout(&amp;mcfi2c-&gt;completion, +adapter-&gt;timeout * msgs-&gt;len)) { +mcfi2c-&gt;status = -ETIMEDOUT; +mcfi2c_stop(mcfi2c); +} + +} while (mcfi2c-&gt;status &amp;&amp; retries--); +if (mcfi2c-&gt;status) +goto done; +++cnt; +++msgs; +} +done: +pm_runtime_put(&amp;adapter-&gt;dev); + +return mcfi2c-&gt;status ?: cnt; +} + +static u32 mcfi2c_func(struct i2c_adapter *adapter) +{ +return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; +} + +static const struct i2c_algorithm mcfi2c_algo = { +.master_xfer= mcfi2c_xfer, +.functionality= mcfi2c_func, +}; + +static const u16 mcfi2c_fdr[] = { + 28, 30, 34, 40, 44, 48, 56, 68, + 80, 88, 104, 128, 144, 160, 192, 240, + 288, 320, 384, 480, 576, 640, 768, 960, +1152, 1280, 1536, 1920, 2304, 2560, 3072, 3840, + 20, 22, 24, 26, 28, 32, 36, 40, + 48, 56, 64, 72, 80, 96, 112, 128, + 160, 192, 224, 256, 320, 384, 448, 512, + 640, 768, 896, 1024, 1280, 1536, 1792, 2048 +}; + +static u8 __devinit mcfi2c_calc_fdr(struct mcfi2c *mcfi2c, + struct mcfi2c_platform_data *pdata) +{ +u32 bitrate = (pdata &amp;&amp; pdata-&gt;bitrate) ? +pdata-&gt;bitrate : DEFAULT_I2C_BUS_SPEED; +int div = clk_get_rate(mcfi2c-&gt;clk)/bitrate; +int r = 0, i = 0; + +do +if (abs(mcfi2c_fdr[i] - div) &lt; abs(mcfi2c_fdr[r] - div)) +r = i; +while (++i &lt; ARRAY_SIZE(mcfi2c_fdr)); + +return r; +} + +static int __devinit mcfi2c_probe(struct platform_device *pdev) +{ +struct mcfi2c *mcfi2c; +struct resource *res; +int status; + +mcfi2c = kzalloc(sizeof(*mcfi2c), GFP_KERNEL); +if (!mcfi2c) { +dev_dbg(&amp;pdev-&gt;dev, "kzalloc failed\n"); + +return -ENOMEM; +} + +res = platform_get_resource(pdev, IORESOURCE_MEM, 0); +if (!res) { +dev_dbg(&amp;pdev-&gt;dev, "platform_get_resource failed\n"); +status = -ENXIO; +goto fail0; +} + +if (!request_mem_region(res-&gt;start, resource_size(res), pdev-&gt;name)) { +dev_dbg(&amp;pdev-&gt;dev, "request_mem_region failed\n"); +status = -EBUSY; +goto fail0; +} + +mcfi2c-&gt;iobase = ioremap(res-&gt;start, resource_size(res)); +if (!mcfi2c-&gt;iobase) { +dev_dbg(&amp;pdev-&gt;dev, "ioremap failed\n"); +status = -ENOMEM; +goto fail1; +} + +mcfi2c-&gt;irq = platform_get_irq(pdev, 0); +if (mcfi2c-&gt;irq &lt; 0) { +dev_dbg(&amp;pdev-&gt;dev, "platform_get_irq failed\n"); +status = -ENXIO; +goto fail2; +} +status = request_irq(mcfi2c-&gt;irq, mcfi2c_irq_handler, 0, pdev-&gt;name, +mcfi2c); +if (status) { +dev_dbg(&amp;pdev-&gt;dev, "request_irq failed\n"); +goto fail2; +} + +mcfi2c-&gt;clk = clk_get(&amp;pdev-&gt;dev, NULL); +if (IS_ERR(mcfi2c-&gt;clk)) { +dev_dbg(&amp;pdev-&gt;dev, "clk_get failed\n"); +status = PTR_ERR(mcfi2c-&gt;clk); +goto fail3; +} +clk_enable(mcfi2c-&gt;clk); + +platform_set_drvdata(pdev, mcfi2c); + +init_completion(&amp;mcfi2c-&gt;completion); + +writeb(mcfi2c_calc_fdr(mcfi2c, pdev-&gt;dev.platform_data), + mcfi2c-&gt;iobase + MCFI2C_FDR); + +writeb(0x00, mcfi2c-&gt;iobase + MCFI2C_ADR); + +mcfi2c_wr_cr(mcfi2c, MCFI2C_CR_IEN); + +pm_runtime_enable(&amp;pdev-&gt;dev); +pm_runtime_get_sync(&amp;pdev-&gt;dev); + +/* if the bus busy (IBB) is set, reset the controller */ +if (mcfi2c_rd_sr(mcfi2c) &amp; MCFI2C_SR_IBB) +mcfi2c_reset(mcfi2c); + +mcfi2c-&gt;adapter.algo= &amp;mcfi2c_algo; +mcfi2c-&gt;adapter.class= I2C_CLASS_HWMON | I2C_CLASS_SPD; +mcfi2c-&gt;adapter.dev.parent= &amp;pdev-&gt;dev; +mcfi2c-&gt;adapter.nr= pdev-&gt;id; +mcfi2c-&gt;adapter.retries= 2; +snprintf(mcfi2c-&gt;adapter.name, sizeof(mcfi2c-&gt;adapter.name), +DRIVER_NAME ".%d", pdev-&gt;id); + +i2c_set_adapdata(&amp;mcfi2c-&gt;adapter, mcfi2c); + +status = i2c_add_numbered_adapter(&amp;mcfi2c-&gt;adapter); +if (status &lt; 0) { +dev_dbg(&amp;pdev-&gt;dev, "i2c_add_numbered_adapter failed\n"); +goto fail4; +} + +pm_runtime_put(&amp;pdev-&gt;dev); + +dev_info(&amp;pdev-&gt;dev, "Coldfire I2C bus driver\n"); + +return 0; + +fail4: +pm_runtime_put(&amp;pdev-&gt;dev); + +clk_disable(mcfi2c-&gt;clk); +clk_put(mcfi2c-&gt;clk); +fail3: +free_irq(mcfi2c-&gt;irq, mcfi2c); +fail2: +iounmap(mcfi2c-&gt;iobase); +fail1: +release_mem_region(res-&gt;start, resource_size(res)); +fail0: +kfree(mcfi2c); + +return status; +} + +static int __devexit mcfi2c_remove(struct platform_device *pdev) +{ +struct mcfi2c *mcfi2c = platform_get_drvdata(pdev); +struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + +/* disable the hardware */ +mcfi2c_wr_cr(mcfi2c, 0); + +platform_set_drvdata(pdev, NULL); +i2c_del_adapter(&amp;mcfi2c-&gt;adapter); +clk_disable(mcfi2c-&gt;clk); +clk_put(mcfi2c-&gt;clk); +free_irq(mcfi2c-&gt;irq, mcfi2c); +iounmap(mcfi2c-&gt;iobase); +release_mem_region(res-&gt;start, resource_size(res)); +kfree(mcfi2c); + +return 0; +} + +#ifdef CONFIG_PM_RUNTIME +static int mcfi2c_runtime_suspend(struct device *dev) +{ +struct mcfi2c *mcfi2c = platform_get_drvdata(to_platform_device(dev)); + +mcfi2c_wr_cr(mcfi2c, 0); +clk_disable(mcfi2c-&gt;clk); + +return 0; +} + +static int mcfi2c_runtime_resume(struct device *dev) +{ +struct mcfi2c *mcfi2c = platform_get_drvdata(to_platform_device(dev)); + +clk_enable(mcfi2c-&gt;clk); +mcfi2c_wr_cr(mcfi2c, MCFI2C_CR_IEN); + +return 0; +} +#endif + +static const struct dev_pm_ops mcfi2c_pm = { +SET_RUNTIME_PM_OPS(mcfi2c_runtime_suspend, mcfi2c_runtime_resume, NULL) +}; + +static struct platform_driver mcfi2c_driver = { +.driver.name= DRIVER_NAME, +.driver.owner= THIS_MODULE, +.driver.pm= &amp;mcfi2c_pm, +.remove= __devexit_p(mcfi2c_remove), +}; + +static int __init mcfi2c_init(void) +{ +return platform_driver_probe(&amp;mcfi2c_driver, mcfi2c_probe); +} +module_init(mcfi2c_init); + +static void __exit mcfi2c_exit(void) +{ +platform_driver_unregister(&amp;mcfi2c_driver); +} +module_exit(mcfi2c_exit); + +MODULE_AUTHOR("Steven King &lt;sfking&lt; at &gt;fdwdc.com&gt;"); +MODULE_DESCRIPTION("I2C-Bus support for Freescale Coldfire processors"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:" DRIVER_NAME); _______________________________________________ uClinux-dev mailing list uClinux-dev&lt; at &gt;uclinux.org http://mailman.uclinux.org/mailman/listinfo/uclinux-dev This message was resent by uclinux-dev&lt; at &gt;uclinux.org To unsubscribe see: http://mailman.uclinux.org/mailman/options/uclinux-dev </pre> Steven King 2012-05-17T02:10:35 http://permalink.gmane.org/gmane.linux.uclinux.devel/20432 <pre> would be good to add a comment so someone doesn't clean this up again. i can post a patch for that though. i know the current struct behavior is ugly, but it's cleaner than previous iterations ;) -mike _______________________________________________ uClinux-dev mailing list uClinux-dev&lt; at &gt;uclinux.org http://mailman.uclinux.org/mailman/listinfo/uclinux-dev This message was resent by uclinux-dev&lt; at &gt;uclinux.org To unsubscribe see: http://mailman.uclinux.org/mailman/options/uclinux-dev</pre> Mike Frysinger 2012-05-16T16:23:44 http://permalink.gmane.org/gmane.linux.uclinux.devel/20431 <pre> No I don't see any existing place that makes any sense. I guess it could be something like a new file include/linux/mtd/uclinux.h. But it looks like Artem is ok with just reverting it to not be static. I am happy to leave it that way if you are. Regards Greg ------------------------------------------------------------------------ Greg Ungerer -- Principal Engineer EMAIL: gerg&lt; at &gt;snapgear.com SnapGear Group, McAfee PHONE: +61 7 3435 2888 8 Gardner Close, FAX: +61 7 3891 3630 Milton, QLD, 4064, Australia WEB: http://www.SnapGear.com _______________________________________________ uClinux-dev mailing list uClinux-dev&lt; at &gt;uclinux.org http://mailman.uclinux.org/mailman/listinfo/uclinux-dev This message was resent by uclinux-dev&lt; at &gt;uclinux.org To unsubscribe see: http://mailman.uclinux.org/mailman/options/uclinux-dev </pre> Greg Ungerer 2012-05-16T11:49:42 http://permalink.gmane.org/gmane.linux.uclinux.devel/20430 <pre>Hi Luis, On 05/16/2012 07:12 PM, Luis Alves wrote: What are the compiler options supplied to gcc? (If you make the kernel with V=1 then you get the full command line trace) Any m68k targeted compiler should be able to generate code for any family member with the right command line options. With the bundled toolchains you may not have the libs generated for your specific CPU member though. Regards Greg ------------------------------------------------------------------------ Greg Ungerer -- Principal Engineer EMAIL: gerg&lt; at &gt;snapgear.com SnapGear Group, McAfee PHONE: +61 7 3435 2888 8 Gardner Close, FAX: +61 7 3891 3630 Milton, QLD, 4064, Australia WEB: http://www.SnapGear.com _______________________________________________ uClinux-dev mailing list uClinux-dev&lt; at &gt;uclinux.org http://mailman.uclinux.org/mailman/listinfo/uclinux-dev This message was resent by uclinux-dev&lt; at &gt;uclinux.org To unsubscribe see: http://mailman.uclinux.org/mailman/options/uclinux-dev </pre> Greg Ungerer 2012-05-16T11:44:08 http://permalink.gmane.org/gmane.linux.uclinux.devel/20428 <pre>Hi Greg, I've solved the missing libraries problem but the toolchain you provided isn't generating proper code for the 68000. I've disassembled the kernel and checked the 'proc_net_ns_init' function, where the kernel is hanging more precisely at the 'memcpy' intruction. So, the memcpy gets compiled into a movel instruction with an odd displacement (causing a bus error). compiled into: [...] 2175b8:217c 6e65 7400 movel #1852142592,%a0&lt; at &gt;(77) 2175be:004d [...] The previous toolchain is generating 4 moveb intructions in this case. I also see some other differences related to move opcodes. For instance, the previous toolchain loads an address content to the stack by doing this: 207104:2f39 001f 54c8 movel 1f54c8 &lt;malloc_sizes+0x1c&gt;,%sp&lt; at &gt;- 20710a:4eb9 0004 2bbc jsr 42bbc &lt;kmem_cache_alloc&gt; The new toolchain is doing this: 21755a:307c 001c moveaw #28,%a0 21755e:d1fc 0020 6d2c addal #2125100,%a0 217564:2f10 movel %a0&lt; at &gt;,%sp&lt; at &gt;- 217566:4eb9 0004 640e jsr 4640e &lt;kmem_cache_alloc&gt; To me this looks Coldfire 'limited' adressing modes. Any suggestion? :| When ever i have the time I'll try to build a toolchain (maybe using gcc 4.7) and check the generated code. Maybe I also could try the code sourcery one, but there is no reference for the 'legacy 68k' family on their download page (only coldfire). Regards, Luis Alves On Tue, May 15, 2012 at 1:32 PM, Greg Ungerer &lt;gerg&lt; at &gt;snapgear.com&gt; wrote: _______________________________________________ uClinux-dev mailing list uClinux-dev&lt; at &gt;uclinux.org http://mailman.uclinux.org/mailman/listinfo/uclinux-dev This message was resent by uclinux-dev&lt; at &gt;uclinux.org To unsubscribe see: http://mailman.uclinux.org/mailman/options/uclinux-dev </pre> Luis Alves 2012-05-16T09:12:58 Search the mailing list at Gmane query http://search.gmane.org/?group=$group=gmane.linux.uclinux.devel