http://blog.gmane.org/gmane.linux.bios hourly 1 1901-01-01T00:00+00:00 http://gmane.org/img/gmane-25t.png http://gmane.org http://permalink.gmane.org/gmane.linux.bios/77271 <pre> And lots of other stuff. There are also one or two well-stocked shops in the city. //Peter </pre> Peter Stuge 2013-05-18T21:43:46 http://permalink.gmane.org/gmane.linux.bios/77270 <pre>There are already PL2303, BeagleBoard, Cortex boards, cables, NET20DC, networking, Huawei E1750 3G dongle and flash chips in Berlin, as well as various general electronics tools, as needed. //Peter </pre> Peter Stuge 2013-05-18T21:40:43 http://permalink.gmane.org/gmane.linux.bios/77269 <pre>Hello, all. I'll be at LinuxTAG and hackathon. This mail is to ask if someone needs some of hw I can take with me (list at the end), I won't take it unless I have requests. Does anybody want to share rooms to save on hotel costs? HW List: PL2303 USB-RS232 converter bus pirate 2 SOIC 8-pin clips Raspberry Pie Thinkpad X201 (coreboot) USB rollable keyboard cables of all kind NET20DC USBdebug gear for network USB wireless USB 3G modems Thinkpad X230 (my next port) Asus A8N-E (corebootable) PLCC32 parallel flash chips PLCC32 FWH/LPC chips PLCC extractor Lemote Yeeloong 2F Lemote Fuloong 2F Lemote Yeeloong 3A Apple Powerbook G4 Too big for transport but I can setup SSH in advance if needed: ia64, alpha, sparc64, SGI Indy, hppa </pre> Vladimir 'φ-coder/phcoder' Serbinenko 2013-05-18T21:13:40 http://permalink.gmane.org/gmane.linux.bios/77268 <pre>Dear coreboot folks, today several devices have more than just one USB debug port, so it makes sense to be able to configure it. Patch »intel/bd82x6x: Add Kconfig options for USB debug port« [1] implements that for Intel BD82x6x. I guess this could be made available to all boards right away. So suggestions where to put these Kconfig variables are very much appreciated. Thanks, Paul [1] http://review.coreboot.org/3240 </pre> Paul Menzel 2013-05-15T15:34:56 http://permalink.gmane.org/gmane.linux.bios/77266 <pre>2013/5/14 Bin X &lt;z2333&lt; at &gt;outlook.com&gt;: coreboot can do that, but you have to spend 'some' time on adding support for your particular mainboard. See http://b2b.gigabyte.com/products/product-page.aspx?pid=3215#sp ("Chipset VIA CN700 chipset with VIA VT8237R Plus") and http://www.coreboot.org/Supported_Chipsets_and_Devices It's very good that you found that programmer parameter. However, the Gigabyte product picture shows that this (non-VXL) board uses LPC flash instead of SPI. What we're interested in is what flashrom's output looks like when there is - your words - no success. Does its output end with many times "&lt;hexadecimal value&gt;:S"? </pre> Idwer Vollering 2013-05-14T20:05:06 http://permalink.gmane.org/gmane.linux.bios/77265 <pre>Am Dienstag, den 14.05.2013, 11:03 +0200 schrieb Paul Menzel: The above was supposed to be `PCI_DEV`. I had not squashed the commits yet. In #coreboor, CareBear\ suggested that I have to access the PCI register in a different way. Suggestions very much welcomed. Thanks, Paul </pre> Paul Menzel 2013-05-14T13:37:04 http://permalink.gmane.org/gmane.linux.bios/77264 <pre>Am Montag, den 13.05.2013, 09:04 +0200 schrieb Paul Menzel: It looks like it is not the same. The BIOS Timer above is more to fit Aaron’s commit. commit c46cc6f149c42653344d6e9f3656a4212fc46cef Author: Aaron Durbin &lt;adurbin&lt; at &gt;chromium.org&gt; Date: Mon Apr 29 16:57:10 2013 -0500 haswell: 24MHz monotonic time implementation Haswell ULT devices have a 24MHz package-level counter. Use this counter to provide a timer_monotonic_get() implementation. Reviewed-on: http://review.coreboot.org/3153 But the problem is, that the register is part of the PCI config space(?) and the Root Complex/PCI stuff is not yet available in ramstage? +#include &lt;stdint.h&gt; +#include &lt;pci_ops.h&gt; +#include &lt;timer.h&gt; + +static struct monotonic_counter { + int initialized; + struct mono_time time; + uint32_t last_value; +} mono_counter; + +static inline uint32_t read_counter_msr(void) +{ + /* D0F0xE4_x0130_80F0 BIOS Timer + * + * This field increments once every microsecond when the timer is + * enabled. The counter rolls over and continues counting when it + * reaches FFFF_FFFFh. A write to this register causes the counter + * to reset and begin counting from the value written. */ + pci_write_config32(CI_DEV(0, 0, 0), 0xe4, 0x013080F0); + + return pci_read_config32(PCI_DEV(0, 0, 0), 0xe4); +} + +void timer_monotonic_get(struct mono_time *mt) +{ + uint32_t current_tick; + uint32_t usecs_elapsed; + + if (!mono_counter.initialized) { + mono_counter.last_value = read_counter_msr(); + mono_counter.initialized = 1; + } + + current_tick = read_counter_msr(); + usecs_elapsed = current_tick - mono_counter.last_value; + + /* Update current time and tick values only if a full tick occurred. */ + if (usecs_elapsed) { + mono_time_add_usecs(&amp;mono_counter.time, usecs_elapsed); + mono_counter.last_value = current_tick; + } + + /* Save result. */ + *mt = mono_counter.time; +} This results in the following hang. 00.000: &lt;00&gt; 00.456: 00.456: 00.456: coreboot-4.0-4160-g41f456b-dirty Tue May 14 00:28:53 CEST 2013 starting... 00.456: BSP Family_Model: 00500f10 00.457: cpu_init_detectedx = 00000000 00.457: agesawrapper_amdinitmmio passed. 00.458: agesawrapper_amdinitreset passed. 00.461: agesawrapper_amdinitearly BSP Family_Model: 00500f10 00.486: cpu_init_detectedx = 00000001 00.486: agesawrapper_amdinitmmio passed. 00.487: agesawrapper_amdinitreset passed. 00.491: agesawrapper_amdinitearly passed. 00.627: agesawrapper_amdinitpost passed. 00.753: agesawrapper_amdinitenv passed. 00.767: Loading image. 00.768: CBFS: loading stage fallback/coreboot_ram &lt; at &gt; 0x200000 (1343544 bytes), entry &lt; at &gt; 0x200000 00.873: Jumping to image. 00.874: coreboot-4.0-4160-g41f456b-dirty Tue May 14 00:28:53 CEST 2013 booting... 00.874: get_pbus: dev is NULL! There are also other timers in the processor cores. 2.4.5 Timers Each core includes the following timers. These timers do not vary in frequency regardless of the current P-state or C-state. • MSR0000_0010 [Time Stamp Counter (TSC)]; the TSC increments at the rate specified by MSRC001_0015[TscFreqSel]. • The APIC timer (APIC380 and APIC390), which decrements at a rate of 2x CLKIN. It looks like that is what AGESA uses and which might be there from the “beginning”. Thanks, Paul </pre> Paul Menzel 2013-05-14T09:03:25 http://permalink.gmane.org/gmane.linux.bios/77263 <pre>Hi Daniel, d-fischer&lt; at &gt;gmx-topmail.de wrote: Always assume no. With the right background and some months of development the answer can become yes. You don't have much choice; either become a coreboot developer, or hire a coreboot developer to work for you, or give up the idea of using coreboot on your machine. If you want to become a developer you'll brick your laptop many times during development, so one thing you need to sort out fairly early is how you will unbrick your laptop. You will typically need to do some soldering in the machine, and you'll need a suitable flash programmer. coreboot folks may be friendly, but it's completely infeasible for anyone else to port coreboot to your machine for you. Adding a new system, even when components are supported like in your case, requires time-intensive work and moderately advanced electronics debugging equipment. (A 33MHz-capable programmable logic analyzer, or experience with programmable logic development in order to hack something.) You'll have to provide a patch, not just information. Nobody else can create a port for you. You're welcome. I'm afraid that seems unlikely. :\ //Peter </pre> Peter Stuge 2013-05-13T20:59:39 http://permalink.gmane.org/gmane.linux.bios/77262 <pre>Hi all, &gt; Any pointers to code already dealing with such indexed registers or Info is on page 150 of that datasheet. D0F0xE0 and D0F0xE4 are used to access D0F0xE4_x[FFFF_FFFF:0000_0000]. To read or write to one of these register, the address is written first into the address register D0F0xE0 and then the data is read from or written to the data register D0F0xE4. You can imagine that as a "window" to some internal address space (in this case address space of SMU) You can even access that through a cmdline: setpci -s 0:0.0 e0.l This will print current register value of e0 So, to read the counter value: setpci -s 0:0.0 e0.l=013080F0 setpci -s 0:0.0 e4.l So, to read the default counter rate: setpci -s 0:0.0 e0.l=013080F1 setpci -s 0:0.0 e4.l Program it to any value: setpci -s 0:0.0 e0.l=013080F0 setpci -s 0:0.0 e4.l=aa55aa55 To program the rate to 42 MHz setpci -s 0:0.0 e0.l=013080F1 setpci -s 0:0.0 e4.l=0000002a The setpci command is equivalent of this code: setpci -s 0:0.0 e0.l=013080F0 setpci -s 0:0.0 e4.l is: pci_write_config32(CI_DEV(0, 0, 0), 0xe4, 0x013080F0); tmp = pci_read_config32(PCI_DEV(0, 0, 0), 0xe4); Happy hacking, Rudolf </pre> Rudolf Marek 2013-05-13T20:19:17 http://permalink.gmane.org/gmane.linux.bios/77261 <pre>Dear coreboot folks,   I admire the coreboot project because it's a fast and up-to-date open source alternative to the proprietary bios crap provided by many vendors. For this reason I am thinking about using coreboot on my Toshiba A100-151 laptop system since it is not supported anymore by Toshiba and even they discontinued to provide all the old drivers for this model in the support section on their homepage (Thank you, you customer-unfriendly profiteers!). How ridiculous that this company has received the German    environmental label "Blue Angel" for some of their products in the past (just a little side note). And even with their locked and constricted Firmware updates I feel somehow as if I should be artificially hindered to use the full potentials of hardware features of my laptop. Just to mention some examples:   - I cannot use the AHCI mode of the SATA controller although the mainboard should be able to switch to this mode. There is no option in the bios and it's always locked to IDE mode. Therefore, the performance of my new SSD is artificially limited to a low level. - Even Toshiba showes on their homepage that 4GB RAM memory are supported by the mainboard, I could only use 3GB at maximum, even after installing diverse 64bit OS such as Ubuntu Linux 12.04 and Windows 7. I guess that some of the missing 1GB RAM will be addressed to the OS and to my ATI video graphic card in particular, although it was shipped with 128MB of dedicated RAM. But again there is no option in the bios settings to manage the VGA Shared Memory. - Few time ago, I couldn't enable the Intel VT feature of my CPU. However, I found a workaround by flashing a modded custom bios from another forum which enabled some great features. But unfortunately, there is still no ahci support :-(   In short, after reading a lot of tutorials in the internet and trying different solutions in Linux and Windows OS (e.g. using registry modifications, pre-boot parameters in grub2 mainly with the command "setpci" as well as trying a MBR mod at the end), I wasn't successful to enable ahci mode and I recognized in general that the bios restrictions by Toshiba obviously represent the biggest problem.   But now to coreboot: So far, I made some first experimental steps by testing coreboot in a qemu environment. At least, in qemu I succeeded! The documentation on the coreboot homepage was of great help.   However, I am still unsure if coreboot could work on my machine under real conditions after flashing. And because of my very limmited technical knowledge, I would appreciate some help and advices very much in order to avoid making mistakes or to brick my laptop at the end. Therefore, I hope to meet here some friendly persons who are willing to help.   In view of the fact, that my model hasn't been supported yet by coreboot I would like to provide all needed information I could get in the following part (with my personal comments marked by "###“):     ------ A very brief description of my system:    board vendor:    Toshiba   board name:    Satellite A100-151 ### please, don't get confused because later you will also see the product name "Satellite M110". This is due to the modded bios with advanced features which I have flashed. The right name is "Satellite A100-151".   CPU:        Intel Core2Duo T7200 ### I have upgraded the CPU. Maybe following output from "dmidecode" could be usefull as well:   Handle 0x0004, DMI type 4, 35 bytes Processor Information     Socket Designation: U2E1     Type: Central Processor     Family: Other     Manufacturer: Intel     ID: F6 06 00 00 FF FB EB BF     Signature: Type 0, Family 6, Model 15, Stepping 6     Flags:         FPU (Floating-point unit on-chip)         VME (Virtual mode extension)         DE (Debugging extension)         PSE (Page size extension)         TSC (Time stamp counter)         MSR (Model specific registers)         PAE (Physical address extension)         MCE (Machine check exception)         CX8 (CMPXCHG8 instruction supported)         APIC (On-chip APIC hardware supported)         SEP (Fast system call)         MTRR (Memory type range registers)         PGE (Page global enable)         MCA (Machine check architecture)         CMOV (Conditional move instruction supported)         PAT (Page attribute table)         PSE-36 (36-bit page size extension)         CLFSH (CLFLUSH instruction supported)         DS (Debug store)         ACPI (ACPI supported)         MMX (MMX technology supported)         FXSR (FXSAVE and FXSTOR instructions supported)         SSE (Streaming SIMD extensions)         SSE2 (Streaming SIMD extensions 2)         SS (Self-snoop)         HTT (Multi-threading)         TM (Thermal monitor supported)         PBE (Pending break enabled)     Version: Intel(R) Core(TM)2 CPU         T7200     Voltage: 3.3 V     External Clock: Unknown     Max Speed: 2048 MHz     Current Speed: 2000 MHz     Status: Populated, Enabled     Upgrade: ZIF Socket     L1 Cache Handle: 0x0005     L2 Cache Handle: 0x0006     L3 Cache Handle: Not Provided     Serial Number: Not Specified     Asset Tag: Not Specified     Part Number: Not Specified     northbridge:    8086:27a0 (i945GM)   ### Here is some further information extraced by using the program "PC Wizard 2012" in Windows. However, I am not sure if this will be usefull. Furthermore, this application reports "Intel i945PM" as northbridge in contrast to the Linux output.   Codename :    Calistoga  Revision :     Stepping :    A3   Bus Speed :    .24 M FSB Frequenz :    MHz (QDR) FSB max. Support :    MHz  RAM max. Support :    DDR2 (667)     southbridge:    SouthBridge :    8086:27b9 (ICH7-M)   ### Here is what the Windows program "PC Wizard 2012" reports: GBM (ICH7-M/U) LPC Interface Controller Revision :           ------ output of "lspci -tvnn"    -[0000:00]-+-00.0  Intel Corporation Mobile 945GM/PM/GMS, 943/940GML and 945GT Express Memory Controller Hub [8086:27a0] +-01.0-[01]----00.0  Advanced Micro Devices [AMD] nee ATI M56P [Radeon Mobility X1600] [1002:71c5] +-1b.0  Intel Corporation N10/ICH 7 Family High Definition Audio Controller [8086:27d8] +-1c.0-[02]-- +-1c.1-[03-04]-- +-1c.2-[05-06]----00.0  Intel Corporation PRO/Wireless 3945ABG [Golan] Network Connection [8086:4222] +-1d.0  Intel Corporation N10/ICH 7 Family USB UHCI Controller #1 [8086:27c8] +-1d.1  Intel Corporation N10/ICH 7 Family USB UHCI Controller #2 [8086:27c9] +-1d.2  Intel Corporation N10/ICH 7 Family USB UHCI Controller #3 [8086:27ca] +-1d.3  Intel Corporation N10/ICH 7 Family USB UHCI Controller #4 [8086:27cb] +-1d.7  Intel Corporation N10/ICH 7 Family USB2 EHCI Controller [8086:27cc] +-1e.0-[07-0b]--+-06.0  Texas Instruments PCIxx12 Cardbus Controller [104c:8039] |               +-06.1  Texas Instruments PCIxx12 OHCI Compliant IEEE 1394 Host Controller [104c:803a] |               +-06.2  Texas Instruments 5-in-1 Multimedia Card Reader (SD/MMC/MS/MS PRO/xD) [104c:803b] |               +-06.3  Texas Instruments PCIxx12 SDA Standard Compliant SD Host Controller [104c:803c] |               \-08.0  Intel Corporation PRO/100 VE Network Connection [8086:1092] +-1f.0  Intel Corporation 82801GBM (ICH7-M) LPC Interface Bridge [8086:27b9] +-1f.2  Intel Corporation 82801GBM/GHM (ICH7-M Family) SATA Controller [IDE mode] [8086:27c4] \-1f.3  Intel Corporation N10/ICH 7 Family SMBus Controller [8086:27da]     ------ output of "superiotool -dV"   superiotool r6637 Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0xffff, rev=0xff Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0xffff, rev=0xff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for ITE Super I/O (init=standard) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=standard) at 0x2e... Failed. Returned data: id=0x3503, rev=0x0 Probing for ITE Super I/O (init=it8502e) at 0x2e... Failed. Returned data: id=0x3503, rev=0x0 Probing for ITE Super I/O (init=it8761e) at 0x2e... Failed. Returned data: id=0x3503, rev=0x0 Probing for ITE Super I/O (init=it8228e) at 0x2e... Failed. Returned data: id=0x3503, rev=0x0 Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0x3503, rev=0x0 Probing for ITE Super I/O (init=standard) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8661f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8671f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for NSC Super I/O at 0x2e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x4e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x15c... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x164e... Failed. Returned data: port=0xff, port+1=0xff Probing for Nuvoton Super I/O at 0x164e... Failed. Returned data: chip_id=0xffff Probing for Nuvoton Super I/O (sid=0xfc) at 0x164e... Failed. Returned data: sid=0xff, id=0xffff, rev=0x00 Probing for Nuvoton Super I/O at 0x2e... Failed. Returned data: chip_id=0xffff Probing for Nuvoton Super I/O (sid=0xfc) at 0x2e... Failed. Returned data: sid=0xff, id=0xffff, rev=0x00 Probing for Nuvoton Super I/O at 0x4e... Failed. Returned data: chip_id=0xffff Probing for Nuvoton Super I/O (sid=0xfc) at 0x4e... Failed. Returned data: sid=0xff, id=0xffff, rev=0x00 Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Failed. Returned data: id=0x35, rev=0x03 Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... Failed. Returned data: id=0x00, rev=0x00 Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for VIA Super I/O at 0x3f0... PCI device 1106:0686 not found. Probing for Server Engines Super I/O at 0x2e... Failed. Returned data: id=0xffff, rev=0xff No Super I/O found   ### The Windows program "HWiNFO64" also showes that the Super-IO/LPC Chip is unknown.     ------ output of "ectool"   EC RAM:   : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  : 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  : 00 00 08 1b 00 00 00 00 00 0a 02 00 23 00 7f 68  a0: 00 00 01 07 00 00 03 00 00 00 00 00 00 00 00 00  b0: 00 00 00 00 00 00 01 00 00 00 00 00 00 00 00 00  c0: 00 62 67 2d 41 00 00 00 ff 03 00 41 01 00 00 36  d0: 00 00 00 00 00 00 00 00 01 06 00 00 31 00 00 00  e0: 7e 00 00 00 00 00 1e 00 00 00 00 00 00 00 00 00  f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    Not dumping EC IDX RAM.   ### Concerning the Embedded Controller (EC) I could get some little information by the Windows tool "Rw version 1.6" which might be usefull for an advanced technician. According to the information it's an EC6662.     ------ output of "flashrom -V"   flashrom v0.9.5.2-r1517 on Linux 3.7.0-7-generic (x86_64), built with libpci 3.1.8, GCC 4.6.3, little endian flashrom is free software, get the source code at http://www.flashrom.org   Calibrating delay loop... OS timer resolution is 1 usecs, 1989M loops per second, 10 myus = 10 us, 100 myus = 101 us, 1000 myus = 998 us, 10000 myus = 10162 us, 4 myus = 6 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "TOSHIBA" DMI string system-product-name: "Satellite M110" DMI string system-version: "PSMB0U-1234567" DMI string baseboard-manufacturer: "Intel Corporation" DMI string baseboard-product-name: "CAPELL VALLEY(NAPA) CRB" DMI string baseboard-version: "Not Applicable" DMI string chassis-type: "Other" DMI chassis-type is not specific enough.   ### I add here some part of the output from "dmidecode" as well with extracted information only about relevant bios parameters. By "dmidecode" I could figure out that ROM Size is only 1024 kB:   Handle 0x0000, DMI type 0, 24 bytes BIOS Information     Vendor: Phoenix Technologies LTD     Version: 6.00        Release Date: 07/12/2007     Address: 0xE4480     Runtime Size: 113536 bytes     ROM Size: 1024 kB     Characteristics:         ISA is supported         PCI is supported         PC Card (PCMCIA) is supported         PNP is supported         APM is supported         BIOS is upgradeable         BIOS shadowing is allowed         ESCD support is available         Boot from CD is supported         ACPI is supported         USB legacy is supported         AGP is supported         BIOS boot specification is supported         Targeted content distribution is supported     ------ URL to the mainboard specifications page: http://www.toshiba.de/discontinued-products/satellite-a100-151/?PRODUCT_ID=114071   ### Unfortunately, I could only find this German website. But I have access to the manual. However, it does not provide much additional information which would be usefull here.       ------ Any other relevant information:   As I have mentioned before, I have upgraded my system including a new CPU (Intel Core2Duo T7200), more RAM (2 x 2GB, identical and  from the same vendor) and a SSD. Furthermore I have flashed a modded custom bios which has enabled some more features and seems to work perfectly untill now. However, after the bios mod the model name has been changed.      To end with, I would like to say thank you for your commitment concerning this great open source projet and especially for reading my long message! As I explained I am still a beginner, comming from a completely different working field, but having some ambition to use open source software. I would appreciate your support so that coreboot might natively run on my system.   -- With best regards, Daniel     </pre> d-fischer< at >gmx-topmail.de 2013-05-13T19:33:09 http://permalink.gmane.org/gmane.linux.bios/77260 <pre>Dear coreboot folks, to read the value of the BIOS Timer (section 2.11.4 of the BIOS and Kernel Developer’s Guide (BKDG) for the AMD Family 14 processors [1]), I am stuck at how to do that. Below is the register description from the BKDG. D0F0xE4_x0130_80F0 BIOS Timer ----------------------------- Reset: 0000_0000h. ----------------------------- Bits 31:0 Description MicroSeconds. Read-write; updated-by hardware. This field increments once every microsecond when the timer is enabled. The counter rolls over and continues counting when it reaches FFFF_FFFFh. A write to this register causes the counter to reset and begin counting from the value written. I could not find any wrapper(?) function in the non-vendor code for that. In the vendor code directory `src/vendorcode/amd/agesa/f14/`, I found only `PcieRegisterRead`, which looks “hard” to access from outside. $ git grep -i iocf8 $ git grep -i d0f0xe4 src/vendorcode/amd/agesa/f14 Any pointers to code already dealing with such indexed registers or instructions how to do that would help me very much. Thanks, Paul [1] http://www.coreboot.org/Datasheets#AMD_Fam14 BKDG 43170 Rev 3.13 – February 17, 2012 </pre> Paul Menzel 2013-05-13T16:56:59 http://permalink.gmane.org/gmane.linux.bios/77259 <pre>Am Sonntag, den 12.05.2013, 15:40 +0200 schrieb Peter Stuge: Probably, yes. As this area is new to me, I prefer to ask and get confirmation to be sure. I totally forgot about that. There is coreboot code for the K8 and Family 10h processors, if I am not mistaken. AGESA is there for Family 10h to 15h processors. Only a little. Having an ASRock E350M1, I am looking into the Family 14h family. There seems to be no TSC stuff in `src/cpu/amd`. But the AMD vendor code seems to have it. $ git grep -i tsc src/vendorcode/amd/agesa/f14/ `AGESA.h` has a struct `MEM_DATA_STRUCT` where the frequency is put into. $ nl -ba src/vendorcode/amd/agesa/f14/AGESA.h | grep -B 40 -A 5 TSC […] 1700/// 1701/// Contains all data relevant to Memory Initialization. 1702/// 1703typedef struct _MEM_DATA_STRUCT { 1704 IN AMD_CONFIG_PARAMS StdHeader; ///&lt; Standard configuration header 1705 1706 IN MEM_PARAMETER_STRUCT *ParameterListPtr; ///&lt; List of input Parameters 1707 1708 OUT MEM_FUNCTION_STRUCT FunctionList; ///&lt; List of function Pointers 1709 1710 IN OUT AGESA_STATUS (*GetPlatformCfg[MAX_PLATFORM_TYPES]) (struct _MEM_DATA_STRUCT *MemData, UINT8 SocketID, CH_DEF_STRUCT *CurrentChannel); ///&lt; look-up platform info 1711 1712 IN OUT BOOLEAN (*ErrorHandling)(struct _DIE_STRUCT *MCTPtr, UINT8 DCT, UINT16 ChipSelMask, AMD_CONFIG_PARAMS *StdHeader); ///&lt; Error Handling 1713 1714 1715 OUT MEM_SOCKET_STRUCT SocketList[MAX_SOCKETS_SUPPORTED]; ///&lt; Socket list for memory code. 1716 ///&lt; SocketList is a shortcut for IBVs to retrieve training 1717 ///&lt; and timing data for each channel indexed by socket/channel, 1718 ///&lt; eliminating their need to parse die/dct/channel etc. 1719 ///&lt; It contains pointers to the populated data structures for 1720 ///&lt; each channel and skips the channel structures that are 1721 ///&lt; unpopulated. In the case of channels sharing the same DCT, 1722 ///&lt; the pTimings pointers will point to the same DCT Timing data. 1723 1724 OUT DIE_STRUCT *DiesPerSystem; ///&lt; Pointed to an array of DIE_STRUCTs 1725 OUT UINT8 DieCount; ///&lt; Number of MCTs in the system. 1726 1727 IN SPD_DEF_STRUCT *SpdDataStructure; ///&lt; Pointer to SPD Data structure 1728 1729 IN OUT struct _PLATFORM_CONFIGURATION *PlatFormConfig; ///&lt; Platform profile/build option config structure 1730 1731 IN OUT BOOLEAN IsFlowControlSupported; ///&lt; Indicates if flow control is supported 1732 1733 OUT UINT32 TscRate; ///&lt; The rate at which the TSC increments in megahertz. 1734 1735} MEM_DATA_STRUCT; […] With $ git grep -i tsc src/vendorcode/amd/agesa/f14/ | grep -i rate […] src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Utilities.c: * &lt; at &gt;CpuServiceMethod{::F_CPU_GET_TSC_RATE}. src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Utilities.c:F14GetTscRate ( src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Utilities.h:F14GetTscRate ( […] I found `F14GetTscRate`. $ nl -ba src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Utilities.c […] 213/*---------------------------------------------------------------------------------------*/ 214/** 215 * Determines the rate at which the executing core's time stamp counter is 216 * incrementing. 217 * 218 * &lt; at &gt;CpuServiceMethod{::F_CPU_GET_TSC_RATE}. 219 * 220 * &lt; at &gt;param[in] FamilySpecificServices The current Family Specific Services. 221 * &lt; at &gt;param[out] FrequencyInMHz TSC actual frequency. 222 * &lt; at &gt;param[in] StdHeader Header for library and services. 223 * 224 * &lt; at &gt;return The most severe status of all called services 225 */ 226AGESA_STATUS 227F14GetTscRate ( 228 IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, 229 OUT UINT32 *FrequencyInMHz, 230 IN AMD_CONFIG_PARAMS *StdHeader 231 ) 232{ 233 UINT64 MsrReg; 234 PSTATE_CPU_FAMILY_SERVICES *FamilyServices; 235 236 FamilyServices = NULL; 237 GetFeatureServicesOfCurrentCore (&amp;PstateFamilyServiceTable, (const VOID **)&amp;FamilyServices, StdHeader); 238 ASSERT (FamilyServices != NULL); 239 240 LibAmdMsrRead (0xC0010015, &amp;MsrReg, StdHeader); 241 if ((MsrReg &amp; 0x01000000) != 0) { 242 return (FamilyServices-&gt;GetPstateFrequency (FamilyServices, 0, FrequencyInMHz, StdHeader)); 243 } else { 244 return (FamilySpecificServices-&gt;GetCurrentNbFrequency (FamilySpecificServices, FrequencyInMHz, StdHeader)); 245 } 246} […] So there is the infrastructure already. The only problem is how to hook this up into coreboot. Create `src/cpu/amd/agesa/tsc_delay.c` and somehow call the AGESA `F14GetTscRate()` from it? Thanks, Paul </pre> Paul Menzel 2013-05-13T07:04:46 http://permalink.gmane.org/gmane.linux.bios/77258 <pre> Isn't that quite clear from the text that you quoted? Yes and no. We can do this for coreboot's own code for AMD platforms, but it obviously does not make much sense to hack this into AGESA if there are not already provisions for it. Since AGESA is the only thing relevant going forward the question is what AGESA needs, timing-wise. Have you checked? //Peter </pre> Peter Stuge 2013-05-12T13:40:03 http://permalink.gmane.org/gmane.linux.bios/77257 <pre>Dear coreboot folks, do you know if the timer mentioned in the BIOS and Kernel Developer’s Guide (BKGD) for the AMD Family 14h processors [1] 2.11.4 BIOS Timer The root complex implements a 32-bit microsecond timer (see D0F0xE4_x0130_80F0 and D0F0xE4_x0130_80F1) that the BIOS can use to accurately time wait operations between initialization steps. To ensure that BIOS waits a minimum number of microseconds between steps BIOS should always wait for one microsecond more than the required minimum wait time. could be used for implementing `tsc_freq_mhz()` as done for Intel Haswell processors? The Wikipedia article for Time Stamp Counter (TSC) claims that since AMD family 10h processors a constant TSC is integrated [2]. Indeed, checking the processor flags under GNU/Linux, the flag `tsc_constant` is present. $ grep -i tsc /proc/cpuinfo flags: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc nonstop_tsc extd_apicid aperfmperf pni monitor ssse3 cx16 popcnt lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch ibs skinit wdt arat hw_pstate npt lbrv svm_lock nrip_save pausefilter flags: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc nonstop_tsc extd_apicid aperfmperf pni monitor ssse3 cx16 popcnt lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch ibs skinit wdt arat hw_pstate npt lbrv svm_lock nrip_save pausefilter Suggestions, if this should be shared and how the files should be named are appreciated. Thanks, Paul [1] http://review.coreboot.org/3169 [2] http://www.coreboot.org/Datasheets#AMD_Fam14 [3] http://en.wikipedia.org/wiki/Time_Stamp_Counter#Implementation_in_various_processors </pre> Paul Menzel 2013-05-12T11:42:04 http://permalink.gmane.org/gmane.linux.bios/77256 <pre>Hi, Paul Menzel wrote: Sure. No need to write so much text though. :) //Peter </pre> Peter Stuge 2013-05-11T23:30:04 http://permalink.gmane.org/gmane.linux.bios/77255 <pre>Dear coreboot folks, since yesterday the tree is broken [1] due to merging the following commits [2][3] without their dependencies as they were not pushed as a branch [4]. commit b8b3e8bff32ee7dddcacec11e015f6683783eb2f Author: Denis 'GNUtoo' Carikli &lt;GNUtoo&lt; at &gt;no-log.org&gt; Date: Thu May 9 16:14:59 2013 +0200 Asus M4A785T-M: Add CMOS defaults. commit f90071faeee3358748d0c8d31e46721b53241e28 Author: Denis 'GNUtoo' Carikli &lt;GNUtoo&lt; at &gt;no-log.org&gt; Date: Thu May 9 23:35:18 2013 +0200 PC Engines ALIX.1C: Add CMOS defaults. The following two boards fail to build [1]. board.i386/asus/m4a785t-m board.i386/pcengines/alix1c Could the two commits be reverted as it does not look like that [4] is going to be approved soon. Thanks, Paul [1] http://qa.coreboot.org/job/coreboot-gerrit/6251/ [2] http://review.coreboot.org/#/c/3224/ [3] http://review.coreboot.org/#/c/3229/ [4] http://review.coreboot.org/#/c/3223/ </pre> Paul Menzel 2013-05-11T23:16:06 http://permalink.gmane.org/gmane.linux.bios/77254 <pre>Dear David, Am Freitag, den 10.05.2013, 01:21 -0600 schrieb David Hubbard: very strange. I did not find, how these troubles started. Was not the ASUS F2A85-M and these RAM modules work fine in the past? I have no idea if the SMBus writes in there are actually correct as I do not have the board to verify it. As Rudolf suggested, try with the 1.6 Volts. But if I am not mistaken you did so already without any luck. What voltage is used with the vendor BIOS? Could you test with other modules maybe borrowed from another system or a friend? Good idea. I understood the code the way, that this is only needed, when autodetection fails. But the values should be autodetected. Maybe you can add some output in the loops above to see where it actually fails. As a workaround you can try to hard code your values though. Maybe there is an option in AGESA where you can limit the maximum frequency. $ more src/mainboard/asus/f2a85-m/buildOpts.c […] #define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY […] #define BLDCFG_MEMORY_CLOCK_SELECT DDR1600_FREQUENCY […] Thanks. The list’s size limit should definitely be raised so such logs can be attached to the message. Any idea, what the above means? I am sorry to not be able to offer you a solution. Could you try to find out with `bios_extract` for example what AGESA version the vendor BIOS uses. Thanks, Paul PS: David, Google Mail changed the compose interface and they send HTML message in addition to text by default. Could you change that to just plain text please [3][4]? [3] http://www.mail-archive.com/gmail-users&lt; at &gt;googlegroups.com/msg00330.html [4] http://en.opensuse.org/openSUSE:Mailing_list_netiquette </pre> Paul Menzel 2013-05-11T20:20:31 http://permalink.gmane.org/gmane.linux.bios/77253 <pre>Dear coreboot folks, looking at how to split up the patch for the Lenovo X201 southbridge support [1], commit 92ba16cf9fabcf478c225dff687ae717666b502d Author: Vladimir Serbinenko &lt;phcoder&lt; at &gt;gmail.com&gt; Date: Sun Mar 31 22:22:10 2013 +0200 intel/bd82x6x: Support mobile 5 southbridge I stumbled over `CONFIG_USBDEBUG_DEFAULT_PORT`. $ git describe 4.0-3936-g92ba16c $ git grep -A3 USBDEBUG_DEFAULT_PORT src/console/Kconfig:config USBDEBUG_DEFAULT_PORT src/console/Kconfig- int "Default USB port to use as Debug Port" src/console/Kconfig- default 1 src/console/Kconfig- depends on USBDEBUG &amp;&amp; !SOUTHBRIDGE_INTEL_I82801GX &amp;&amp; !SOUTHBRIDGE_AMD_SB600 -- src/console/console.c: enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); src/console/console.c- early_usbdebug_init(); src/console/console.c-#endif src/console/console.c-#if CONFIG_CONSOLE_SERIAL -- src/southbridge/amd/sb600/Kconfig:config USBDEBUG_DEFAULT_PORT src/southbridge/amd/sb600/Kconfig- int src/southbridge/amd/sb600/Kconfig- default 0 src/southbridge/amd/sb600/Kconfig- -- src/southbridge/intel/bd82x6x/Kconfig:config USBDEBUG_DEFAULT_PORT src/southbridge/intel/bd82x6x/Kconfig- int src/southbridge/intel/bd82x6x/Kconfig- default 2 src/southbridge/intel/bd82x6x/Kconfig- -- src/southbridge/intel/i82801gx/Kconfig:config USBDEBUG_DEFAULT_PORT src/southbridge/intel/i82801gx/Kconfig- int src/southbridge/intel/i82801gx/Kconfig- default 1 src/southbridge/intel/i82801gx/Kconfig- -- src/southbridge/intel/i82801ix/Kconfig:config USBDEBUG_DEFAULT_PORT src/southbridge/intel/i82801ix/Kconfig- int src/southbridge/intel/i82801ix/Kconfig- default 1 src/southbridge/intel/i82801ix/Kconfig- 1. Is there an easier way to handle this? I assume the complexity is due to the fact, that boards have different defaults? Is default default 1 default 0 if SOUTHBRIDGE_AMD_SB600 a shorter alternative? 2. The other thing is probably under what menu item this option is displayed at. If under Console or Chipset. Do you have other suggestions? Shall I prepare a commit to change the code as suggested above? Thanks, Paul [1] http://review.coreboot.org/#/c/2995/ </pre> Paul Menzel 2013-05-11T13:21:29 http://permalink.gmane.org/gmane.linux.bios/77252 <pre>Hello. I'm Ayush from India and I have applied to coreboot for GSoc 2013. My proposal is on developing a cheap test rig for the distributed firmware test environment and I have gone through the material on Distributed Test Environment given in GSoc ideas page. I wish to know how many firmware test servers are being used and how many systems under test are present in total. Are they in the same office? And what type of flash chips would you want the test-rig to be able to program? Do you need support for parallel, LPC, FWH flash? Please suggest improvements in my GSoc proposal if possible: http://www.google-melange.com/gsoc/proposal/review/google/gsoc2013/ayush3504/1#&lt;http://www.google-melange.com/gsoc/proposal/review/google/gsoc2013/ayush3504/1&gt; Thanks </pre> Ayush Sagar 2013-05-11T06:13:53 http://permalink.gmane.org/gmane.linux.bios/77251 <pre>Hi all, There seems to be a problem in the code logic, Paul should know more. Maybe playing with the SMBus write and set voltage to 165 might help? Unfortunately I don't know. Hope some AGESA expert will step in. I'm AFK for the weekend so I can't help more. Have a look to the mainboard manual, i think dimm labeled A1 is in fact the second channel and not the first one. Please give a try in other slots too. Sorry for the short answer, I travel soonish AFK. Thanks Rudolf </pre> Rudolf Marek 2013-05-10T08:30:31 http://permalink.gmane.org/gmane.linux.bios/77250 <pre>Hi Rudolf, Paul, I pulled the version from http://review.coreboot.org/#/c/3200/ but my F2A85-M still halts in the same place: ASSERTION FAILED: file 'src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmExcludeDimm.c', line 263 I am using CONFIG_BOARD_ASUS_F2A85_M_DDR3_VOLT_150 I uncommented the #define IDSOPT_IDS_ENABLED in src/mainboard/asus/f2a85-m/OptionsIds.h and captured the serial output. What do you think I should pursue first, option A or B: Option A is where AGESA says: [0000000000000001] Start MemFInitTableDrive End It sounds like AGESA needs a table with Rtt entries? Option B is where AGESA says: If DDR3-667 works but AGESA fails at DDR3-1600, is it possible to go back to DDR3-667 or try an intermediate speed, say DDR3-1333 ? I put a sample log at https://gist.github.com/davidhubbard/5552910 Here are some things I did: 1. cold boot after removing AC power for ~30 s 2. try the other DIMM in slot A1 (still just a single DIMM in the machine) 3. hit the reset switch a couple of times The manufacturer page for the memory says: [1] Non-ECC Tested Speed DDR3-2133 MHz Tested Latency 11-11-11-30 2N Tested Voltage 1.5 -1.6V SPD Speed 1600 MHz SPD Voltage 1.5V Some useful snippets from the log: MemoryClockSelect : 800 AmdMemAuto: Start MEM PARAMS: BottomIo : 00E0 MemHoleRemap : 1 LimitBelow1TB : 1 UserTimingMode : 0 MemClockValue : 800 BankIntlv : 1 NodeIntlv : 0 ChannelIntlv : 1 EccFeature : 0 PowerDown : 1 OnLineSpare : 0 Parity : 0 BankSwizzle : 1 MemClr : 1 UmaMode : 1 UmaSize : 8192 MemRestoreCtl : 0 SaveMemContextCtl : 0 ExternalVrefCtl : 0 ForceTrainMode : 2 Node0: 1.5V -&gt; 800MHz MemClkFreq: 333 MHz MemClkFreq changed: 333 MHz -&gt; 800 MHz [1] http://www.gskill.com/products.php?index=397 [2] this is the same product: http://www.newegg.com/Product/Product.aspx?Item=N82E16820231468 </pre> David Hubbard 2013-05-10T07:21:26 Search the mailing list at Gmane query http://search.gmane.org/?group=$group=gmane.linux.bios