gmane.linux.bios

Re: make und Git: fatal: No names found, cannot describe anything.

Patrick Georgi — 2012-05-25T07:13:11

Am Do 24 Mai 2012 22:09:18 CEST schrieb Paul Menzel:
Indeed. I fixed it. Thanks for the heads up.


Patrick

Patch merged into coreboot/master: 88a1ccf nvramtool:use C99 PRIx64 / PRId64 for uint64_t variables

2012-05-25T06:01:39

the following patch was just integrated into master:
commit 88a1ccfa55bad83429c09acdb3cb6e2aa84cb03e
Author: Stefan Reinauer <reinauer< at >chromium.org>
Date:   Thu May 24 13:36:30 2012 -0700

    nvramtool: use C99 PRIx64 / PRId64 for uint64_t variables
    
    In printf/printk, using %lld or %ld for uint64_t will warn on either
    64bit or 32bit machines.  However, C99 defines PRIx64 / PRId64 to
    provide the right modifiers for printing uint64_t variables. Use them
    instead.
    
    Change-Id: I68df5d069a1e99d1a75885173ddfd7815197afea
    Signed-off-by: Stefan Reinauer <reinauer< at >google.com>

Reviewed-By: Patrick Georgi <patrick< at >georgi-clan.de> at Fri May 25 08:01:34 2012, giving +2
See http://review.coreboot.org/1053 for details.

-gerrit

Patch merged into coreboot/master: c960958 Fix size_tfor certain versions of GCC

2012-05-25T06:00:45

the following patch was just integrated into master:
commit c960958a82b43dc4401d8f300e0d90daefc9341f
Author: Stefan Reinauer <reinauer< at >chromium.org>
Date:   Mon May 14 13:21:08 2012 -0700

    Fix size_t for certain versions of GCC
    
    When compiling coreboot with the latest ChromeOS toolchain, GCC
    complains that some printk calls use %zu in connection with size_t
    types since it resolves the typedefs to long unsigned int.
    
    The problem is solved by using the GCC built-in __SIZE_TYPE__ if it
    exists and define __SIZE_TYPE__ to long unsigned int otherwise.
    
    Change-Id: I449c3d385b5633a05e57204704e981de6e017b86
    Signed-off-by: Stefan Reinauer <reinauer< at >google.com>

Reviewed-By: Patrick Georgi <patrick< at >georgi-clan.de> at Fri May 25 08:00:43 2012, giving +2
See http://review.coreboot.org/1040 for details.

-gerrit

Re: [AMD] Persimmon

2012-05-25T02:36:28

Hello Zheng,


Yes, I have tested AMD Union Station on non persimmon MB, and it will hang 0x39.
This MB is not Union Station, it just quite close it.
So I guess these differences make it hang.
Then I get persimmon MB from AMD, I think this MB are all the same with coreboot support MBs
and it could boot normally, but it not ...
I found this persimmon MB is RevA, I am not sure it is a problem or not.

Finally, I use oscilloscope to check LPC signal and nothing found.

It is amazing that no LPC or PCI debug card signal, I don't know where it stop?


I guess, just guess, have you checked the input clkin in F81865? It has two options, 48MHz or 24MHz.
You should set in superio register based on the actual input clock freq.

Thanks for your help,
Martin

-----Original Message-----
From: Bao, Zheng [mailto:Zheng.Bao< at >amd.com] 
Sent: Thursday, May 24, 2012 1:34 PM
To: martin.meng (孟憲君 - MIC)
Cc: 'coreboot< at >coreboot.org'
Subject: RE: [coreboot] [AMD] Persimmon

Hi, Martin,
Are you test on persimmon or other board which is quite close it?

I guess, just guess, have you checked the input clkin in F81865? It has two options, 48MHz or 24MHz.
You should set in superio register based on the actual input clock freq.



Zheng (Joe)

Patch set updated for coreboot: b3d2676 Reduce defaultverbosity of SPI flash drivers

Stefan Reinauer — 2012-05-24T21:31:25

Stefan Reinauer (stefan.reinauer< at >coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1045

-gerrit

commit b3d2676231863076a3a3965142aeda130ea3f423
Author: Stefan Reinauer <reinauer< at >chromium.org>
Date:   Wed May 23 11:03:29 2012 -0700

    Reduce default verbosity of SPI flash drivers
    
    Only print PP: lines if CONFIG_DEBUG_SPI_FLASH is enabled.
    
    Change-Id: If25e916ecb585f37c90d42980e933a6cd1a3d956
    Signed-off-by: Stefan Reinauer <reinauer< at >google.com>
---
 src/drivers/spi/eon.c      |    2 ++
 src/drivers/spi/macronix.c |    2 ++
 src/drivers/spi/spansion.c |    2 ++
 src/drivers/spi/stmicro.c  |    2 ++
 src/drivers/spi/winbond.c  |    2 ++
 5 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/src/drivers/spi/eon.c b/src/drivers/spi/eon.c
index b7c0630..7d9bc44 100644
--- a/src/drivers/spi/eon.c
+++ b/src/drivers/spi/eon.c
< at >< at > -85,9 +85,11 < at >< at > static int eon_write(struct spi_flash *flash,
 cmd[2] = page_addr;
 cmd[3] = byte_addr;
 
+#if CONFIG_DEBUG_SPI_FLASH
 printk(BIOS_SPEW,
     "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",
      buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
+#endif
 
 ret = spi_flash_cmd(flash->spi, CMD_EN25Q128_WREN, NULL, 0);
 if (ret < 0) {
diff --git a/src/drivers/spi/macronix.c b/src/drivers/spi/macronix.c
index 84e79ef..f74eb4f 100644
--- a/src/drivers/spi/macronix.c
+++ b/src/drivers/spi/macronix.c
< at >< at > -141,9 +141,11 < at >< at > static int macronix_write(struct spi_flash *flash,
 cmd[2] = (offset >> 8) & 0xff;
 cmd[3] = offset & 0xff;
 
+#if CONFIG_DEBUG_SPI_FLASH
 printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }"
      " chunk_len = %zu\n",
      buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
+#endif
 
 ret = spi_flash_cmd(flash->spi, CMD_MX25XX_WREN, NULL, 0);
 if (ret < 0) {
diff --git a/src/drivers/spi/spansion.c b/src/drivers/spi/spansion.c
index 5479cae..511091b 100644
--- a/src/drivers/spi/spansion.c
+++ b/src/drivers/spi/spansion.c
< at >< at > -162,9 +162,11 < at >< at > static int spansion_write(struct spi_flash *flash,
 cmd[2] = page_addr;
 cmd[3] = byte_addr;
 
+#if CONFIG_DEBUG_SPI_FLASH
 printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }"
      " chunk_len = %zu\n",
      buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
+#endif
 
 ret = spi_flash_cmd(flash->spi, CMD_S25FLXX_WREN, NULL, 0);
 if (ret < 0) {
diff --git a/src/drivers/spi/stmicro.c b/src/drivers/spi/stmicro.c
index 9322c06..ccdfa00 100644
--- a/src/drivers/spi/stmicro.c
+++ b/src/drivers/spi/stmicro.c
< at >< at > -163,9 +163,11 < at >< at > static int stmicro_write(struct spi_flash *flash,
 cmd[2] = page_addr;
 cmd[3] = byte_addr;
 
+#if CONFIG_DEBUG_SPI_FLASH
 printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }"
      " chunk_len = %zu\n",
      buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
+#endif
 
 ret = spi_flash_cmd(flash->spi, CMD_M25PXX_WREN, NULL, 0);
 if (ret < 0) {
diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c
index 7b6d105..01644b0 100644
--- a/src/drivers/spi/winbond.c
+++ b/src/drivers/spi/winbond.c
< at >< at > -130,9 +130,11 < at >< at > static int winbond_write(struct spi_flash *flash,
 cmd[1] = (offset >> 16) & 0xff;
 cmd[2] = (offset >> 8) & 0xff;
 cmd[3] = offset & 0xff;
+#if CONFIG_DEBUG_SPI_FLASH
 printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }"
         " chunk_len = %zu\n", buf + actual,
 cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
+#endif
 
 ret = spi_flash_cmd(flash->spi, CMD_W25_WREN, NULL, 0);
 if (ret < 0) {

Patch set updated for coreboot: 2af8cea Fix printk typesin SPI flash drivers

Stefan Reinauer — 2012-05-24T21:31:21

Stefan Reinauer (stefan.reinauer< at >coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1041

-gerrit

commit 2af8cea9fd41eecf0bbddf2579d7ea9dada5dad3
Author: Stefan Reinauer <reinauer< at >chromium.org>
Date:   Mon May 14 13:52:32 2012 -0700

    Fix printk types in SPI flash drivers
    
    - use %zu instead of %zd for size_t (%zd is for ssize_t)
    - use %x instead of %lx for u32
    - break some long lines to avoid commit hook trouble
    
    Change-Id: Idfad716523dbcd2a595d26317240e972b5253e8b
    Signed-off-by: Stefan Reinauer <reinauer< at >google.com>
---
 src/drivers/spi/eon.c      |    2 +-
 src/drivers/spi/macronix.c |    6 ++++--
 src/drivers/spi/spansion.c |    3 ++-
 src/drivers/spi/sst.c      |    2 +-
 src/drivers/spi/stmicro.c  |    3 ++-
 src/drivers/spi/winbond.c  |    6 +++---
 6 files changed, 13 insertions(+), 9 deletions(-)

diff --git a/src/drivers/spi/eon.c b/src/drivers/spi/eon.c
index 4056953..b7c0630 100644
--- a/src/drivers/spi/eon.c
+++ b/src/drivers/spi/eon.c
< at >< at > -86,7 +86,7 < at >< at > static int eon_write(struct spi_flash *flash,
 cmd[3] = byte_addr;
 
 printk(BIOS_SPEW,
-    "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zd\n",
+    "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",
      buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
 
 ret = spi_flash_cmd(flash->spi, CMD_EN25Q128_WREN, NULL, 0);
diff --git a/src/drivers/spi/macronix.c b/src/drivers/spi/macronix.c
index 130e746..84e79ef 100644
--- a/src/drivers/spi/macronix.c
+++ b/src/drivers/spi/macronix.c
< at >< at > -141,7 +141,8 < at >< at > static int macronix_write(struct spi_flash *flash,
 cmd[2] = (offset >> 8) & 0xff;
 cmd[3] = offset & 0xff;
 
-printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zd\n",
+printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }"
+     " chunk_len = %zu\n",
      buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
 
 ret = spi_flash_cmd(flash->spi, CMD_MX25XX_WREN, NULL, 0);
< at >< at > -165,7 +166,8 < at >< at > static int macronix_write(struct spi_flash *flash,
 byte_addr = 0;
 }
 
-printk(BIOS_INFO, "SF: Macronix: Successfully programmed %zu bytes < at > 0x%lx\n",
+printk(BIOS_INFO, "SF: Macronix: Successfully programmed %zu bytes < at >"
+      " 0x%x\n",
       len, offset - len);
 
 spi_release_bus(flash->spi);
diff --git a/src/drivers/spi/spansion.c b/src/drivers/spi/spansion.c
index a4f370a..5479cae 100644
--- a/src/drivers/spi/spansion.c
+++ b/src/drivers/spi/spansion.c
< at >< at > -162,7 +162,8 < at >< at > static int spansion_write(struct spi_flash *flash,
 cmd[2] = page_addr;
 cmd[3] = byte_addr;
 
-printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zd\n",
+printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }"
+     " chunk_len = %zu\n",
      buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
 
 ret = spi_flash_cmd(flash->spi, CMD_S25FLXX_WREN, NULL, 0);
diff --git a/src/drivers/spi/sst.c b/src/drivers/spi/sst.c
index c5bec12..3ca5563 100644
--- a/src/drivers/spi/sst.c
+++ b/src/drivers/spi/sst.c
< at >< at > -194,7 +194,7 < at >< at > sst_write(struct spi_flash *flash, u32 offset, size_t len, const void *buf)
 ret = sst_byte_write(flash, offset, buf + actual);
 
 done:
-printk(BIOS_INFO, "SF: SST: program %s %zu bytes < at > 0x%lx\n",
+printk(BIOS_INFO, "SF: SST: program %s %zu bytes < at > 0x%x\n",
       ret ? "failure" : "success", len, offset - actual);
 
 spi_release_bus(flash->spi);
diff --git a/src/drivers/spi/stmicro.c b/src/drivers/spi/stmicro.c
index 8cbdad5..9322c06 100644
--- a/src/drivers/spi/stmicro.c
+++ b/src/drivers/spi/stmicro.c
< at >< at > -163,7 +163,8 < at >< at > static int stmicro_write(struct spi_flash *flash,
 cmd[2] = page_addr;
 cmd[3] = byte_addr;
 
-printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zd\n",
+printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }"
+     " chunk_len = %zu\n",
      buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
 
 ret = spi_flash_cmd(flash->spi, CMD_M25PXX_WREN, NULL, 0);
diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c
index 65818d5..7b6d105 100644
--- a/src/drivers/spi/winbond.c
+++ b/src/drivers/spi/winbond.c
< at >< at > -130,8 +130,8 < at >< at > static int winbond_write(struct spi_flash *flash,
 cmd[1] = (offset >> 16) & 0xff;
 cmd[2] = (offset >> 8) & 0xff;
 cmd[3] = offset & 0xff;
-printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %ld\n",
-buf + actual,
+printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }"
+        " chunk_len = %zu\n", buf + actual,
 cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
 
 ret = spi_flash_cmd(flash->spi, CMD_W25_WREN, NULL, 0);
< at >< at > -155,7 +155,7 < at >< at > static int winbond_write(struct spi_flash *flash,
 byte_addr = 0;
 }
 
-printk(BIOS_INFO, "SF: Winbond: Successfully programmed %zu bytes < at > 0x%lx\n",
+printk(BIOS_INFO, "SF: Winbond: Successfully programmed %zu bytes < at > 0x%x\n",
 len, offset - len);
 ret = 0;

New patch to review for coreboot: 88a1ccf nvramtool: useC99 PRIx64 / PRId64 for uint64_t variables

Stefan Reinauer — 2012-05-24T20:40:04

Stefan Reinauer (stefan.reinauer< at >coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1053

-gerrit

commit 88a1ccfa55bad83429c09acdb3cb6e2aa84cb03e
Author: Stefan Reinauer <reinauer< at >chromium.org>
Date:   Thu May 24 13:36:30 2012 -0700

    nvramtool: use C99 PRIx64 / PRId64 for uint64_t variables
    
    In printf/printk, using %lld or %ld for uint64_t will warn on either
    64bit or 32bit machines.  However, C99 defines PRIx64 / PRId64 to
    provide the right modifiers for printing uint64_t variables. Use them
    instead.
    
    Change-Id: I68df5d069a1e99d1a75885173ddfd7815197afea
    Signed-off-by: Stefan Reinauer <reinauer< at >google.com>
---
 util/nvramtool/lbtable.c |   10 ++++++----
 1 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/util/nvramtool/lbtable.c b/util/nvramtool/lbtable.c
index 71c3244..83597e4 100644
--- a/util/nvramtool/lbtable.c
+++ b/util/nvramtool/lbtable.c
< at >< at > -29,6 +29,8 < at >< at >
  *  51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
 \*****************************************************************************/
 
+#include <stdint.h>
+#include <inttypes.h>
 #include <arpa/inet.h>
 #include <string.h>
 #include <sys/mman.h>
< at >< at > -655,10 +657,10 < at >< at > static void memory_print_fn(const struct lb_record *rec)
 start = unpack_lb64(ranges[i].start);
 end = start + size - 1;
 printf("%s memory:\n"
-       "    from physical addresses 0x%016llx to 0x%016llx\n"
-       "    size is 0x%016llx bytes (%lld in decimal)\n",
-       mem_type, start, end, size,
-       (unsigned long long)size);
+       "    from physical addresses 0x%016" PRIx64
+       " to 0x%016" PRIx64 "\n    size is 0x%016" PRIx64
+       " bytes (%" PRId64 " in decimal)\n",
+       mem_type, start, end, size, size);
 
 if (++i >= entries)
 break;

Patch set updated for coreboot: c960958 Fix size_t forcertain versions of GCC

Stefan Reinauer — 2012-05-24T20:30:08

Stefan Reinauer (stefan.reinauer< at >coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1040

-gerrit

commit c960958a82b43dc4401d8f300e0d90daefc9341f
Author: Stefan Reinauer <reinauer< at >chromium.org>
Date:   Mon May 14 13:21:08 2012 -0700

    Fix size_t for certain versions of GCC
    
    When compiling coreboot with the latest ChromeOS toolchain, GCC
    complains that some printk calls use %zu in connection with size_t
    types since it resolves the typedefs to long unsigned int.
    
    The problem is solved by using the GCC built-in __SIZE_TYPE__ if it
    exists and define __SIZE_TYPE__ to long unsigned int otherwise.
    
    Change-Id: I449c3d385b5633a05e57204704e981de6e017b86
    Signed-off-by: Stefan Reinauer <reinauer< at >google.com>
---
 src/arch/x86/include/stddef.h |    5 ++++-
 1 files changed, 4 insertions(+), 1 deletions(-)

diff --git a/src/arch/x86/include/stddef.h b/src/arch/x86/include/stddef.h
index e4fc019..a6c3fc6 100644
--- a/src/arch/x86/include/stddef.h
+++ b/src/arch/x86/include/stddef.h
< at >< at > -2,7 +2,10 < at >< at >
 #define I386_STDDEF_H
 
 typedef long ptrdiff_t;
-typedef unsigned long size_t;
+#ifndef __SIZE_TYPE__
+#define __SIZE_TYPE__ unsigned long
+#endif
+typedef __SIZE_TYPE__ size_t;
 typedef long ssize_t;
 
 typedef int wchar_t;

Patch merged into coreboot/master: b972fec Add EM100mode to Intel Firmware Descriptor tool

2012-05-24T20:22:25

the following patch was just integrated into master:
commit b972fecf8b37384fa75de7e5d1e33827fce8b675
Author: Stefan Reinauer <reinauer< at >chromium.org>
Date:   Fri May 11 15:53:43 2012 -0700

    Add EM100 mode to Intel Firmware Descriptor tool
    
    To avoid having two copies for every firmware descriptor (one for
    EM100 use and one for real SPI flash use), add an EM100 mode to
    ifdtool that allows to "dumb down" a fast image to the settings
    required for the EM100 to work.
    
    Change-Id: I0ed989f0a49316bc63d8627cb5d4bd988ae7a103
    Signed-off-by: Stefan Reinauer <reinauer< at >google.com>

Build-Tested: build bot (Jenkins) at Thu May 24 10:41:49 2012, giving +1
See http://review.coreboot.org/1039 for details.

-gerrit

Patch merged into coreboot/master: 813532b chromeos: Fixcompilation of coreboot-utils package

2012-05-24T20:22:15

the following patch was just integrated into master:
commit 813532b8352bd643fb507c472d518fafebf1edfe
Author: Stefan Reinauer <reinauer< at >chromium.org>
Date:   Fri May 11 12:58:11 2012 -0700

    chromeos: Fix compilation of coreboot-utils package
    
    The ChromeOS build system provides a set of CXXFLAGS, however those do
    not contain -DCOMPACT. This breaks the compilation of cbfstool in
    coreboot-utils.
    
    This fix overrides CXXFLAGS so that coreboot-utils compiles again.
    
    Change-Id: If9495bdd815fe2cdaeba5386afa953558742467b
    Signed-off-by: Stefan Reinauer <reinauer< at >google.com>

Build-Tested: build bot (Jenkins) at Thu May 24 10:27:35 2012, giving +1
See http://review.coreboot.org/1038 for details.

-gerrit

make und Git: fatal: No names found,cannot describe anything.

Paul Menzel — 2012-05-24T20:09:18

Dear coreboot folks,


I cloned the source tree,

        $ git describe
        4.0-2410-g92ff934

did `make crossgcc` and run `make menuconfig`.

I chose ASRock E350M1 and SeaBIOS master.

At the end I got the following.

        $ make
        […]
            Checking out SeaBIOS revision origin/master
        Switched to branch 'master'
        Deleted branch coreboot (was 347f294).
        Branch coreboot set up to track remote branch master from origin.
        Switched to a new branch 'coreboot'
            CONFIG     SeaBIOS origin/master
          Working around non-functional -combine
          Build default config
        # 
        # configuration written to /home/joe/coreboot/build/seabios/.config
        #
            MAKE       SeaBIOS origin/master
          Working around non-functional -combine
          Build Kconfig config file
        /home/joe/coreboot/build/seabios/.config:89:warning: override: reassigning to symbol COREBOOT
        /home/joe/coreboot/build/seabios/.config:90:warning: override: reassigning to symbol DEBUG_SERIAL
        /home/joe/coreboot/build/seabios/.config:95:warning: override: reassigning to symbol VGAHOOKS
        #
        # configuration written to /home/joe/coreboot/build/seabios/.config
        #
          Compiling whole program /home/joe/coreboot/build/seabios/out/ccode32flat.o
          Compiling whole program /home/joe/coreboot/build/seabios/out/code32seg.o
          Compiling whole program /home/joe/coreboot/build/seabios/out/ccode16.o
          Compiling to assembler /home/joe/coreboot/build/seabios/out/asm-offsets.s
          Generating offset file /home/joe/coreboot/build/seabios/out/asm-offsets.h
          Compiling (16bit) /home/joe/coreboot/build/seabios/out/romlayout.o
          Building ld scripts
        fatal: No names found, cannot describe anything.
      * Version: -20120524_211503-asrock-e350m1
        Fixed space: 0xe05b-0x10000  total: 8101  slack: 10  Percent slack: 0.1%
        16bit size:           38848
        32bit segmented size: 2307
        32bit flat size:      17309
        32bit flat init size: 40928
        Lowmem size:          2144
          Linking /home/joe/coreboot/build/seabios/out/rom16.o
          Stripping /home/joe/coreboot/build/seabios/out/rom16.strip.o
          Linking /home/joe/coreboot/build/seabios/out/rom32seg.o
          Stripping /home/joe/coreboot/build/seabios/out/rom32seg.strip.o
          Linking /home/joe/coreboot/build/seabios/out/rom.o
          Prepping /home/joe/coreboot/build/seabios/out/bios.bin
        […]

I guess it has to do with cloned SeaBIOS git tree.


Thanks,

Paul

Patch merged into coreboot/master: cb5e566 Converted theFRAMEBUFFER_VESA_MODE to a choice.

2012-05-24T19:54:10

the following patch was just integrated into master:
commit cb5e566eb996dac15b34d56dc4982d8c094260ac
Author: Steve Goodrich <steve.goodrich< at >se-eng.com>
Date:   Fri May 18 11:18:47 2012 -0600

    Converted the FRAMEBUFFER_VESA_MODE to a choice.
    
    Being a diligent soul, I changed the "enter a numeric value for the
    mode you want" option to a choice of common modes.  New modes can be
    added quite easily.
    
    Change-Id: I8cf4572c2d36ced6549541ec173c0c02d8eaca4a
    Signed-off-by: Steve Goodrich <steve.goodrich< at >se-eng.com>


See http://review.coreboot.org/1036 for details.

-gerrit

Patch merged into coreboot/master: b071aa2 abuild:Disable abuild-level parallelism for now

2012-05-24T16:09:19

the following patch was just integrated into master:
commit b071aa230fe252af638aed7d0bfc979cb914b93e
Author: Patrick Georgi <patrick< at >georgi-clan.de>
Date:   Mon May 21 20:10:04 2012 +0200

    abuild: Disable abuild-level parallelism for now
    
    It still failed because make touches files it isn't
    supposed to touch.
    
    Change-Id: I5a6ceaa9d5da212c1e34b121cf39fa9d27964747
    Signed-off-by: Patrick Georgi <patrick< at >georgi-clan.de>

Reviewed-By: Patrick Georgi <patrick< at >georgi-clan.de> at Thu May 24 18:09:17 2012, giving +2
See http://review.coreboot.org/1037 for details.

-gerrit

Patch merged into coreboot/master: 6cf94df cbtypes.h:Unify cbtypes.h used in AMD board's code

2012-05-24T15:38:44

the following patch was just integrated into master:
commit 6cf94dfec7b4ac5cdb3716ae45726a5fa8ea0235
Author: Vikram Narayanan <vikram186< at >gmail.com>
Date:   Sat Apr 21 23:47:56 2012 +0530

    cbtypes.h: Unify cbtypes.h used in AMD board's code
    
    Remove all the repeated sections of code in cbtypes.h and place it
    in a common location. Add include dir in vendor code's Makefile.
    
    Change-Id: Ida92c2a7a88e9520b84b0dcbbf37cd5c9f63f798
    Signed-off-by: Vikram Narayanan <vikram186< at >gmail.com>

Build-Tested: build bot (Jenkins) at Thu Apr 26 18:54:23 2012, giving +1
Reviewed-By: Marc Jones <marcj303< at >gmail.com> at Thu May 24 17:38:41 2012, giving +2
See http://review.coreboot.org/912 for details.

-gerrit

Patch set updated for coreboot: d75af2f Sandybridge: FixMRC cache calculation

Patrick Georgi — 2012-05-24T07:46:38

Patrick Georgi (patrick< at >georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1046

-gerrit

commit d75af2fac06191f07b91fdad5f61fa936deebb2a
Author: Stefan Reinauer <reinauer< at >chromium.org>
Date:   Wed May 23 11:21:10 2012 -0700

    Sandybridge: Fix MRC cache calculation
    
    The MRC region is described by Kconfig variables, no further math
    or parsing is required at this point.
    
    Change-Id: I290d8788b69ef007e9ea2317ce55aefa2d791883
    Signed-off-by: Stefan Reinauer <reinauer< at >google.com>
---
 src/northbridge/intel/sandybridge/mrccache.c |    6 ++----
 1 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c
index 5c4c382..aad2b91 100644
--- a/src/northbridge/intel/sandybridge/mrccache.c
+++ b/src/northbridge/intel/sandybridge/mrccache.c
< at >< at > -65,8 +65,8 < at >< at > u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr)
 {
 u8 *mrc_region;
 u32 region_size;
-u32 *data;
 #ifdef USE_FDT_FMAP_FOR_MRC_CACHE
+u32 *data;
 const struct fdt_header *fdt_header;
 const struct fdt_property *fdtp;
 int offset, len;
< at >< at > -114,10 +114,8 < at >< at > u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr)
 region_size = fdt32_to_cpu(data[1]);
 mrc_region = (u8*)((unsigned long)flashrom_base + fdt32_to_cpu(data[0]));
 #else
-data = (u32 *)((void *)(CONFIG_MRC_CACHE_BASE + CONFIG_MRC_CACHE_LOCATION + 12));
-
 region_size = CONFIG_MRC_CACHE_SIZE;
-mrc_region = (u8*)(CONFIG_MRC_CACHE_BASE + be32_to_cpu(data[0]));
+mrc_region = (u8*)(CONFIG_MRC_CACHE_BASE + CONFIG_MRC_CACHE_LOCATION);
 #endif
 
 *mrc_region_ptr = (struct mrc_data_container *)mrc_region;

Patch set updated for coreboot: d03766d Drop configvariable CPU_MODEL_INDEX

Patrick Georgi — 2012-05-24T07:46:37

Patrick Georgi (patrick< at >georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1047

-gerrit

commit d03766d8bac5f99128d9c8a0adbc2ef7cb5e71ba
Author: Stefan Reinauer <reinauer< at >chromium.org>
Date:   Fri May 11 16:30:54 2012 -0700

    Drop config variable CPU_MODEL_INDEX
    
    It's only used in the ACPI generator for Sandybridge/Ivybridge CPUs
    and the code can easily be changed to not rely on any Kconfig magic.
    
    Change-Id: Ie2f92edfe8908f7eb2fda3088f77ad22f491ddcf
    Signed-off-by: Stefan Reinauer <reinauer< at >google.com>
---
 src/cpu/intel/model_206ax/Kconfig |    8 --------
 src/cpu/intel/model_206ax/acpi.c  |   11 ++---------
 2 files changed, 2 insertions(+), 17 deletions(-)

diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig
index c11f21a..d2d4c73 100644
--- a/src/cpu/intel/model_206ax/Kconfig
+++ b/src/cpu/intel/model_206ax/Kconfig
< at >< at > -36,18 +36,10 < at >< at > if CPU_INTEL_MODEL_206AX
    config CPU_MODEL_NAME
 string
 default "Intel SandyBridge CPU"
-
-   config CPU_MODEL_INDEX
-hex
-default 0x2a
 endif
 
 if CPU_INTEL_MODEL_306AX
    config CPU_MODEL_NAME
 string
 default "Intel IvyBridge CPU"
-
-   config CPU_MODEL_INDEX
-hex
-default 0x3a
 endif
diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c
index 1a8ceb7..6153174 100644
--- a/src/cpu/intel/model_206ax/acpi.c
+++ b/src/cpu/intel/model_206ax/acpi.c
< at >< at > -44,15 +44,8 < at >< at > static int get_cores_per_package(void)
 if (c.x86 != 6)
 return 1;
 
-switch (c.x86_model) {
-case CONFIG_CPU_MODEL_INDEX:
-result = cpuid_ext(0xb, 1);
-cores = result.ebx & 0xff;
-break;
-default:
-cores = (cpuid_ebx(1) >> 16) & 0xff;
-break;
-}
+result = cpuid_ext(0xb, 1);
+cores = result.ebx & 0xff;
 
 return cores;
 }

Patch set updated for coreboot: a3e04c2 Fix compilationwith CONFIG_DEBUG_SPI_FLASH enabled

Patrick Georgi — 2012-05-24T07:46:37

Patrick Georgi (patrick< at >georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1044

-gerrit

commit a3e04c29df4e7a0c8073eee8ca7f3cdc75cd5839
Author: Stefan Reinauer <reinauer< at >chromium.org>
Date:   Tue May 22 15:24:51 2012 -0700

    Fix compilation with CONFIG_DEBUG_SPI_FLASH enabled
    
    Right now coreboot compilation fails when SPI flash debugging is
    enabled. Fix it by using the right set of memory functions.
    
    Change-Id: I5e372c4a5df53b4d46aaed9e251e5205ff68cb5b
    Signed-off-by: Stefan Reinauer <reinauer< at >google.com>
---
 src/drivers/spi/spi_flash.c         |    1 -
 src/southbridge/intel/bd82x6x/spi.c |   12 ++++++------
 2 files changed, 6 insertions(+), 7 deletions(-)

diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c
index 2c0f702..0b859f3 100644
--- a/src/drivers/spi/spi_flash.c
+++ b/src/drivers/spi/spi_flash.c
< at >< at > -264,7 +264,6 < at >< at > struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
 
 #if CONFIG_DEBUG_SPI_FLASH
 printk(BIOS_SPEW, "SF: Got idcodes\n");
-print_buffer(0, idcode, 1, sizeof(idcode), 0);
 #endif
 
 /* count the number of continuation bytes */
diff --git a/src/southbridge/intel/bd82x6x/spi.c b/src/southbridge/intel/bd82x6x/spi.c
index 2508a96..95fbfb9 100644
--- a/src/southbridge/intel/bd82x6x/spi.c
+++ b/src/southbridge/intel/bd82x6x/spi.c
< at >< at > -162,7 +162,7 < at >< at > enum {
 
 static u8 readb_(const void *addr)
 {
-u8 v = readb(addr);
+u8 v = read8((unsigned long)addr);
 printk(BIOS_DEBUG, "read %2.2x from %4.4x\n",
        v, ((unsigned) addr & 0xffff) - 0xf020);
 return v;
< at >< at > -170,7 +170,7 < at >< at > static u8 readb_(const void *addr)
 
 static u16 readw_(const void *addr)
 {
-u16 v = readw(addr);
+u16 v = read16((unsigned long)addr);
 printk(BIOS_DEBUG, "read %4.4x from %4.4x\n",
        v, ((unsigned) addr & 0xffff) - 0xf020);
 return v;
< at >< at > -178,7 +178,7 < at >< at > static u16 readw_(const void *addr)
 
 static u32 readl_(const void *addr)
 {
-u32 v = readl(addr);
+u32 v = read32((unsigned long)addr);
 printk(BIOS_DEBUG, "read %8.8x from %4.4x\n",
        v, ((unsigned) addr & 0xffff) - 0xf020);
 return v;
< at >< at > -186,21 +186,21 < at >< at > static u32 readl_(const void *addr)
 
 static void writeb_(u8 b, const void *addr)
 {
-writeb(b, addr);
+write8((unsigned long)addr, b);
 printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n",
        b, ((unsigned) addr & 0xffff) - 0xf020);
 }
 
 static void writew_(u16 b, const void *addr)
 {
-writew(b, addr);
+write16((unsigned long)addr, b);
 printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n",
        b, ((unsigned) addr & 0xffff) - 0xf020);
 }
 
 static void writel_(u32 b, const void *addr)
 {
-writel(b, addr);
+write32((unsigned long)addr, b);
 printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n",
        b, ((unsigned) addr & 0xffff) - 0xf020);
 }

Patch set updated for coreboot: fe81ee8 Reduce defaultverbosity of SPI flash drivers

Patrick Georgi — 2012-05-24T07:46:36

Patrick Georgi (patrick< at >georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1045

-gerrit

commit fe81ee8c93b8f72d4f403e0e3a8a53da6cc7032c
Author: Stefan Reinauer <reinauer< at >chromium.org>
Date:   Wed May 23 11:03:29 2012 -0700

    Reduce default verbosity of SPI flash drivers
    
    Only print PP: lines if CONFIG_DEBUG_SPI_FLASH is enabled.
    
    Change-Id: If25e916ecb585f37c90d42980e933a6cd1a3d956
    Signed-off-by: Stefan Reinauer <reinauer< at >google.com>
---
 src/drivers/spi/eon.c      |    2 ++
 src/drivers/spi/macronix.c |    2 ++
 src/drivers/spi/spansion.c |    2 ++
 src/drivers/spi/stmicro.c  |    2 ++
 src/drivers/spi/winbond.c  |    2 ++
 5 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/src/drivers/spi/eon.c b/src/drivers/spi/eon.c
index b7c0630..7d9bc44 100644
--- a/src/drivers/spi/eon.c
+++ b/src/drivers/spi/eon.c
< at >< at > -85,9 +85,11 < at >< at > static int eon_write(struct spi_flash *flash,
 cmd[2] = page_addr;
 cmd[3] = byte_addr;
 
+#if CONFIG_DEBUG_SPI_FLASH
 printk(BIOS_SPEW,
     "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",
      buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
+#endif
 
 ret = spi_flash_cmd(flash->spi, CMD_EN25Q128_WREN, NULL, 0);
 if (ret < 0) {
diff --git a/src/drivers/spi/macronix.c b/src/drivers/spi/macronix.c
index 84e79ef..f74eb4f 100644
--- a/src/drivers/spi/macronix.c
+++ b/src/drivers/spi/macronix.c
< at >< at > -141,9 +141,11 < at >< at > static int macronix_write(struct spi_flash *flash,
 cmd[2] = (offset >> 8) & 0xff;
 cmd[3] = offset & 0xff;
 
+#if CONFIG_DEBUG_SPI_FLASH
 printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }"
      " chunk_len = %zu\n",
      buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
+#endif
 
 ret = spi_flash_cmd(flash->spi, CMD_MX25XX_WREN, NULL, 0);
 if (ret < 0) {
diff --git a/src/drivers/spi/spansion.c b/src/drivers/spi/spansion.c
index 5479cae..511091b 100644
--- a/src/drivers/spi/spansion.c
+++ b/src/drivers/spi/spansion.c
< at >< at > -162,9 +162,11 < at >< at > static int spansion_write(struct spi_flash *flash,
 cmd[2] = page_addr;
 cmd[3] = byte_addr;
 
+#if CONFIG_DEBUG_SPI_FLASH
 printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }"
      " chunk_len = %zu\n",
      buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
+#endif
 
 ret = spi_flash_cmd(flash->spi, CMD_S25FLXX_WREN, NULL, 0);
 if (ret < 0) {
diff --git a/src/drivers/spi/stmicro.c b/src/drivers/spi/stmicro.c
index 9322c06..ccdfa00 100644
--- a/src/drivers/spi/stmicro.c
+++ b/src/drivers/spi/stmicro.c
< at >< at > -163,9 +163,11 < at >< at > static int stmicro_write(struct spi_flash *flash,
 cmd[2] = page_addr;
 cmd[3] = byte_addr;
 
+#if CONFIG_DEBUG_SPI_FLASH
 printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }"
      " chunk_len = %zu\n",
      buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
+#endif
 
 ret = spi_flash_cmd(flash->spi, CMD_M25PXX_WREN, NULL, 0);
 if (ret < 0) {
diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c
index 7b6d105..01644b0 100644
--- a/src/drivers/spi/winbond.c
+++ b/src/drivers/spi/winbond.c
< at >< at > -130,9 +130,11 < at >< at > static int winbond_write(struct spi_flash *flash,
 cmd[1] = (offset >> 16) & 0xff;
 cmd[2] = (offset >> 8) & 0xff;
 cmd[3] = offset & 0xff;
+#if CONFIG_DEBUG_SPI_FLASH
 printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }"
         " chunk_len = %zu\n", buf + actual,
 cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
+#endif
 
 ret = spi_flash_cmd(flash->spi, CMD_W25_WREN, NULL, 0);
 if (ret < 0) {

Patch set updated for coreboot: 5e0503e Move subsystemIDs to devicetree.cb

Patrick Georgi — 2012-05-24T07:46:35

Patrick Georgi (patrick< at >georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1042

-gerrit

commit 5e0503e0511dd37377917d874d2afd7ae41efdea
Author: Stefan Reinauer <reinauer< at >chromium.org>
Date:   Tue May 15 12:36:57 2012 -0700

    Move subsystem IDs to devicetree.cb
    
    A while back coreboot was changed to read the subsystem IDs from
    devicetree.cb to allow each onboard PCI device to have its own
    subsystem id. When we originally branched, this was not the case,
    and the sandybridge/ivybridge mainboards have not been updated yet.
    Also, drop the subsystem ID from Emerald Lake 2, since it's not a
    Google device.
    
    Change-Id: Ie96fd67cd2ff65ad6ff725914e3bad843e78712e
    Signed-off-by: Stefan Reinauer <reinauer< at >google.com>
---
 src/mainboard/intel/emeraldlake2/Kconfig   |    8 --------
 src/mainboard/samsung/lumpy/Kconfig        |    8 --------
 src/mainboard/samsung/lumpy/devicetree.cb  |    1 +
 src/mainboard/samsung/stumpy/Kconfig       |    8 --------
 src/mainboard/samsung/stumpy/devicetree.cb |    1 +
 5 files changed, 2 insertions(+), 24 deletions(-)

diff --git a/src/mainboard/intel/emeraldlake2/Kconfig b/src/mainboard/intel/emeraldlake2/Kconfig
index 9e4f347..873d273 100644
--- a/src/mainboard/intel/emeraldlake2/Kconfig
+++ b/src/mainboard/intel/emeraldlake2/Kconfig
< at >< at > -43,12 +43,4 < at >< at > config VGA_BIOS_FILE
 string
 default "pci8086,0166.rom"
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-hex
-default 0x1ae0
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-hex
-default 0xc000
-
 endif # BOARD_INTEL_EMERALDLAKE2
diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig
index 200edac..0835012 100644
--- a/src/mainboard/samsung/lumpy/Kconfig
+++ b/src/mainboard/samsung/lumpy/Kconfig
< at >< at > -44,14 +44,6 < at >< at > config VGA_BIOS_FILE
 string
 default "pci8086,0106.rom"
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-hex
-default 0x1ae0
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-hex
-default 0xc000
-
 config MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 bool
 default n
diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb
index 36af1ca..3e93df4 100644
--- a/src/mainboard/samsung/lumpy/devicetree.cb
+++ b/src/mainboard/samsung/lumpy/devicetree.cb
< at >< at > -33,6 +33,7 < at >< at > chip northbridge/intel/sandybridge
 end
 
 device pci_domain 0 on
+subsystemid 0x1ae0 0xc000 inherit
 device pci 00.0 on end # host bridge
 device pci 02.0 on end # vga controller
 
diff --git a/src/mainboard/samsung/stumpy/Kconfig b/src/mainboard/samsung/stumpy/Kconfig
index dda3002..18094cf 100644
--- a/src/mainboard/samsung/stumpy/Kconfig
+++ b/src/mainboard/samsung/stumpy/Kconfig
< at >< at > -43,14 +43,6 < at >< at > config VGA_BIOS_FILE
 string
 default "pci8086,0106.rom"
 
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-hex
-default 0x1ae0
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-hex
-default 0xc000
-
 config MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 bool
 default n
diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb
index f10b283..b59dcb2 100644
--- a/src/mainboard/samsung/stumpy/devicetree.cb
+++ b/src/mainboard/samsung/stumpy/devicetree.cb
< at >< at > -28,6 +28,7 < at >< at > chip northbridge/intel/sandybridge
 end
 
 device pci_domain 0 on
+subsystemid 0x1ae0 0xc000 inherit
 device pci 00.0 on end # host bridge
 device pci 02.0 on end # vga controller

Patch set updated for coreboot: 01b7d07 Implement %zu /%zd in printk

Patrick Georgi — 2012-05-24T07:46:34

Patrick Georgi (patrick< at >georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1043

-gerrit

commit 01b7d0786bc78115af3fd03727a2c48a3243468e
Author: Stefan Reinauer <reinauer< at >chromium.org>
Date:   Tue May 15 13:28:07 2012 -0700

    Implement %zu / %zd in printk
    
    The SPI drivers from u-boot make heavy use of %zu/%zd (size_t/ssize_t).
    Implement this in our printk implementation so we get useful output.
    
    Change-Id: I91798ff4f28b9c3cd4db204c7ec503596d247dcd
    Signed-off-by: Stefan Reinauer <reinauer< at >google.com>
---
 src/console/vtxprintf.c |    5 +++--
 1 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/console/vtxprintf.c b/src/console/vtxprintf.c
index a370e5f..28c5a60 100644
--- a/src/console/vtxprintf.c
+++ b/src/console/vtxprintf.c
< at >< at > -170,7 +170,7 < at >< at > repeat:
 
 /* get the conversion qualifier */
 qualifier = -1;
-if (*fmt == 'h' || *fmt == 'l' || *fmt == 'L') {
+if (*fmt == 'h' || *fmt == 'l' || *fmt == 'L' || *fmt == 'z') {
 qualifier = *fmt;
 ++fmt;
 if (*fmt == 'l') {
< at >< at > -218,7 +218,6 < at >< at > repeat:
 field_width, precision, flags);
 continue;
 
-
 case 'n':
 if (qualifier == 'L') {
 long long *ip = va_arg(args, long long *);
< at >< at > -265,6 +264,8 < at >< at > repeat:
 num = va_arg(args, unsigned long long);
 } else if (qualifier == 'l') {
 num = va_arg(args, unsigned long);
+} else if (qualifier == 'z') {
+num = va_arg(args, size_t);
 } else if (qualifier == 'h') {
 num = (unsigned short) va_arg(args, int);
 if (flags & SIGN)

Patch set updated for coreboot: 595f2fc Fix size_t forcertain versions of GCC

Patrick Georgi — 2012-05-24T07:46:33

Patrick Georgi (patrick< at >georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1040

-gerrit

commit 595f2fcfb7492fa40b1a63acb0fb882d1fec0d73
Author: Stefan Reinauer <reinauer< at >chromium.org>
Date:   Mon May 14 13:21:08 2012 -0700

    Fix size_t for certain versions of GCC
    
    When compiling coreboot with the latest ChromeOS toolchain, GCC
    complains that some printk calls use %zu in connection with size_t
    types since it resolves the typedefs to long unsigned int.
    
    The problem is solved by using the GCC built-in __SIZE_TYPE__ if it
    exists and define __SIZE_TYPE__ to long unsigned int otherwise.
    
    Change-Id: I449c3d385b5633a05e57204704e981de6e017b86
    Signed-off-by: Stefan Reinauer <reinauer< at >google.com>
---
 src/arch/x86/include/stddef.h |    5 ++++-
 1 files changed, 4 insertions(+), 1 deletions(-)

diff --git a/src/arch/x86/include/stddef.h b/src/arch/x86/include/stddef.h
index e4fc019..c737be1 100644
--- a/src/arch/x86/include/stddef.h
+++ b/src/arch/x86/include/stddef.h
< at >< at > -2,7 +2,10 < at >< at >
 #define I386_STDDEF_H
 
 typedef long ptrdiff_t;
-typedef unsigned long size_t;
+#ifndef __SIZE_TYPE__
+#define __SIZE_TYPE__ long unsigned int
+#endif
+typedef __SIZE_TYPE__ size_t;
 typedef long ssize_t;
 
 typedef int wchar_t;