gmane.linux.bios

Re: DDR fails on F2A85-M

David Hubbard — 2013-05-22T17:40:47

 |V1.1.0.7
 |V1.1.0.1

Thanks for that. For the bios version I have (5103) it's:

007ac760  41 47 45 53 41 00 00 00  56 31 2e 31 2e 30 2e 37
 |AGESA...V1.1.0.7|

David

Re: DDR fails on F2A85-M

Ward Vandewege — 2013-05-22T15:49:07

The above is for proprietary bios revision 5202.

Bizarrely, the most recent proprietary bios revision for this board (6102)
appears to use an older Agesa version, v1.1.0.1:

213221:0079e760  00 00 00 00 30 30 30 30  41 47 45 53 41 00 00 00
|....0000AGESA...|
213222-0079e770  56 31 2e 31 2e 30 2e 31  20 20 20 20 00 00 00 00  |V1.1.0.1
....|

Thanks,
Ward.

Re: DDR fails on F2A85-M

Ward Vandewege — 2013-05-22T15:18:46

Hi Paul and David,

We got an F2A85-M today. I haven't tried to boot coreboot yet but I can
answer the question below:

On Sat, May 11, 2013 at 10:20:31PM +0200, Paul Menzel wrote:

bios_extract is not able to do anything with the image:

$ ../bios_extract/bios_extract f2a85m-proprietary.rom 
Using file "f2a85m-proprietary.rom" (8192kB)
Error: Unable to detect BIOS Image type.

However, hd/strings suggest that the AGESA version is v1.1.0.7:

206209:007acd40  00 00 00 00 30 30 30 30  41 47 45 53 41 00 00 00
|....0000AGESA...|
206210-007acd50  56 31 2e 31 2e 30 2e 37  20 20 20 20 00 00 00 00  |V1.1.0.7
....|

Thanks,
Ward.

Re: ASRock E350M1: Linux reports `piix4_smbus 0000:00:14.0: SMBus base address index region 0xcd6 already in use!`

Paul Menzel — 2013-05-22T07:04:25

Am Samstag, den 30.03.2013, 11:38 +0100 schrieb Rudolf Marek:


Starting Linux just with `quiet` on the command line (in GRUB 2), then
the message is different.

        ACPI: resource piix4_smbus [io  0x0b00-0x0b07] conflicts with ACPI region SMB0 [io 0xb00-0xb0b]


Rudolf gave me some more hints for debugging, I paste here.



        $ sudo acpidump > acpi.txt
        $ sudo acpixtract -a acpi.txt
        Acpi table [DSDT] -  10971 bytes written to DSDT.dat
        Acpi table [FACS] -     64 bytes written to FACS.dat
        Acpi table [FACP] -    244 bytes written to FACP.dat
        Acpi table [HPET] -     56 bytes written to HPET.dat
        Acpi table [APIC] -     92 bytes written to APIC.dat
        Acpi table [HEST] -     40 bytes written to HEST.dat
        Acpi table [SSDT] -   5774 bytes written to SSDT1.dat
        Acpi table [SSDT] -    990 bytes written to SSDT2.dat
        Acpi table [SSDT] -     69 bytes written to SSDT3.dat
        Acpi table [RSDT] -     64 bytes written to RSDT.dat

Re: DDR fails on F2A85-M

David Hubbard — 2013-05-22T01:57:29

The board does boot, but only at DDR667. (I tried each option up to DDR1600)


On Tue, May 21, 2013 at 7:19 PM, David Hubbard <
david.c.hubbard+coreboot< at >gmail.com> wrote:

Re: DDR fails on F2A85-M

David Hubbard — 2013-05-22T01:19:01

back

This is a great suggestion.

I have spent a few days studying the AGESA code to find out what
frequencies it tries. I concluded that the built-in AGESA autodetection is
very limited. It may be there is a bug in the AGESA autodetection because
this is not the same code path generally used in vendor BIOSes. The error
messages about missing tables are suspicious. I believe it means AMD has
the motherboard OEM (i.e. Asus) provide parameter tables measured with a
scope that help the timings match the production board.

Specifically I added IDS_HDT_CONSOLE (MEM_FLOW, "MemPPSCFlow enter "
__FILE__ ":%d\n", __LINE__); and IDS_HDT_CONSOLE (MEM_FLOW, "MemPPSCFlow
exit " __FILE__ ":%d\n", __LINE__); to the function MemPPSCFlow() in
src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mp.c



I attempted setting BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT and
BLDCFG_MEMORY_CLOCK_SELECT:
diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c
b/src/mainboard/asus/f2a85-m/buildOpts.c
index 7f893f9..b9346b7 100644
--- a/src/mainboard/asus/f

Re: Recording the LinuxTag talks

Carl-Daniel Hailfinger — 2013-05-21T23:49:26

Am 21.05.2013 17:45 schrieb Peter Stuge:

Will bring my mini-tripod, but I lack a suitable camera.

Regards,
Carl-Daniel

Re: Recording the LinuxTag talks

Peter Stuge — 2013-05-21T15:45:12

As far as I know nobody has either tripod or camera. If you have one,
bring it to LinuxTag. Thanks!


//Peter

Re: Recording the LinuxTag talks

Christian Gmeiner — 2013-05-21T14:34:24

2013/5/21 Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006< at >gmx.net>:

that would be great!
--
Christian Gmeiner, MSc

Recording the LinuxTag talks

Carl-Daniel Hailfinger — 2013-05-21T13:11:44

Hi,

would someone please be so kind and record the coreboot talks at
LinuxTag? A few of my colleagues can't be at LinuxTag, but they have
expressed interest in watching the talks if any recording is made available.

Thanks in advance!

Regards,
Carl-Daniel

S3 fails to suspend after wake up from USB keyboard

WANG Siyuan — 2013-05-21T10:36:55

Hi,
I am trying to debug an issue on Parmer.
1) use "pm-suspend" to suspend.
2) use USB keyboard to wake up.
3) use "pm-suspend" to suspend. FAIL To SUSPEND.

After wake up by USB keyboard, I got some errors in dmesg:
[   55.585935] Disabling IRQ #9

I don't know why this is happened. It seems that ACPI method (_PTS,
_WAK) have nothing to do with suspend and wake up.

Does anybody can help me?
1) What is the workflow of USB keyboard wake up from S3?
2) What are differences between power button wake up and USB keyboard wake up?

dmesg:
[   55.585874] irq 9: nobody cared (try booting with the "irqpoll" option)
[   55.585880] Pid: 691, comm: X Tainted: P           O 3.6.11-1-ARCH #1
[   55.585882] Call Trace:
[   55.585884]  <IRQ>  [<ffffffff810daffd>] __report_bad_irq+0x3d/0xe0
[   55.585895]  [<ffffffff810db2f3>] note_interrupt+0x1a3/0x1f0
[   55.585899]  [<ffffffff810e1bdf>] ? rcu_process_callbacks+0xaf/0x5b0
[   55.585903]  [<ffffffff810d8bcf>] handle_irq_event_percpu+0xbf/0x260
[   55.585907]  [<ffffffff81

Re: Exposing performance data to user space/systemd

Christian Gmeiner — 2013-05-21T10:35:21

Hi Paul


The biggest problem is the defined interface between the coreboot and systemd.


In the next weeks I will find some time for some coreboot work and maybe I will
get something up and running.

greets
--
Christian Gmeiner, MSc

Re: Trying to get coreboot running on VIA EPIA-M (lzma: Decoding error = 1)

ron minnich — 2013-05-20T17:02:41

if you ever see an lzma issue turn off payload compression. It's a
quick easy test to see if there is something else going on -- like,
bad memory configuration, which is always an issue with these boards.

ron

Re: Trying to get coreboot running on VIA EPIA-M (lzma: Decoding error = 1)

Marius Schäfer — 2013-05-20T16:18:20

Ok, this change doesn't seem to be in my tree.
I was in the thought that by a git clone I get all the latest and
greatest stuff.

Marius

2013/5/20 Patrick Georgi <patrick< at >georgi-clan.de>

Re: Trying to get coreboot running on VIA EPIA-M (lzma: Decoding error = 1)

Patrick Georgi — 2013-05-20T15:46:22

Am 20.05.2013 17:16, schrieb Marius Schäfer:
That problem looks like the one solved by
33e83caff59f7b6ff2ba62d3b496235ef5c4e543 from 2013-04-08.
Since I can't figure out the revision you used for this build, please
check that this is in.

If that's not the issue (ie. your tree contains this change), please
tell us more about your config, in particular the coreboot revision and
the payload you used.

Regards,
Patrick

Trying to get coreboot running on VIA EPIA-M (lzma:Decoding error = 1)

Marius Schäfer — 2013-05-20T15:16:02

Hello,

I just want to play around with coreboot on my old VIA EPIA-M, as it should
be supportet and a good place to start. I just followed the Build HOWTO.
But I always end up with 'lzma: Decoding error = 1'.
I clonded coreboot from git, in menuconfig I choose the VIA EPIA-M board
and built everything

Thats what I get on the serial console when I try to boot it:

 Enabling mainboard devices
 Enabling shadow ram
vt8623 init starting
Detecting Memory
Number of Banks 04
Number of Rows 0d
Priamry DRAM width08
No Columns 0a
MA type e0
Bank 0 (*16 Mb) 10
No Physical Banks 02
Total Memory (*16 Mb) 20
CAS Supported 2 2.5 3
Cycle time at CL X     (nS)50
Cycle time at CL X-0.5 (nS)60
Cycle time at CL X-1   (nS)75
Starting at CAS 3
We can do CAS 2.5
We can do CAS 2
tRP 3c
tRCD 3c
tRAS 28
Low Bond 00  High Bondb7  Setting DQS delay7avt8623 done
00:06 11 23 31 06 00 30 22 00 00 00 06 00 00 00 00
10:08 00 00 d0 00 00 00 00 00 00 00 00 00 00 00 00
20:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30:00 00 00 00 a0 00 00

Re: Coreboot hackathon hardware

ron minnich — 2013-05-20T14:13:06

x201 might be practical to try, as well as the 230.

Although we have lots of equipment I'd say it would be useful to have
tools and parts you need for your thinkpad work.

ron

Re: Coreboot hackathon hardware

Vladimir 'φ-coder/phcoder' Serbinenko — 2013-05-20T10:24:13


Ok, so it's not worth to take small stuff. What about mobos/laptops? Is
anyone inte3rested in any of ones I enumerated?

Re: Exposing performance data to user space/systemd

Peter Stuge — 2013-05-19T14:30:53

LinuxTag is an exhibition and not really a developer meeting.

Of course developers can meet anyway, but don't assume that
especially much meaningful work can be done.

I suggest to establish contact with all relevant parties and instead
ask if they can join the coreboot developer meeting following LinuxTag.

Keep in mind that this is already very late, because many people are
already travelling to Berlin by now.


//Peter

Exposing performance data to user space/systemd

Paul Menzel — 2013-05-19T13:58:47

Dear coreboot folks,


as LinuxTag approaches and some of the systemd developers are going to
be there, I remembered the discussion how systemd only supports exposing
performance data on EFI systems [1].

Christian already brought up coreboot/SeaBIOS in that discussion. H.
Peter Anvin (Syslinux) also voiced a need for a having that for non-EFI
systems.

Christin, are there any news?

Thanks to the CBMEM console, the cbmem utility can read, and the timer
work, we have performance data available now. If I am not mistaken,
Chrome OS also supports reading these values. So maybe such an interface
could be designed during LinuxTag and implemented afterward.

If I am right about Chrome OS, do the developers have any suggestions?
Are you content with your interface and can it be generalized for
different boot loaders?


Thanks,

Paul


[1] https://plus.google.com/115547683951727699051/posts/dXs8rrFQkLd
[2] http://www.freedesktop.org/wiki/Software/systemd/BootLoaderInterface/

Re: Coreboot hackathon hardware

Peter Stuge — 2013-05-18T21:43:46

And lots of other stuff. There are also one or two well-stocked shops
in the city.


//Peter