gmane.linux.bios

Re: Adding Supermicro X9SCV-QV4

Nachiketh G — 2012-05-22T10:12:19

Thanks Mike,
That surely has to be a good place to start my work.
Regards,
Nachiketh

On Wed, May 16, 2012 at 11:01 PM, Mike Bishton <mike< at >thebisht.com> wrote:

Re: [SerialICE] Boots from PCI add-on card on Intel ICHs

Alexander Graf — 2012-05-21T06:27:02


On 21.05.2012, at 05:32, ron minnich <rminnich< at >gmail.com> wrote:


If I read the original mail correctly, the method he describes maps the PCI card's option rom _over_ the mainboard one, so it allows for execution of code way earlier.

However, couldn't the normal option rom code path be used to configure the BAR to 0xfff... and trigger a triple fault, rebooting the machine automatically into coreboot? That way you wouldn't have to manually enable coreboot, but only need to have your special PCI card plugged in ;)

Alex

New patch to review for coreboot: ef19ebf abuild:Disable abuild-level parallelism for now

Patrick Georgi — 2012-05-21T18:11:27

Patrick Georgi (patrick< at >georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1037

-gerrit

commit ef19ebfb6133089012cf505018afbafbea7cdb25
Author: Patrick Georgi <patrick< at >georgi-clan.de>
Date:   Mon May 21 20:10:04 2012 +0200

    abuild: Disable abuild-level parallelism for now
    
    It still failed because make touches files it isn't
    supposed to touch.
    
    Change-Id: I5a6ceaa9d5da212c1e34b121cf39fa9d27964747
    Signed-off-by: Patrick Georgi <patrick< at >georgi-clan.de>
---
 util/abuild/abuild |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/util/abuild/abuild b/util/abuild/abuild
index 481fbc2..3639cc6 100755
--- a/util/abuild/abuild
+++ b/util/abuild/abuild
< at >< at > -606,12 +606,12 < at >< at > USE_XARGS=0
 if [ "$cpus" != "1" ]; then
 if [ "$target" = "" ]; then
 # Test if xargs supports the non-standard -P flag
-echo | xargs -P 0$cpus -n 1 echo 2>/dev/null >/dev/null && USE_XARGS=1
+# FIXME: disabled until we managed to eli

Patch merged into coreboot/master: a5a5432 Fix Persimmonbuild without S3.

2012-05-21T17:10:24

the following patch was just integrated into master:
commit a5a543259f455c6d99cf1a8e69cd12cb4bafee20
Author: Marc Jones <marc.jones< at >se-eng.com>
Date:   Tue May 15 16:08:24 2012 -0600

    Fix Persimmon build without S3.
    
    In the heap function, only check for S3 check when it is built in
    with CONFIG_HAVE_ACPI_RESUME.
    
    Change-Id: I439275a4e1b7b446b499bcf90c925785a14b980d
    Signed-off-by: Marc Jones <marc.jones< at >se-eng.com>

Build-Tested: build bot (Jenkins) at Wed May 16 00:37:02 2012, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer< at >coreboot.org> at Thu May 17 20:08:20 2012, giving +2
See http://review.coreboot.org/1034 for details.

-gerrit

New patch to review for coreboot: 52e4920 Converted theFRAMEBUFFER_VESA_MODE to a choice.

Steve Goodrich — 2012-05-21T16:45:13

Steve Goodrich (steve.goodrich< at >se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1036

-gerrit

commit 52e492016ac13ac1190cb3e70975cfedde5e87a4
Author: Steve Goodrich <steve.goodrich< at >se-eng.com>
Date:   Fri May 18 11:18:47 2012 -0600

    Converted the FRAMEBUFFER_VESA_MODE to a choice.
    
    Being a diligent soul, I changed the "enter a numeric value for the
    mode you want" option to a choice of common modes.  New modes can be
    added quite easily.
    
    Change-Id: I8cf4572c2d36ced6549541ec173c0c02d8eaca4a
    Signed-off-by: Steve Goodrich <steve.goodrich< at >se-eng.com>
---
 src/Kconfig |  129 +++++++++++++++++++++++++++++++++++++++++++++++++++++++---
 1 files changed, 122 insertions(+), 7 deletions(-)

diff --git a/src/Kconfig b/src/Kconfig
index a5a0f00..717146d 100644
--- a/src/Kconfig
+++ b/src/Kconfig
< at >< at > -151,7 +151,7 < at >< at > config INCLUDE_CONFIG_FILE
     coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304,

Re: [SerialICE] Boots from PCI add-on card on Intel ICHs

ron minnich — 2012-05-21T15:55:52


ah, somehow I missed that, it is very cool.

ron

Trac reminder: list of new ticket(s)

coreboot tracker — 2012-05-21T14:00:01

Re: [SerialICE] Boots from PCI add-on card on Intel ICHs

Patrick Georgi — 2012-05-21T06:32:09

Am Mo 21 Mai 2012 05:32:42 CEST schrieb ron minnich:
But only after the PC BIOS did its work.
This trick exploits that some chipsets allow PCI devices to respond to 
the system firmware region (4gb-flashsize), so it's coreboot running 
from the plugin card.


Patrick

Re: [SerialICE] Boots from PCI add-on card on Intel ICHs

ron minnich — 2012-05-21T03:32:42

Maybe I misunderstand, but this is how Etherboot originally worked:
flash a new expansion rom onto, e.g., a 3c905 and that could take over
the boot process.

ron

Re: Boots from PCI add-on card on Intel ICHs

Peter Stuge — 2012-05-20T12:43:03

They don't have a flash chip.


//Peter

Re: Boots from PCI add-on card on Intel ICHs

Oliver Schinagl — 2012-05-20T12:18:23

Hi

This sounds extremly interesting! Assuming this only works with PCI and 
not PCI-e, would it also work on wifi mini-pci cards? As you mention 
laptop's specifically, I think most cards available are wifi cards.

Oliver

On 20-05-12 10:23, Kyösti Mälkki wrote:

Boots from PCI add-on card on Intel ICHs

Kyösti Mälkki — 2012-05-20T08:23:07

Hi

I did not find this method of bypassing the mainboard flash chip and
booting from PCI add-on card documented or discussed before. The nice
think in this is that neither mainboard or its flash needs to be
modified. Good news in the case of a soldered flash and this method may
work with mini-PCI slots on laptops too.

For pre-ICH6 the key is in subtractive PCI decode. This has been
supported in 82801 chipset from the early days and is briefly documented
in ICH3 datasheet [1], see 5.1.1. PCI Bus interface. This decode mode is
on by default and there is no documentation of a hw bootstrap that could
disable it.

For ICH7 onwards there are HW bootstraps to select between LPC/SPI/PCI.
If you don't know where the bootstraps are, go with SPI and forget about
this PCI add-on boot.


To try this, I have modified a PCI PATA-RAID card as follows: I cut the
PCI RST# signal from card edge to controller, put a jumper to close it
for normal boots and placed a weak 10kOhm pull-up to Vio on the chip
side.

With this I have

Re: Adding Supermicro X9SCV-QV4

Mike Bishton — 2012-05-16T17:31:36

Nachiketh,

That board is very similar to the Emerald Lake (2) CRB which was 
recently added to coreboot, I would start there.

This board is special because even though it's marketed as a server 
motherboard, it is actually based on the mobile platform.

Hope it helps,
Mike


On 5/16/2012 11:25 AM, Nachiketh G wrote:

Re: Support of the MS-7091 mainboard

Peter Stuge — 2012-05-18T21:55:51

Hello Paul,

Paul Du wrote:


It's not supported. I don't believe there is much documentation for
the 915 chipset, and the platform is quite old. Experience has shown
that a skilled developer will spend at least one year on reverse
engineering and re-engineering the code required to initialize an
unsupported and undocumented chipset, assuming that various
electronic engineering tools are readily available.

It can be fun if you are in need of a new project.


//Peter

Support of the MS-7091 mainboard

Paul Du — 2012-05-18T21:13:04

Hello,I would like to know if my motherboard is or could be supported by coreboot. Thanks :)I was inspired from http://www.coreboot.org/pipermail/coreboot/2010-April/057128.html because I didn't find the answer of this mail so sorry if you've already answer for this motherboard.( Sorry if I didn't do the right things, it's my first mailing list. )
Step 1:My motherboard is a MSI-7091 (OEM-Board by MEDION) socket 775.The CPU is an Intel Pentium 4 524 3.06 Ghz with Hyperthreading.I found the Host bridge : Intel Corporation 82915G/P/GV/GL/PL/910GL Memory Controller HubThe PCI Bridge : Intel Corporation 82915G/P/GV/GL/PL/910GL PCI Express Root PortAnother PCI Bridge : Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) PCI Express Port 1A third PCI Bridge : Intel Corporation 82801 PCI BridgeAn ISA Bridge : Intel Corporation 82801FB/FR (ICH6/ICH6R) LPC Interface BridgeA SMBUS : Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) SMBus ControllerMy System Operation is in 64 bits.
Step 2 :-[0000:00]-+-00.0  Int

Re: Adding Supermicro X9SCV-QV4

Peter Stuge — 2012-05-16T16:33:32

No, there is not. You have to develop chipset support from scratch.


//Peter

Re: Adding Supermicro X9SCV-QV4

Nachiketh G — 2012-05-16T16:25:27

Hi,
If there is any particular board supported by coreboot which I can use as
reference for Intel QM67 chip set with the Intel core i5/i7 processor
families.... please let me know. I can use it as a reference to build the
support for the Supermicro motherboard that I have.
Thanks & Regards,
Nachiketh

On Fri, May 11, 2012 at 10:19 AM, Peter Stuge <peter< at >stuge.se> wrote:

New patch to review for coreboot: a5a5432 Fix Persimmonbuild without S3.

Marc Jones — 2012-05-15T22:13:21

Marc Jones (marcj303< at >gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1034

-gerrit

commit a5a543259f455c6d99cf1a8e69cd12cb4bafee20
Author: Marc Jones <marc.jones< at >se-eng.com>
Date:   Tue May 15 16:08:24 2012 -0600

    Fix Persimmon build without S3.
    
    In the heap function, only check for S3 check when it is built in
    with CONFIG_HAVE_ACPI_RESUME.
    
    Change-Id: I439275a4e1b7b446b499bcf90c925785a14b980d
    Signed-off-by: Marc Jones <marc.jones< at >se-eng.com>
---
 src/mainboard/amd/persimmon/agesawrapper.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/amd/persimmon/agesawrapper.c b/src/mainboard/amd/persimmon/agesawrapper.c
index 0d63abb..195ff54 100644
--- a/src/mainboard/amd/persimmon/agesawrapper.c
+++ b/src/mainboard/amd/persimmon/agesawrapper.c
< at >< at > -253,10 +253,12 < at >< at > UINT32 GetHeapBase(
 {
 UINT32 heap;
 
+#if CONFIG_HAVE_APCI_RESUME
 /* Both romstage and ramstage has this S3 detect. */
 if (acpi

Patch merged into coreboot/master: 458c537 Fix fadtlegacy free setting.

2012-05-15T17:18:07

the following patch was just integrated into master:
commit 458c5372d8945badcb47039b4e7622318d3a2611
Author: Marc Jones <marc.jones< at >se-eng.com>
Date:   Sat May 12 09:56:45 2012 -0600

    Fix fadt legacy free setting.
    
    The fadt legacy free logic was backwards.
    
    Change-Id: Ieb21ef335f7514ced70248d0bf8668ddb73cf59f
    Signed-off-by: Marc Jones <marc.jones< at >se-eng.com>

Build-Tested: build bot (Jenkins) at Tue May 15 19:04:24 2012, giving +1
Reviewed-By: Peter Stuge <peter< at >stuge.se> at Tue May 15 01:05:38 2012, giving +2
See http://review.coreboot.org/1030 for details.

-gerrit

Patch merged into coreboot/master: fb5306c Pass IASL toSeaBIOS

2012-05-15T05:01:43

the following patch was just integrated into master:
commit fb5306c489c07395984bcc59115ae0e2d3cb9f7b
Author: Marc Jones <marc.jones< at >se-eng.com>
Date:   Mon May 14 21:06:10 2012 -0600

    Pass IASL to SeaBIOS
    
    Use the coreboot IASL for building SeaBIOS.
    
    Change-Id: Ia6c802b090d53b7fbbc8ddb6edad3de6b822ff41
    Signed-off-by: Marc Jones <marc.jones< at >se-eng.com>

Build-Tested: build bot (Jenkins) at Tue May 15 05:23:54 2012, giving +1
Reviewed-By: Peter Stuge <peter< at >stuge.se> at Tue May 15 07:00:01 2012, giving +2
See http://review.coreboot.org/1033 for details.

-gerrit

Patch merged into coreboot/master: 129d4e6 Fix Cygwinbootblock generation

2012-05-15T05:15:53

the following patch was just integrated into master:
commit 129d4e61e013b9f3ad4f6c13879661e29b47d6b3
Author: Marc Jones <marc.jones< at >se-eng.com>
Date:   Mon May 14 16:20:26 2012 -0600

    Fix Cygwin bootblock generation
    
    Cygwin is case insensitive, so bootblock.s and bootblock.S in the
    same directory cause a build failure. This changes bootblock.S
    to bootblock_inc.S, as it is generated from bootblock_inc.
    crt0.S and crt0.S also had this problem. This changes crt0.S to
    crt0.romstage.S.
    
    Change-Id: I29d230a93b0743e34f11228f9034880ceaf7ab7b
    Signed-off-by: Marc Jones <marc.jones< at >se-eng.com>

Build-Tested: build bot (Jenkins) at Tue May 15 07:08:44 2012, giving +1
Reviewed-By: Peter Stuge <peter< at >stuge.se> at Tue May 15 07:03:28 2012, giving +2
See http://review.coreboot.org/1032 for details.

-gerrit