gmane.comp.emulators.kvm.devel

Re: [PATCH v3 03/13] nEPT: Add EPT tables support to paging_tmpl.h

Xiao Guangrong — 2013-05-21T11:05:19

Okay.

The functions used to translate L2's gva to L1's gpa are paging32_gva_to_gpa_nested
and paging64_gva_to_gpa_nested which are created by PTTYPE == 32 and PTTYPE == 64.


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Re: [PATCH v3 13/13] nEPT: Inject EPT violation/misconfigration

Xiao Guangrong — 2013-05-21T10:56:09

It is better that set mmu->check_tdp_pte = is_rsvd_bits_set for the
current modes, then this part can be moved to mmu.c


This specified operations can be move to nested_ept_inject_page_fault()?

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Re: I/O port permission bit inheritance between threads

Gleb Natapov — 2013-05-21T10:01:18

The program segfaults on physical hardware:
# ./a.out 
joining
waiting
beeping
Segmentation fault

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Re: I/O port permission bit inheritance between threads

Joerg Roedel — 2013-05-21T09:50:30

Hey Stephen,

On Mon, May 20, 2013 at 02:24:31PM -0700, Stephen Hemminger wrote:

Is this specific to SVM or do you see it on VMX too? My first guess
would be that the KVM instruction emulator does not check to
IO-permissions correctly, but that would affect VMX and SVM.


Joerg


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Re: [PATCH v3 10/13] nEPT: Nested INVEPT

Xiao Guangrong — 2013-05-21T09:16:18

Hmm?

L0 can not always intercept L1's changes due to unsync shadow pages...


So, i can not understand why we need not handle INVEPT.

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Re: [PATCH v3 03/13] nEPT: Add EPT tables support to paging_tmpl.h

Gleb Natapov — 2013-05-21T09:01:02

You can write it down here for future reviewers :)

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Re: [PATCH 0/8] s390/kvm fixes

Gleb Natapov — 2013-05-21T08:56:04

Applied, thanks.


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Re: [PATCH v3 05/13] nEPT: MMU context for nested EPT

Xiao Guangrong — 2013-05-21T08:50:58

That means L1 guest always uses page-walk length == 4? But in your previous patch,
it can be 2.


Hmm? EPT always support NX.


Exactly. :)


I guess we need not care these since the permission of EPT page does not depend
on these.


Hmm, you directly copy the error code from FNAME(walk_addr_generic),
but its format is different and i did not see you cook the error code
in the previous patches.

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Re: [PATCH v3 03/13] nEPT: Add EPT tables support to paging_tmpl.h

Xiao Guangrong — 2013-05-21T08:30:13

Sorry, i misunderstood it. Have found the reason out.



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Re: [PATCH v3 04/13] nEPT: Define EPT-specific link_shadow_page()

Xiao Guangrong — 2013-05-21T08:15:05

The only difference between this function and the current link_shadow_page()
is shadow_accessed_mask. Can we add a parameter to eliminate this difference,
some like:

static void link_shadow_page(u64 *sptep, struct kvm_mmu_page *sp, bool accessed)
{
u64 spte;

spte = __pa(sp->spt) | PT_PRESENT_MASK | PT_WRITABLE_MASK |
       shadow_user_mask | shadow_x_mask;

if (accessed)
spte |= shadow_accessed_mask;

mmu_spte_set(sptep, spte);
}

?

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Re: [PATCH 2/4] KVM/MIPS32: Wrap calls to gfn_to_pfn() with srcu_read_lock/unlock()

Gleb Natapov — 2013-05-21T08:00:47

Should I expect new version, or can I just drop this include from the
patch and apply?

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Re: [PATCH v3 03/13] nEPT: Add EPT tables support to paging_tmpl.h

Xiao Guangrong — 2013-05-21T07:52:12

CMPXHG is only used in FNAME(cmpxchg_gpte), but you commented it later.
Do we really need it?


And the SDM says:

"It uses a page-walk length of 4, meaning that at most 4 EPT paging-structure
entriesare accessed to translate a guest-physical address.", Is My SDM obsolete?
Which kind of process supports page-walk length = 2?

It seems your patch is not able to handle the case that the guest uses walk-lenght = 2
which is running on the host with walk-lenght = 4.
(plrease refer to how to handle sp->role.quadrant in FNAME(get_level1_sp_gpa) in
the current code.)


It seems wrong. The ACC_XXX definition:

#define ACC_EXEC_MASK    1
#define ACC_WRITE_MASK   PT_WRITABLE_MASK
#define ACC_USER_MASK    PT_USER_MASK
#define ACC_ALL          (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)

The bits are different with the bits used in EPT page table, for example,
your code always see that the execution is not allowed.


There are lots of code in paging_tmpl.h depends on PT_ACCESSED_MASK/PT_DIRTY_MASK.
I do not see oth

Re: [PATCH 0/8] s390/kvm fixes

Martin Schwidefsky — 2013-05-21T06:57:34

On Sun, 19 May 2013 11:49:43 +0300
Gleb Natapov <gleb< at >redhat.com> wrote:


Yes.

[PATCH 2/3] powerpc/vfio: Implement IOMMU driver for VFIO

Alexey Kardashevskiy — 2013-05-21T03:33:10

VFIO implements platform independent stuff such as
a PCI driver, BAR access (via read/write on a file descriptor
or direct mapping when possible) and IRQ signaling.

The platform dependent part includes IOMMU initialization
and handling.  This implements an IOMMU driver for VFIO
which does mapping/unmapping pages for the guest IO and
provides information about DMA window (required by a POWER
guest).

Cc: David Gibson <david< at >gibson.dropbear.id.au>
Signed-off-by: Alexey Kardashevskiy <aik< at >ozlabs.ru>
Signed-off-by: Paul Mackerras <paulus< at >samba.org>
---
 Documentation/vfio.txt              |   63 ++++++
 drivers/vfio/Kconfig                |    6 +
 drivers/vfio/Makefile               |    1 +
 drivers/vfio/vfio.c                 |    1 +
 drivers/vfio/vfio_iommu_spapr_tce.c |  377 +++++++++++++++++++++++++++++++++++
 include/uapi/linux/vfio.h           |   34 ++++
 6 files changed, 482 insertions(+)
 create mode 100644 drivers/vfio/vfio_iommu_spapr_tce.c

diff --git a/Documentation/vfio.txt b/Documentation/vfio

[PATCH 3/4] KVM: PPC: Add support for IOMMU in-kernel handling

Alexey Kardashevskiy — 2013-05-21T03:06:46

This allows the host kernel to handle H_PUT_TCE, H_PUT_TCE_INDIRECT
and H_STUFF_TCE requests without passing them to QEMU, which should
save time on switching to QEMU and back.

Both real and virtual modes are supported - whenever the kernel
fails to handle TCE request, it passes it to the virtual mode.
If it the virtual mode handlers fail, then the request is passed
to the user mode, for example, to QEMU.

This adds a new KVM_CAP_SPAPR_TCE_IOMMU ioctl to asssociate
a virtual PCI bus ID (LIOBN) with an IOMMU group, which enables
in-kernel handling of IOMMU map/unmap.

Tests show that this patch increases transmission speed from 220MB/s
to 750..1020MB/s on 10Gb network (Chelsea CXGB3 10Gb ethernet card).

Cc: David Gibson <david< at >gibson.dropbear.id.au>
Signed-off-by: Alexey Kardashevskiy <aik< at >ozlabs.ru>
Signed-off-by: Paul Mackerras <paulus< at >samba.org>

---

Changes:
2013-05-20:
* removed get_user() from real mode handlers
* kvm_vcpu_arch::tce_tmp usage extended. Now real mode handler puts there
translated TCEs

I/O port permission bit inheritance between threads

Stephen Hemminger — 2013-05-20T21:24:31

ioperm() inheritance across threads is different in KVM then when run
on physical hardware.  The following program runs on physical hardware
but get SEGV under KVM.

It appears that the I/O permission bits are not shared between threads
in the same way.

/* Original Copyright 2011, Kees Cook <kees< at >outflux.net>, License: GPLv2 */
#include <unistd.h>
#include <stdio.h>
#include <pthread.h>
#include <sys/io.h>

static void *beep(void *arg)
{
unsigned char bits;

fprintf(stderr, "waiting\n");
sleep(1);

fprintf(stderr, "beeping\n");
/* turn on speaker */
bits = inb(0x61);
bits |= 3;
outb(bits, 0x61);

/* set 1000 Hz frequency */
bits = 0xA9;
outb(bits, 0x42);
bits = 0x04;
outb(bits, 0x42);

/* listen to the beep */
sleep(4);
fprintf(stderr, "done\n");

return NULL;
}

int main() {
pthread_t tid;
unsigned char orig;

if (pthread_create(&tid, NULL, &beep, NULL)) {
perror("pthread");
return 1;
}

/* gain access to speaker control port */
if (ioperm(0x61, 0x61, 1) < 0) {
perror("0x61");

[PATCH v3 2/5] mips/kvm: Fix ABI for use of 64-bit registers.

David Daney — 2013-05-20T21:01:23

From: David Daney <david.daney< at >cavium.com>

All registers are 64-bits wide, 32-bit guests use the least
significant portion of the register storage fields.

Signed-off-by: David Daney <david.daney< at >cavium.com>
---
 arch/mips/include/asm/kvm.h | 16 +++++++++++-----
 1 file changed, 11 insertions(+), 5 deletions(-)

diff --git a/arch/mips/include/asm/kvm.h b/arch/mips/include/asm/kvm.h
index 0e8f565..86812fb 100644
--- a/arch/mips/include/asm/kvm.h
+++ b/arch/mips/include/asm/kvm.h
< at >< at > -18,12 +18,18 < at >< at >
 #define N_MIPS_COPROC_REGS      32
 #define N_MIPS_COPROC_SEL   8
 
-/* for KVM_GET_REGS and KVM_SET_REGS */
+/*
+ * for KVM_GET_REGS and KVM_SET_REGS
+ *
+ * If Config[AT] is zero (32-bit CPU), the register contents are
+ * stored in the lower 32-bits of the struct kvm_regs fields and sign
+ * extended to 64-bits.
+ */
 struct kvm_regs {
-__u32 gprs[32];
-__u32 hi;
-__u32 lo;
-__u32 pc;
+__u64 gprs[32];
+__u64 hi;
+__u64 lo;
+__u64 pc;
 
 __u32 cp0reg[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
 };

Re: [Qemu-devel] VFIO VGA test branches

Knut Omang — 2013-05-20T21:08:59

Hmm, seems you have been more lucky with the choice of chipset/CPU than
me - all my tests are also with these branches but on Intel...

Knut



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Re: [PATCH 00/18] KVM/MIPS32: Support for the new Virtualization ASE (VZ-ASE)

David Daney — 2013-05-20T18:58:17

FWIW:  The MIPS-VZ architecture module requires the presence of CP0 
scratch registers that can be used for this in the exception handlers 
without having to worry about using these implementation dependent 
registers.  For the trap-and-emulate only version, there really is no 
choice other than to re-purpose some of the existing CP0 registers.

David Daney

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Re: [PATCH 00/18] KVM/MIPS32: Support for the new Virtualization ASE (VZ-ASE)

Maciej W. Rozycki — 2013-05-20T18:36:23


 That's rather risky as the implementation of this register (and its 
presence in the first place) is processor-specific.  Do you maintain a 
list of PRId values the use of this register is safe with?

  Maciej
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Re: [PATCH 00/18] KVM/MIPS32: Support for the new Virtualization ASE (VZ-ASE)

Sanjay Lal — 2013-05-20T17:34:24

On May 20, 2013, at 10:29 AM, David Daney wrote:



arch/mips/kvm/kvm_locore.S


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